KR20090076142A - Method for manufacturing semiconductor device - Google Patents

Abstract

A manufacturing method of the semiconductor device is provided, which increases the charge mobility by making the gate spacer out of the material fitting for the performance characteristic of each transistor. The gate(106) is formed at the upper part of the semiconductor substrate(100) classified into the cell area(A), the NMOS area(B), and the PMOS area(C). The first spacer stuff film is formed at the upper part of the whole surface. The first spacer stuff film of the NMOS area is removed. The second spacer stuff film is formed at the upper part of the whole surface. The second spacer stuff film is front-etched and the first gate spacer(114) is formed in the gate sidewall of the NMOS area. The first spacer stuff film of the PMOS area is front-etched and the second gate spacer(118) is formed in the gate sidewall of the PMOS area.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a semiconductor device capable of increasing charge mobility by forming gate spacers of an NMOS transistor and a PMOS transistor formed in a peripheral circuit region, respectively, with a material suitable for operating characteristics of each transistor. It is a technique relating to the manufacturing method of.

In general, to increase the speed of devices such as transistors that make up integrated circuits, integrated circuit manufacturers have reduced device size. Smaller devices can operate at higher speeds, but the secondary performance factors of the device, such as reducing the source / drain breakdown voltage, increasing junction capacitance, and threshold voltage instability, have a negative effect on the transistor performance called the short channel effect. .

The technology to increase device operating speed has shifted from reducing device size to improving charge mobility and reducing short channel effects. Charge mobility can be improved by straining the devices.

In order to improve the operating characteristics of the NMOS and PMOS transistors when stress is applied to the transistors, tensile stress and compressive stress should be applied based on the channel direction, respectively.

To this end, when forming the gate spacer, the spacer material and deposition conditions are controlled to apply different stresses according to the type of transistor. That is, in the case of the NMOS transistor, the tensile stress is applied to the substrate, and in the case of the PMOS transistor, the charge mobility is increased when the compressive stress is applied to the substrate, thereby improving operation characteristics.

1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1, an isolation layer 14 defining an active region 12 is formed in a semiconductor substrate 10 divided into a cell region A and a peripheral circuit region D. FIG.

In this case, the peripheral circuit region D is divided into an NMOS region B in which an NMOS transistor is to be formed and a PMOS region C in which a PMOS transistor is to be formed.

Next, a gate insulating film (not shown) is formed on the semiconductor substrate 10. Next, a gate polysilicon layer 16a, a gate electrode layer 16b, and a gate hard mask layer 16c are formed on the gate insulating layer.

Next, the stacked structure is etched by a photolithography process using a gate mask to form gates 16 in the cell region A, the NMOS region B, and the PMOS region C, respectively.

Subsequently, a spacer material film (not shown) is formed on the entire surface of the semiconductor substrate 10 on which the gate 16 is formed while the peripheral circuit region D is exposed by a low pressure deposition method.

The first gate spacer 18 is formed on the sidewalls of the gate 16 of the NMOS region B and the PMOS region C by etching the spacer material layer.

Here, when the first gate spacer 18 is formed of a nitride film having a tensile stress, the characteristics of the NMOS transistor are improved, but the characteristics of the PMOS transistor are deteriorated.

On the other hand, when the first gate spacer 18 is formed of an oxide film having a compressive stress, the characteristics of the PMOS transistor are improved, but the characteristics of the NMOS transistor are deteriorated.

Next, an insulating film for a spacer (not shown) is formed on the entire surface of the semiconductor substrate 10 on which the gate 16 is formed while the cell region A is exposed. Next, an interlayer insulating film 20 is formed on the spacer insulating film.

Next, the interlayer insulating layer 20 is etched by a photolithography process using a landing plug contact mask to form a landing plug contact hole (not shown) that exposes the semiconductor substrate 10. At the same time, the second gate spacer 22 is formed on the sidewall of the gate 16 of the cell region A.

Next, a conductive film (not shown) is formed on the interlayer insulating film 20 including the landing plug contact hole, and the landing plug 24 is formed by planarizing the conductive film until the gate 16 is exposed.

The above-described method of manufacturing a semiconductor device according to the related art has a problem in that the operation characteristics of any one of the NMOS and PMOS transistors are deteriorated by forming the gate spacers of the NMOS and PMOS transistors formed in the peripheral circuit region with one material film of an oxide film or a nitride film. There is this.

An object of the present invention is to increase charge mobility by forming gate spacers of an NMOS transistor and a PMOS transistor formed in a peripheral circuit region, respectively, with a material suitable for operating characteristics of each transistor.

A method of manufacturing a semiconductor device according to the present invention includes forming a gate on a semiconductor substrate divided into a cell region, an NMOS region, and a PMOS region; Forming a material film for the first spacer on the entire surface; Removing the material film for the first spacer in the NMOS region; Forming a material film for the second spacer on the entire surface; Forming a first gate spacer on the gate sidewall of the NMOS region by etching the entire surface of the second spacer material layer; And etching the entire surface of the first spacer material layer in the PMOS region to form a second gate spacer on the sidewall of the gate of the PMOS region.

Here, the first spacer material film is formed of an oxide film having a compressive stress, the first spacer material film removal process is performed by a wet etching method, and the second spacer material film is a nitride film having a tensile stress. It is characterized by forming.

And forming a buffer film over the entire surface after the second gate spacer forming step; Removing the buffer layer and the material layer for the second spacer while the cell region is exposed; Forming a material layer for the third spacer on the entire surface; Forming an interlayer insulating film on the third spacer material film; Selectively etching the interlayer insulating layer to form a landing plug contact hole exposing the semiconductor substrate in the cell region; And filling a conductive film in the landing plug contact hole to form a landing plug.

The buffer layer may be formed of an oxide layer, the third spacer material layer may be formed of a nitride layer, and a third gate spacer may be formed on sidewalls of the gate of the cell region during the landing plug contact hole forming process. do.

The present invention provides an effect of increasing charge mobility by forming gate spacers of an NMOS transistor and a PMOS transistor formed in a peripheral circuit region, respectively, with a material suitable for operating characteristics of each transistor.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A to 2M are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, an isolation layer 104 defining an active region 102 is formed in a semiconductor substrate 100 separated into a cell region A and a peripheral circuit region D. FIG.

Here, the cell region A represents a region where a memory cell is to be formed, and the peripheral circuit region D represents a region where an element constituting a peripheral circuit except for the memory cell is to be formed.

In this case, the peripheral circuit region D includes an NMOS region B and a PMOS region C in which NMOS and PMOS transistors constituting the peripheral circuit are to be formed.

Next, a gate insulating film (not shown) is formed on the semiconductor substrate 100, and a gate polysilicon layer (not shown), a gate electrode layer (not shown), and a gate hard mask layer (not shown) are formed on the gate insulating film. do.

Next, the gate hard mask layer, the gate electrode layer, and the gate polysilicon layer are etched by a photolithography process using a gate mask. Accordingly, the gate 106 including the gate polysilicon layer pattern 106a, the gate electrode layer pattern 106b, and the gate hard mask layer pattern 106c in the cell region A, the NMOS region B, and the PMOS region C. ) Are formed respectively.

Referring to FIG. 2B, the first spacer material film 108 is formed on the semiconductor substrate 100 on which the gate 106 is formed.

Here, the first spacer material film 108 is for forming a gate spacer of a PMOS transistor to be formed in a subsequent process, and is preferably formed of an oxide film having a compressive stress.

Next, a first photoresist layer pattern 110 exposing the NMOS region B is formed on the first spacer material layer 108.

Referring to FIG. 2C, the first spacer material film 108 exposed by the first photosensitive film pattern 110 is removed.

In this case, the process of removing the first spacer material film 108 may be performed by a wet etch method.

Next, the first photosensitive film pattern 110 is removed.

Referring to FIG. 2D, a second spacer material film 112 is formed over the entire surface.

Here, the second spacer material film 112 is for forming a gate spacer of an NMOS transistor to be formed in a subsequent process, and is preferably formed of an insulating film having a tensile stress.

Referring to FIG. 2E, the first spacer spacer 114 may be etched back to form the first gate spacer 114 on the sidewall of the gate 106 of the NMOS region B. Referring to FIG.

At this time, during the etching process of the second spacer material film 112, the second spacer material film 112 of the cell region A and the PMOS region C is also removed.

Then, a source / drain ion implantation process is performed to form a source / drain region (not shown) in the active region 102 exposed at both sides of the gate 106 of the NMOS region B. This completes the NMOS transistor.

Referring to FIG. 2F, a second photosensitive film pattern 116 exposing the PMOS region C is formed on the entire surface.

Referring to FIG. 2G, the first spacer material layer 108 exposed by the second photoresist pattern 116 is etched back to the second gate spacer on the sidewall of the gate 106 of the PMOS region C. Referring to FIG. Form 118.

Next, a source / drain ion implantation process is performed to form a source / drain region (not shown) in the active region 102 exposed at both sides of the gate 106 of the PMOS region C. Thus, the PMOS transistor is completed.

Next, the second photosensitive film pattern 116 is removed.

Referring to FIG. 2H, the buffer film 120 is formed over the entire surface.

Here, the buffer film 120 is preferably formed of an oxide film. The buffer layer 120 may not directly apply stress to the semiconductor substrate 100 exposed in the NMOS region B and the PMOS region C by the third spacer material layer to be formed in a subsequent process. It acts as a buffer.

In addition, when the interlayer insulating layer to be formed in a subsequent process is formed of a BPSG material film including boron (B), the buffer layer 120 may prevent a phenomenon in which boron penetrates into the surface of the semiconductor substrate 100.

Referring to FIG. 2I, a third photoresist pattern 122 is formed on the entire surface to expose the cell region C. Referring to FIG.

Referring to FIG. 2J, the first spacer material film 108 exposed by the third photoresist pattern 122 is removed.

In this case, the first spacer material layer 108 may be removed by a wet etching method.

Next, the third photosensitive film pattern 122 is removed.

Referring to FIG. 2K, the third spacer material layer 124 is formed on the entire surface.

The third spacer material film 124 may be formed of a nitride film.

Referring to FIG. 2L, an interlayer insulating layer 126 is formed on the third spacer material layer 124.

Referring to FIG. 2M, a landing plug contact hole (not shown) exposing the semiconductor substrate 100 may be formed by selectively etching the interlayer insulating layer 126 of the cell region C. Referring to FIG.

At the same time, the third gate spacer 124a is formed on the sidewall of the gate 106 of the cell region C.

Next, a conductive film (not shown) is formed on the interlayer insulating film 126 including the landing plug contact hole.

Next, the insulating interlayer 126 is planarized and etched until the gate 106 is exposed to form the landing plug 128.

That is, the present invention forms a gate spacer having a tensile stress in an NMOS transistor in a peripheral circuit region, and forms a gate spacer having a compressive stress in a PMOS transistor, thereby transferring charges by an external force applied to the substrate by each gate spacer. By increasing the degree, the operating characteristics of the NMOS and PMOS transistors can be improved.

1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.

2A to 2M are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Claims (8)

Forming a gate over the semiconductor substrate divided into a cell region, an NMOS region, and a PMOS region; Forming a material film for the first spacer on the entire surface; Removing the material film for the first spacer in the NMOS region; Forming a material film for the second spacer on the entire surface; Forming a first gate spacer on the gate sidewall of the NMOS region by etching the entire surface of the second spacer material layer; And Etching the entire surface of the first spacer material layer in the PMOS region to form a second gate spacer on the gate sidewall of the PMOS region Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the first spacer material film is formed of an oxide film having a compressive stress. The method of claim 1, wherein the removing of the material layer for the first spacer is performed by a wet etching method. The method of claim 1, wherein the second spacer material film is formed of a nitride film having a tensile stress. The method of claim 1, further comprising after forming the second gate spacer. Forming a buffer film over the entire surface; Removing the buffer layer and the material layer for the second spacer while the cell region is exposed; Forming a material layer for the third spacer on the entire surface; Forming an interlayer insulating film on the third spacer material film; Selectively etching the interlayer insulating layer to form a landing plug contact hole exposing the semiconductor substrate in the cell region; And Filling a conductive film in the landing plug contact hole to form a landing plug Method of manufacturing a semiconductor device further comprising. The method of claim 5, wherein the buffer film is formed of an oxide film. The method of claim 5, wherein the third spacer material film is formed of a nitride film. The method of claim 5, wherein a third gate spacer is formed on the gate sidewall of the cell region during the landing plug contact hole forming process.

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