KR20090073493A - Vertical image sensor and method for manufacturing the sensor - Google Patents

Abstract

A vertical image sensor and a method for manufacturing the sensor are provided to minimize the scattering of the light by defects existing in the interface of the interlayer insulating films by filling holes with an interlayer insulating film which has same refractive index as a micro lens. A plurality of photo diodes(152) is formed perpendicularly in a photodiode region of a semiconductor substrate(150). The etch stop layer(158) is formed on an upper portion of the photo diode. A plurality of inter-layer insulating films(160,162,164,166) is formed on the etch stop layer. By using a photograph and etching process, the inter-layer insulating films of photodiode are etched to form a hole. The light transmitting layer(190) is formed in the hole. The refractive index of the light transmitting layer is same as that of the refractive index of the micro lens.

Description

Vertical image sensor and method for manufacturing the sensor

TECHNICAL FIELD The present invention relates to an image sensor, and more particularly, to a CMOS vertical image sensor and a manufacturing method thereof.

In general, CMOS image sensors are semiconductor devices that convert an optical image into an electrical signal. Among them, a charge coupled device (CCD) includes an individual metal-oxide silicon (MOS) capacitor. A device in which charge carriers are stored and transported in a capacitor while being in close proximity to one another.

On the other hand, the CMOS image sensor is connected to and connected to the number of photo diodes (PD) as many as the number of pixels using CMOS technology using a control circuit and a signal processing circuit as peripheral circuits. It is a device that creates transistors that open and close and detects optical signals of red, green, and blue in sequence using transistors and outputs them by a switching method.

The CMOS image sensor described above has many advantages such as low power consumption, low process cost, and high level of integration. In particular, recent technological advances have made CMOS image sensors a viable alternative to charge-coupled devices (CCDs) in many applications. CMOS image sensors are classified into 3T type, 4T type, and 5T type according to the number of transistors. Type 3T consists of one photodiode and three transistors, and type 4T consists of one photodiode and four transistors. In the case of such a CMOS image sensor, transistors for driving and the like are formed horizontally, including a photodiode, and unit pixels are formed by using color filters of red (R), green (G), and blue (B). It will detect the light of color. At this time, in the CMOS image sensor, since one unit pixel must include all of the red (R), green (G), and blue (B) color filters formed in a plane, the size becomes larger. Therefore, in the case of the general CMOS image sensor, the pixel integration degree is lowered. As such, a vertical image sensor has been proposed to improve the problem of lowering the density of a general image sensor. In the vertical image sensor, red / green / blue photodiodes are vertically structured to detect red (R), green (G), and blue (B) signals per unit pixel.

Hereinafter, a conventional vertical CMOS image sensor will be described with reference to the accompanying drawings.

FIG. 1 is a plan view illustrating a general vertical CMOS image sensor, and FIG. 2 is a structural cross-sectional view taken along line II ′ of FIG. 1.

Referring to FIGS. 1 and 2, the photodiode of the conventional vertical image sensor 10 has a well shape, and red (R) and green (G) can detect all signals per unit pixel. ), Blue (B) photodiodes 3, 6, and 8 are formed vertically. Here, the conventional vertical image sensor 10 includes a pixel region 20 in which a plurality of unit pixels are formed, elements (not shown) formed in the pixel region 20, and each photodiode 3, 6, and 8. It is largely divided into a peripheral region 40 including a predetermined terminal and grounding terminals to which a signal is applied. The conventional vertical CMOS image sensor includes a silicon semiconductor substrate 1, a first photodiode 3 sensing red light formed at a predetermined portion of the semiconductor substrate 1, and a semiconductor substrate 1. The first epitaxial layer 4, the second photodiode 6 formed on the first epitaxial layer 4 and overlapping the first photodiode 3, and on the first epitaxial layer 4. A second epitaxial layer 7 formed on the second epitaxial layer 7, a third photodiode 8 overlapping with the second photodiode 6 on the second epitaxial layer 7, and each silicon substrate and the first and second epitaxial layers. First to third dummy moats 9, 19, and 29 formed at portions spaced from the corresponding photodiodes of layers 4 and 7.

3 is a cross-sectional view of a unit pixel of another general vertical CMOS image sensor.

Comparing the image sensor shown in FIG. 3 with the image sensor shown in FIG. 2, layer 105 corresponds to layers 1, 4, and 9, and red (R), green (G), and blue (B). Photodiode 110 corresponds to photodiode 3, 6 and 8, respectively.

Referring to FIG. 3, the gate pattern 112 for signal processing includes a gate and a gate insulating layer, and the etch stop layer 116 serves to block etching in an etching process for forming a contact. The spacer 114 is formed on the side of the gate pattern 112. The interlayer insulating layers 118, 120, 122, and 124 for signal transmission and device protection are stacked to form metal wires 130, 132, and 134, vias, and the like.

In general, when fabricating the image sensor as described above, as the metal layer increases, the interface between the interlayer insulating films increases. Since the surface of the interlayer insulating film is formed by a chemical mechanical polarization (CMP) process, the surface of the interlayer insulating film has a large number of defects, and light is incident on the area 140, causing various scattering to deteriorate the sensitivity of the image sensor. There is a problem. In order to reduce this, the hydrogen anneal (hydrogen anneal) is used, but the improvement effect is very minimal.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a vertical image sensor and a method of manufacturing the same, which can increase light incident efficiency to a photodiode.

According to an aspect of the present invention, there is provided a method of manufacturing a vertical image sensor, the method comprising: vertically stacking a plurality of photodiodes in a photodiode region on a semiconductor substrate, and forming an etch stop layer on the top photodiode Forming a hole on the etch stop layer, forming a plurality of interlayer insulating films on the etch stop layer, and etching the interlayer insulating films of the photodiode region to the etch stop layer using a photolithography and etching process; It is preferable that the light transmitting layer is formed in the hole.

Alternatively, an image sensor according to the present invention for achieving the above object, a plurality of photodiodes formed by being stacked vertically on the photodiode region on the semiconductor substrate, a gate pattern formed in the transistor region, and formed on the uppermost photodiode And an etch stop layer, a plurality of interlayer insulating layers formed by vertically stacking an upper portion of the gate pattern in the transistor region, and a light transmitting layer formed on the etch stop layer in the photodiode region. Vertical image sensor.

In the vertical image sensor according to the present invention and a method of manufacturing the same, a hole is formed by selectively etching only the interlayer insulating layers present in the photodiode region, and a film having the same refractive index as that of the microlens is formed in the hole. Since it can be effectively filled by a process, etc., it is possible to minimize and reduce the scattering of light due to defects present in the interface between the interlayer insulating film has the effect of increasing the light collection efficiency.

Hereinafter, a method of manufacturing a vertical image sensor according to the present invention will be described with reference to the accompanying drawings.

4A and 4B are cross-sectional views of a vertical image sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, an image sensor is divided into a transistor region 200 in which a transistor is formed and a photodiode region 210 in which a photodiode is formed. Here, the photodiode region 210 means a path through which light is incident on the photodiode 152. A plurality of photodiodes 152 are vertically stacked on the photodiode region 210. The plurality of photodiodes 152 are formed on the semiconductor substrate and the epi layer 150 as photodiodes of red (R: red), green (G: green), and blue (B: blue). That is, vertical photodiodes 152 may be generated in the photodiode region 210 through continuous epitaxial layer formation and ion implantation on the silicon wafer. Since the layer 150 corresponds to the layer 150 shown in FIG. 3 and the photodiode 152 corresponds to the photodiode 110 shown in FIG. 3, a detailed description thereof will be omitted.

After forming the vertical photodiode 152, a gate pattern 154 having a structure in which a gate insulating layer (not shown) and a polysilicon gate (not shown) are stacked on the layer 150 is formed. The spacer 156 is formed on the side of 154. The gate pattern 154 and the spacer 156 may also be formed by a general process, and the transistors of the image sensor are completed by performing the following general process.

An etch stop layer 158 is formed on the photodiode 152 at the top of the photodiode. That is, as shown in FIG. 4A, the etch stop layer 158 may be formed in the transistor region 200 as well as the photodiode region 210. However, the etch stop layer 158 may not be formed in the transistor region 200, but may be selectively formed only in the photodiode region 210. The etch stop layer 158 performs an etch stop function in an etching process for forming a contact.

As shown in FIG. 3, the image sensor illustrated in FIG. 4A includes a plurality of interlayer insulating layers 160, 162, and 164 formed on an upper front surface of the etch stop layer 158 of the transistor region 200 and the photodiode region 210. And 166). The interlayer insulating layers 160, 162, 164, and 166 serve as signal transmission and device protection. In the process of forming the plurality of interlayer insulating layers 160, 162, 164, and 166, the metal wires 170, 172, and 174 or the contact plug (not shown) are formed by a conventional process.

Thereafter, only the interlayer insulating layers 160, 162, 164, and 166 formed on the photodiode region 210 are etched and removed to the etch stop layer 158 by using a photo and etching process, thereby removing the hole 180. Form.

In some embodiments, the interlayer insulating layers 160, 162, 164, and 166 may be formed of only four layers as shown in FIG. 4A, and may be formed with fewer or more. Therefore, the thickness of the etch stop layer 158 may be set according to the thickness of the interlayer insulating layer being stacked. After forming the approximately top metal, the total thickness of the interlayer insulating films 160, 162, 164, and 166 is about 3 mu m. In this case, when the etching gas having the selectivity of 100: 1 is used, the etch stop function may not be performed properly when the thickness of the etch stop layer 158 is 300 ms. Therefore, the thickness of the 158 may be set to 500 ms. Can be.

Thereafter, as shown in FIG. 4B, the light transmitting layer 190 is formed in the hole 180. According to the present invention, the refractive index n of the light transmitting layer 190 may be the same as the microlens (not shown) and the refractive index. The micro lens serves to focus light incident on the image sensor to the photodiode, and thus a detailed description thereof will be omitted. For example, the refractive index of the light transmitting layer 190 may be 1.0 to 1.2.

In the case of chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods, if the depth of the hole 180 is about 3 μm, this step is overcome and the hole 180 is overcome. It may be difficult to evenly form the light transmitting layer 190. Accordingly, according to the present invention, the light-transmitting layer 190 may be formed in the hole 180 by a silicon-on-glass process (SOG). In the SOG process, the light transmitting layer may be evenly formed only in the hole 180 which is about 3 μm due to the characteristics of the fluid.

Hereinafter, a vertical image sensor according to an embodiment of the present invention will be described with reference to FIG. 4B.

The image sensor is divided into a transistor region 200 in which a transistor is formed and a photodiode region 210, which is a region in which a photodiode is formed, that is, a region in which light is received. In this case, a plurality of photodiodes 152 are vertically stacked on the photodiode region 210.

The gate pattern 154 and the spacer 156 are formed in the transistor region 200 for signal processing. In the gate pattern 154, a gate insulating layer is formed on the layer 150, and a polysilicon gate is formed on the gate insulating layer.

An etch stop layer 158 is formed over the top surface of the transistor region 200, including the photodiode region 210 including the top of the top photodiode. However, the etch stop layer 158 may be selectively formed only in the photodiode region 210.

The interlayer insulating layers 160, 162, 164, and 166 are vertically stacked only on the upper portion of the gate pattern 152, that is, on the upper portion of the transistor region 200, in the transistor region 200. Metal wires 170, 172, and 174 and a contact plug (not shown) may be formed on and in the corresponding interlayer insulating film.

The image sensor shown in FIG. 4B according to the present invention, unlike the general image sensor shown in FIG. 3, has an interlayer insulating layer 160, 162, 164 and 166 on top of the etch stop layer 158 in the photodiode region 210. Instead, the light transmitting layer 190 is formed.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a plan view illustrating a general vertical CMOS image sensor.

FIG. 2 is a structural cross-sectional view taken along line II ′ of FIG. 1.

3 is a cross-sectional view of a unit pixel of another general vertical CMOS image sensor.

4A and 4B are cross-sectional views of a vertical image sensor according to an exemplary embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

150: semiconductor substrate and epi layer 152: photodiode

154: gate pattern 156: spacer

158: etch stop layer 160, 162, 164, 166: interlayer insulating film

190: light transmitting layer

Claims (6)

Vertically stacking a plurality of photodiodes in the photodiode region on the semiconductor substrate; Forming an etch stop layer on the top photodiode; Forming a plurality of interlayer insulating films on the etch stop layer; And Etching the interlayer insulating layers of the photodiode region to the etch stop layer by using a photo and etching process to form a hole; And And forming a light transmitting layer in the hole. The method of manufacturing an image sensor having a microlens, wherein the refractive index of the light transmitting layer is the same as that of the microlens and the manufacturing method of the vertical image sensor. The method of claim 1, wherein the light transmitting layer has a refractive index of about 1.0 to about 1.2. The method of claim 1, wherein the light transmitting layer is formed in the hole by a silicon-on-glass (SOC) process. The method of claim 1, wherein the etch stop layer has a thickness of 500 μs. A plurality of photo diodes stacked vertically on the photo diode region on the semiconductor substrate; A gate pattern formed in the transistor region; An etch stop layer formed on the top photodiode; A plurality of interlayer insulating layers formed in the transistor region by being stacked vertically on the gate pattern; And And forming a light transmitting layer formed on the etch stop layer in the photodiode region.

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