KR20090073463A - Mathod for manufacturing of image sensor - Google Patents

Abstract

A method of manufacturing an image sensor is provided to improve a fill factor photosensitivity by providing the vertical type integration of a photo diode and a transistor circuitry. A CMOS circuitry(20) is formed on a semiconductor substrate(10). The interlayer insulating film(30) including a metal wiring(40) is formed on the semiconductor substrate. The plasma treatment on the surface of the interlayer insulating film is progressed. A bottom electrode(55) connected to the metal wiring is formed. A photo diode is formed on the interlayer insulating film including the bottom electrode. At least one among O2, and He and NH3 is used in the plasma treatment process.

Description

Method for Manufacturing of Image Sensor

In an embodiment, a method of manufacturing an image sensor is disclosed.

The image sensor is a semiconductor device that converts an optical image into an electrical signal, and includes a charge coupled device (CCD) image sensor and a complementary metal oxide silicon (CMOS) image sensor (CIS). do.

The CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor is a structure in which a photo diode area for receiving a light signal and converting it into an electric signal and a transistor area for processing the electric signal are horizontally disposed. That is, according to the horizontal CMOS image sensor, the photodiode and the transistor are formed adjacent to each other horizontally on the substrate.

Accordingly, an additional area for photodiode formation is required. Thus, the horizontal image sensor reduces the fill factor area of the photodiode and limits the possibility of resolution.

The embodiment provides a method of manufacturing an image sensor that can provide vertical integration of transistor circuits and photodiodes.

In addition, the embodiment is to provide a method of manufacturing an image sensor that can improve the adhesion characteristics of the photodiode while employing a vertical photodiode.

In another embodiment, a method of manufacturing an image sensor includes: forming a CMOS circuit on a semiconductor substrate; Forming an interlayer insulating film including metal wiring on the semiconductor substrate; Performing a plasma process on the surface of the interlayer insulating film; Forming a lower electrode connected to the metal wiring; And forming a photodiode on the interlayer insulating layer including the lower electrode.

According to the method of manufacturing the image sensor according to the embodiment, it is possible to provide a vertical integration of a transistor circuit and a photodiode.

In addition, according to the embodiment, the fill factor may be approached to 100% by vertical integration of the transistor circuit and the photodiode.

Further, according to the embodiment, it is possible to provide higher sensitivity at the same pixel size by vertical integration than in the prior art.

In addition, according to the embodiment it is possible to reduce the maintenance for the same resolution (Resolution) than the prior art.

In addition, according to the exemplary embodiment, each unit pixel may implement a more complicated circuit without reducing the sensitivity.

In addition, the additional on-chip circuitry that can be integrated by the embodiment can increase the performance of the image sensor and further reduce the size and manufacturing cost of the device.

In addition, according to the embodiment, the adhesion failure of the photodiode can be solved while employing a vertical photodiode.

A method of manufacturing an image sensor according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

A method of manufacturing an image sensor according to an embodiment will be described with reference to FIGS. 1 to 5.

Referring to FIG. 1, an interlayer insulating film 30 including a metal wiring 40 on a CMOS circuit 20 is formed on a semiconductor substrate 10.

On the semiconductor substrate 10, a CMOS circuit 20, which is connected to a photodiode to be described later and converts an electric signal from photoelectric charges received, may be formed for each pixel. For example, the CMOS circuit 20 may be one of 3Tr, 4Tr, and 5Tr.

An interlayer insulating film 30 including a metal wiring 40 is formed on the semiconductor substrate 10 including the CMOS circuit 20 to be connected to a power line or a signal line.

The interlayer insulating film 30 may be formed of a plurality of layers. For example, the interlayer insulating film 30 may be formed of a nitride film or an oxide film.

The metal wire 40 serves to transfer electrons generated from the photodiode to the CMOS circuit 20 below. The metal wire 40 may be connected to an impurity region under the semiconductor substrate 10.

The metal wire 40 may be formed in plural through the interlayer insulating film 30. The metal wire 40 may be formed of various conductive materials including metal, alloy, or salicide. For example, the metal wire 40 may be formed of aluminum, copper, cobalt or tungsten.

Referring to FIG. 2, a plasma treatment process is performed on the surface of the interlayer insulating layer 30. The plasma treatment is to improve the adhesion between the photodiode and the interlayer insulating layer 30.

The plasma treatment may be performed using any one of O ₂ , He, and NH ₃ .

When the plasma treatment process is performed on the interlayer insulating layer 30, the adhesive property of the film in contact with the interlayer insulating layer 30 may be improved.

Referring to FIG. 3, a lower electrode layer 50 is formed on the interlayer insulating layer 30. The lower electrode layer 50 may be formed on the interlayer insulating film 30 to be electrically connected to the metal wiring 40. For example, the lower electrode layer 50 may be formed of metals such as Cr, Ti, TiW, and Ta by PVD.

Referring to FIG. 4, lower electrodes 55 are formed for each pixel on the interlayer insulating layer 30.

In order to form the lower electrode 55, a photoresist pattern (not shown) is formed on the lower electrode layer 50. The lower electrode layer 50 is etched using the photoresist pattern as an etching mask.

Then, lower electrodes 55 electrically connected to the metal wires 40 are formed on the interlayer insulating layer 30 for each pixel.

Referring to FIG. 5, a photodiode is formed on the interlayer insulating film 30 including the lower electrode 55. In particular, since the photodiode is formed on the plasma treatment-treated interlayer insulating film 30, stress such as peeling between the photodiode and the interlayer insulating film 30 may be prevented from occurring. Therefore, the adhesive property between the interlayer insulating layer 30 and the photodiode may be improved.

The photodiode uses a NIP diode. The NIP diode is formed of a structure in which a metal, an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, and a p-type amorphous silicon layer are bonded to each other.

The NIP diode is a photodiode in which an intrinsic amorphous silicon layer, which is a pure semiconductor, is bonded between a p-type silicon layer and a metal, and the intrinsic amorphous silicon layer formed between the p-type metal and the metal becomes a depletion region to generate charge. And storage.

In an embodiment, a NIP diode is used as the photodiode, and the diode may have a structure such as P-I-N, N-I-P, or I-P. In this embodiment, a photodiode having a NIP structure is used as an example. The n-type amorphous silicon layer is the first conductivity type conductive layer 60, the intrinsic amorphous silicon layer is the intrinsic layer 70, and the p-type amorphous silicon layer is The second conductive type conductive layer 80 will be referred to as.

A method of forming the photodiode will be described below.

A first conductivity type conductive layer 60 is formed on the interlayer insulating film 30. In some cases, the first conductivity type conductive layer 60 may not be formed and subsequent processes may be performed.

The first conductivity type layer 60 may serve as the N layer of the N-I-P diode employed in the embodiment. That is, the first conductivity type conductive layer 60 may be an N type conductivity type conductive layer, but is not limited thereto.

The first conductivity type layer 60 may be formed by chemical vapor deposition (CVD), in particular PECVD. For example, the first conductivity type layer 60 is a mixture of PH ₃ , P ₂ H ₅ , and the like in silane gas (SiH ₄ ), deposited at about 100 to 400 ° C. by PECVD, to N-doped amorphous silicon. Can be formed. The first conductivity type conductive layer 60 may be formed to a thickness of 50 ~ 2000Å.

Since the first conductivity type conductive layer 60 is formed on the plasma insulating interlayer 30, mutual adhesion may be improved.

An intrinsic layer 70 is formed on the first conductivity type conductive layer 60. The intrinsic layer 70 may serve as the I layer of the N-I-P diode employed in the embodiment. The intrinsic layer 70 may be formed using intrinsic amorphous silicon.

The intrinsic layer 70 may be formed by chemical vapor deposition (CVD), in particular, PECVD. For example, the intrinsic layer 70 may be formed of amorphous silicon by PECVD using silane gas (SiH ₄ ). The intrinsic layer 70 may be formed to a thickness of 500 ~ 2000Å.

Here, the intrinsic layer 70 may be formed to a thickness of about 10 to 1,000 times thicker than the thickness of the first conductivity type conductive layer 60. This is because the thicker the intrinsic layer 70 is, the more the depletion region of the pin diode increases, which is advantageous for storing and generating a large amount of photocharges.

The second conductivity type conductive layer 80 is formed on the intrinsic layer 70. The second conductivity type conductive layer 80 may be formed in a continuous process with the formation of the intrinsic layer 70. The second conductivity type conductive layer 80 may serve as a P layer of the N-I-P diode employed in the embodiment. That is, the second conductivity type conductive layer 80 may be a P type conductivity type conductive layer, but is not limited thereto.

The second conductivity type conductive layer 80 may be formed by chemical vapor deposition (CVD), in particular, PECVD. For example, the second conductivity type conductive layer 80 is mixed with silane gas (SiH ₄ ), such as BH ₃ or B ₂ H ₆ , by vapor deposition at about 100 to 400 ° C. by PECVD, and is P-doped amorphous. It may be formed of silicon.

The CMOS circuit 20 and the photodiode may be integrated on the semiconductor substrate 10 to close the fill factor of the photodiode to 100%.

An upper electrode 90 is formed on the semiconductor substrate 10 on which the photodiode is formed. The upper electrode 90 may be formed of a transparent electrode having good light transmittance and high conductivity. For example, the upper electrode 90 may be formed of any one of indium tin oxide (ITO), cardium tin oxide (CTO), and ZnO ₂ by a PVD method. The upper electrode may be formed to 100 ~ 1000Å.

Although not shown, a color filter and a micro lens may be additionally formed on the upper electrode 90.

The embodiments described above are not limited to the above-described embodiments and drawings, and it is common to those skilled in the art that various embodiments may be substituted, modified, and changed without departing from the technical spirit of the present embodiment. It will be apparent to those who have knowledge.

1 to 5 are views illustrating a manufacturing process of an image sensor according to an embodiment.

Claims (4)

Forming a CMOS circuit on the semiconductor substrate; Forming an interlayer insulating film including metal wiring on the semiconductor substrate; Performing a plasma treatment on the surface of the interlayer insulating film; Forming a lower electrode connected to the metal wiring; And forming a photodiode on the interlayer insulating film including the lower electrode. The method of claim 1, At least one of O ₂ , He and NH ₃ is injected during the plasma treatment process. The method of claim 1, The lower electrode is formed of any one of Cr, Ti, TiW and Ta. The method of claim 1, The photodiode includes an n-type amorphous silicon, intrinsic silicon, and a p-type amorphous silicon.

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