KR20090072673A - Method for forming a pattern of semiconductor device - Google Patents

Abstract

A method for forming a pattern of a semiconductor device is provided to regularly maintain thickness of a resist residue layer between parts in which a pattern is formed by applying a step height of an overlay vernier or an alignment key as an imprint stop film of an imprint stamp. A resist layer is coated on a top part of a wafer(300) including an alignment mark(310). A pattern of an imprint stamp is imprinted on the resist layer. If imprint stamp is contacted in the alignment mark, the imprint is stopped. The resist layer imprinted by the imprint stamp is hardened. The imprint stamp is separated. A pattern(320a) is formed by removing a resist residue layer formed between parts in which a pattern of the imprinted resist layer is formed.

Description

METHODS FOR FORMING A PATTERN OF SEMICONDUCTOR DEVICE

The present invention relates to a method of forming a pattern of a semiconductor device. In particular, the present invention relates to a pattern formation method using nano imprint lithography.

Lithography technology is the technology of printing and forming complex patterns that define integrated circuits on a wafer. Advances in lithography technology have enabled the high integration of today's integrated circuits.

Background Art [0002] Optical lithography, which is widely used in the past, uses high precision optics to image a pattern on a reduced mask on a semiconductor wafer to which a resist layer is applied.

Such optical lithography uses a KrF (Krypton Fluoride) excimer laser that currently produces 248 nm Deep Ultraviolet (DUV) via g-line (435 nm) and i-line (365 nm) as a light source.

However, conventional optical lithography is limited to ultrafine pattern formation of 70 nm or less.

To overcome this limitation of optical lithography, so-called Next-Generation Lithographies (NGLs) have been developed.

These technologies include EUV lithography (EUVL), X-ray lithography, Ion-beam Projection lithography, Electron-Beam lithography, dip pen lithography, atomic force microscopy (AFM), and Proximal Probe lithography using Scanning Tunneling Microscope (STM). It is proposed.

As described above, the lithographic method has a problem in that the maximum patterning area is small, the patterning speed and throughput are too low, and the cost is excessively consumed.

In addition, the application in the actual nanopattern process is extremely impractical because it requires a multi-step pretreatment process, requires a complicated device, or the pattern is too small to be used as a mask.

The nanoimprint lithography method proposed to overcome the problems of such lithography methods has been spotlighted as a technology for economic mass production of nanostructures and nano devices.

Here, the nanoimprint lithography method refers to a substrate resist coated with a UV-curable or thermoplastic polymer such as PMMA (Polymethylmethacrylate) with a stamp having a nano-sized structure (100 nm or less) and a polymer resist on the substrate. ) The method of moving the stamp pattern on the surface.

At this time, the nanostructures stamped on the resist is formed in the same shape as the stamp, the stamp is mainly made of silicon, silicon oxide, etc. having a nano-size pattern.

1A to 1E are cross-sectional views illustrating a method of forming a pattern of a semiconductor device using imprint lithography according to the prior art.

1A and 1B, a resist layer 110 is formed on the wafer 100.

Here, the resist layer 110 uses a resist such as an ultraviolet curable or thermosetting polymer resin.

Next, the surface of the resist layer 110 is pressed by the imprint stamp 120 having the uneven portion defining the line / space pattern so that the pattern of the imprint stamp 120 is imprinted.

In this case, the imprint process may be applied by directly applying pressure, or there may be a method using an adsorption force acting between the imprint stamp and the resist layer.

Referring to FIG. 1C, ultraviolet rays are projected onto the resist layer 110 imprinted by the imprint stamp 120 so that the resist layer 110 is hardened.

In this case, in addition to the method of transmitting ultraviolet rays, the resist layer 110 may be hardened by applying heat above the glass transition temperature of the resist layer 110 to the lower portion of the wafer 100.

Here, when the resist layer 110 uses an ultraviolet curable polymer resin, it is preferable to expose the ultraviolet ray, and when the resist layer 110 is a thermosetting polymer resin, heat is applied to cure the resist.

1D and 1E, the imprint stamp 120 is separated from the resist layer 110. At this time, since the pressure is not applied to the surface of the wafer 100 and only the pressure is applied within the resist layer 110, a resist resist layer having a predetermined thickness is left between the resist layers of the portion where the pattern is formed.

Next, the entire surface is etched to remove the resist residue layer between the patterns to form the pattern 110a.

2A and 2B are cross-sectional views illustrating a problem of a method for forming a pattern of a semiconductor device using an imprint lithography method according to the prior art.

Referring to FIG. 2A, after forming a resist layer on the wafer 200, the surface of the resist layer 210 is pressed with an imprint stamp 220 having an uneven portion defining a pattern.

At this time, when the wafer 200 or the imprint stamp 220 is slightly inclined, the thickness of the resist resist layer remaining between the portions on which the pattern is formed may become uneven.

Also, referring to FIG. 2B, when the thickness of the resist resist layer between the portions where the pattern is formed is relatively thick compared to the thickness of the portions where the pattern is formed, the pattern does not act as a mask during the subsequent etching process. In this case, the CD uniformity (Critical Dimension Uniformity) of the pattern is deteriorated or the problem of not-opening between the patterns occurs.

In the method of forming a pattern of a semiconductor device according to the related art described above, a subsequent etching process is performed when the thickness of the resist resist layer remaining between the patterns during imprinting is not uniform or is formed relatively thicker than the thickness of the pattern. There is a problem that the CD uniformity of the time pattern is lowered, or a sickle open phenomenon occurs and the characteristics of the device are lowered.

The present invention uses the overlay vernier or the alignment key step as the imprint stop film of the stamp for imprint, thereby making the thickness of the resist resist layer remaining between the patterned portions of the resist layer constant and the CD uniformity of the pattern during the subsequent etching process and It is an object of the present invention to provide a method for forming a pattern of a semiconductor device in which the etching rate is controlled to improve the characteristics of the device.

The method of forming a pattern of a semiconductor device according to the present invention

Applying a resist layer over the wafer including alignment marks,

Imprinting a pattern of an imprint stamp on the resist layer, wherein the imprint is stopped when the imprint stamp contacts the alignment mark;

Hardening the resist layer imprinted by the imprint stamp;

Separating the imprint stamp;

Removing the resist resist layer formed between the pattern forming portions of the imprinted resist layer to form a pattern;

The alignment mark includes an overlay vernier or an alignment key;

To adjust the thickness of the alignment mark,

The resist layer is an ultraviolet curable or thermosetting polymer resin,

The imprint stamp is formed of silicon, quartz or nickel,

Removing the resist residue layer is characterized in that to proceed to the etch back process.

In the method of forming a pattern of a semiconductor device according to the present invention, by using an overlay vernier or an alignment key as an imprint stop film of an imprint stamp, the thickness of the resist resist layer remaining between the portions where the pattern is formed in the resist layer is constant and subsequently During the etching process, the CD uniformity and the etching rate of the pattern may be constantly controlled to improve device characteristics.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

3A and 3B, a resist layer 320 is formed on the wafer 300 provided with the alignment mark 310.

Here, the wafer 300 includes an alignment mark 310, and the resist layer 320 uses a resist such as an ultraviolet curable or thermosetting polymer resin.

In this case, the alignment mark 310 preferably includes an overlay vernier or an alignment key. The overlay vernier is formed at an edge corner of a field, and at least four overlay verniers are formed per filed.

Next, the surface of the resist layer 320 is pressed by the imprint stamp 330 having the uneven portion defining the line / space pattern so that the pattern of the imprint stamp 330 is imprinted.

In this case, the imprint stamp 330 is preferably formed of silicon, quartz, or nickel.

In addition, the imprint process may be applied by directly applying pressure, or there may be a method using an adsorption force acting between the imprint stamp and the resist layer.

Here, in the imprint process, the thickness of the resist resist layer remaining between the patterned portions of the imprinted resist layer 320 is fixed by using the step of the alignment mark 310 as the stop film of the stamp 330 for imprinting. Let's do it. In this case, when the alignment mark 310 is formed, the thickness of the resist residue layer may be adjusted by adjusting the thickness thereof.

Next, ultraviolet rays are projected onto the resist layer 320 imprinted by the imprint stamp 330 so that the resist layer 320 is hardened.

In this case, in addition to the method of transmitting ultraviolet rays, the resist layer 320 may be hardened by applying heat above the glass transition temperature of the resist layer 320 to the lower portion of the wafer 300.

Here, when the resist layer 320 uses an ultraviolet curable polymer resin, it is preferable to expose with ultraviolet rays, and when the resist layer 320 is a thermosetting polymer resin, heat is applied to cure the resist.

Referring to FIG. 3C, the imprint stamp 330 is separated from the imprinted resist layer 320.

Here, the process of separating the imprint stamp 330 is preferably performed using air pressure or vacuum.

Referring to FIG. 3D, the imprinted resist layer 320 leaves a resist residue layer between the patterned portion and the pattern.

At this time, since the imprint is stopped by the alignment mark 320, the thickness of the resist resist layer remaining is constant.

Next, the entire surface etching process is performed to etch a resist resist layer other than the portion where the pattern is formed to form a pattern 320a.

By using the overlay vernier or alignment key as described above, this is used as an etch stop layer in the imprint process, thereby making the thickness of the resist resist layer constant so that the CD uniformity of the pattern is lowered and not open. Problems such as development and lack of etching targets can be prevented.

1A to 1E are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the prior art.

2A and 2B are cross-sectional views illustrating problems occurring in the method of forming a pattern of a semiconductor device according to the prior art.

3A to 3D are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

300: wafer 310: alignment mark

320: resist layer 330: imprint stamp

320a: pattern

Claims (6)

Applying a resist layer over the wafer including alignment marks; Imprinting a pattern of an imprint stamp on the resist layer, wherein the imprint is stopped when the imprint stamp contacts the alignment mark; Hardening the resist layer imprinted by the imprint stamp; Separating the imprint stamp; And Removing the resist residue layer formed between the pattern forming portions of the imprinted resist layer to form a pattern Pattern forming method of a semiconductor device comprising a. The method of claim 1, The alignment mark is a pattern forming method of a semiconductor device, characterized in that it comprises an overlay vernier or an alignment key. The method of claim 1, And a thickness of the alignment mark can be adjusted. The method of claim 1, The resist layer is a pattern of forming a semiconductor device, characterized in that the ultraviolet curable or thermosetting polymer resin. The method of claim 1, The imprint stamp is a pattern forming method of a semiconductor device, characterized in that formed of silicon (Quilz) or quartz (Quartz) or nickel (Nikel). The method of claim 1, Removing the resist resist layer by an etch back process.

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