KR20090072026A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20090072026A
KR20090072026A KR1020070139995A KR20070139995A KR20090072026A KR 20090072026 A KR20090072026 A KR 20090072026A KR 1020070139995 A KR1020070139995 A KR 1020070139995A KR 20070139995 A KR20070139995 A KR 20070139995A KR 20090072026 A KR20090072026 A KR 20090072026A
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region
gate electrode
semiconductor substrate
semiconductor device
insulating film
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KR1020070139995A
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Korean (ko)
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주창영
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주식회사 동부하이텍
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Priority to KR1020070139995A priority Critical patent/KR20090072026A/en
Publication of KR20090072026A publication Critical patent/KR20090072026A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device is provided to compensate a transistor voltage by forming an interlayer insulation film of a dwindling shape from a center to an edge of a moat region. A moat region(15) and an isolation region are defined on a semiconductor substrate. An isolation film(20) is formed on the isolation region of the semiconductor substrate. A gate insulation film and a gate electrode are formed on the moat region of the semiconductor substrate. A spacer is formed on a side wall of the gate electrode. A source and a drain are isolated each other. The gate electrode is positioned between the source and the drain. An interlayer insulation film(70) is formed on the semiconductor substrate including the gate electrode. The interlayer insulation film is formed into a dwindling shape from an edge to a center of the moat region.

Description

반도체 소자{semiconductor device}Semiconductor device

본 발명은 반도체 소자에 관한 것으로, 특히 험프 누설을 방지할 수 있는 반도체 소자에 관한 것이다. The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of preventing hump leakage.

일반적으로 반도체 소자는 기판 상에 트랜지스터와 같은 능동소나나 커패시터와 같은 수동소자들이 형성되고, 형성된 소자들에 대해 외부에서 신호를 인가해주기 위한 금속배선들이 상부에 배치되는 구조로 이루어진다. In general, a semiconductor device has a structure in which active elements such as transistors or passive elements such as capacitors are formed on a substrate, and metal wirings for applying a signal from the outside to the formed elements are disposed thereon.

이중, 모스 트랜지스터는 게이트 전압에 의해 발생하는 전계를 이용하여 전하 채널을 형성하고 게이트 전압의 변화로 전하의 흐름을 제어할 수 있는 반도체 소자이다. 모스 트랜지스터는 바이폴라 트랜지스터에 비해 적은 에너지 소비와 간단한 공정, 그리고 트랜지스터 단위의 크기가 작다는 장점 때문에 집적 회로의 주종을 이루고 있다.Among them, the MOS transistor is a semiconductor device capable of forming a charge channel using an electric field generated by the gate voltage and controlling the flow of charge by changing the gate voltage. Morse transistors dominate integrated circuits because of their low energy consumption, simple process, and small transistor size compared to bipolar transistors.

그러면, 종래의 반도체 소자를 첨부된 도면을 참조하여 설명한다.Next, a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1은 종래에 따른 반도체 소자를 간략하게 나타낸 평면도이다.1 is a plan view briefly showing a semiconductor device according to the related art.

도 1에 도시된 바와 같이, 종래에 따른 반도체 소자는 모스 트랜지스터의 게이트, 소스, 드레인 및 스페이서 등이 형성되는 액티브 영역을 위한 모트(Moat) 영 역(1)과, 모스 트랜지스터의 게이트, 소스, 드레인 및 스페이서 등이 형성된 모트 영역(1)과 소자 분리 영역(3) 상에 형성되는 층간 절연막(2)을 포함하여 구성된다. As shown in FIG. 1, a semiconductor device according to the related art includes a moat region 1 for an active region in which a gate, a source, a drain, and a spacer of a MOS transistor are formed, a gate, a source, And the interlayer insulating film 2 formed on the mote region 1 on which the drain, the spacer, and the like are formed, and the element isolation region 3.

여기서, 소자 분리 영역(3)의 에지 부분에 층간 절연막(2)은 패드(pad) 형태로 확장되어 형성된다. Here, the interlayer insulating film 2 is formed in the edge portion of the device isolation region 3 in a pad form.

이러한 종래의 반도체 소자는 모트 영역 형성 이후 수차례의 열공정을 진행하면서 소자분리막 에지 부분에서 보론(Boron) 격리 현상이 발생한다. 이는 웰 농도가 낮은 트랜지스터의 경우 트랜지스터 전압을 낮추는 효과를 가지고 온다. 이로 인해, 트랜지스터의 센터 부분과 에지 부분간의 트랜지스터 전압 차이가 크게 발생하고 이로 인해 서브스레스홀드(subthreshold) 구간에 하이오프(high-off)가 발생하게 된다. 이와 같은 현상을 개선하기 위해 종래의 반도체 소자는 소자 분리 영역의 에지 부분에 층간 절연 영역(20)을 패드 형태로 확장하여 형성하여 트랜지스터 전압을 보상하지만, 모트 영역의 센터 부분과 에지 부분(B)간의 층간 절연막의 가파른 변화로 인해 트랜지스터 전압의 보상정도가 일치되지 않는 문제점을 가진다.In the conventional semiconductor device, boron isolation occurs at the edge portion of the device isolation layer while undergoing several thermal processes after the formation of the mote region. This has the effect of lowering the transistor voltage for transistors with low well concentrations. As a result, a large transistor voltage difference between the center portion and the edge portion of the transistor is generated, which causes a high-off in the subthreshold section. In order to improve such a phenomenon, the conventional semiconductor device compensates the transistor voltage by forming an interlayer insulating region 20 in the form of a pad in the edge portion of the device isolation region to compensate for the transistor voltage. Due to the steep change of the interlayer insulating film therebetween, the compensation degree of the transistor voltage is not matched.

따라서, 상기와 같은 문제점을 해결하기 위하여, 본 발명은 험프 누설을 방지할 수 있는 반도체 소자를 제공하는데 그 목적이 있다.  Accordingly, in order to solve the above problems, an object of the present invention is to provide a semiconductor device capable of preventing hump leakage.

본 발명에 따른 반도체 소자는 모트 영역과 소자분리영역이 정의된 반도체 기판과, 상기 반도체 기판의 소자분리영역에 형성된 소자분리막과, 상기 반도체 기판의 모트 영역 상에 형성된 게이트 절연막 및 게이트 전극과, 상기 게이트 전극의 측벽에 형성된 스페이서와, 상기 게이트 전극을 사이에 두고 이격하며 형성된 소스/드레인과, 상기 게이트 전극을 포함한 상기 반도체 기판 상에 형성된 층간절연막을 포함하며, 상기 층간절연막은 상기 모트 영역의 에지 부분에서 센터 부분으로 갈수록 좁아지는 형태로 형성되는 것을 특징으로 한다.The semiconductor device according to the present invention includes a semiconductor substrate in which a mott region and an isolation region are defined, an isolation layer formed in an isolation region of the semiconductor substrate, a gate insulating film and a gate electrode formed on the mott region of the semiconductor substrate, A spacer formed on the sidewall of the gate electrode, a source / drain formed while being spaced apart from the gate electrode, and an interlayer insulating film formed on the semiconductor substrate including the gate electrode, wherein the interlayer insulating film is an edge of the mote region. Characterized in that it is formed in a narrower shape from the portion to the center portion.

이상에서 설명한 바와 같이, 본 발명에 의한 반도체 소자는 모트 영역 센터 부분에서 에지 쪽으로 줄어드는 형태로 층간절연막을 형성함으로써 트랜지스터 전압을 자연스럽게 보상하여 험프 누설을 방지할 수 있다.As described above, in the semiconductor device according to the present invention, the interlayer insulating film is formed in the form of a shrinking portion at the center of the mote region, thereby naturally compensating the transistor voltage to prevent hump leakage.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자를 상세히 설명한다.Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 반도체 소자를 나타낸 평면도이고, 도 3은 도 2의 A- A`부분을 나타낸 단면도이다. 2 is a plan view showing a semiconductor device according to the present invention, Figure 3 is a cross-sectional view showing a portion AA 'of FIG.

도 2 및 도 3에 도시된 바와 같이, 본 발명에 따른 반도체 소자는 웰(미도시)이 형성된 반도체 기판(10)과, 반도체 기판(10)의 모트 영역(15)을 정의하기 위해 반도체 기판(10)의 필드 영역에 형성된 소자분리막(20)과, 반도체 기판(10)의 모트 영역(15) 상에 형성된 게이트 절연막(30) 및 게이트 전극(40)과, 게이트 전극(40)의 측벽에 형성된 스페이서(50)와, 게이트 전극(40)을 사이에 두고 이격하며 형성된 소스/드레인(60)과, 게이트 전극(40)을 포함한 반도체 기판(10) 전면에 형성된 층간 절연막(70)을 포함하여 이루어진다. As shown in FIG. 2 and FIG. 3, the semiconductor device according to the present invention includes a semiconductor substrate 10 in which a well (not shown) is formed, and a mote region 15 of the semiconductor substrate 10. A device isolation film 20 formed in the field region of 10, the gate insulating film 30 and the gate electrode 40 formed on the mote region 15 of the semiconductor substrate 10, and the sidewalls of the gate electrode 40. And a spacer 50, a source / drain 60 formed to be spaced apart from each other with the gate electrode 40 interposed therebetween, and an interlayer insulating layer 70 formed on the entire surface of the semiconductor substrate 10 including the gate electrode 40. .

여기서, 층간 절연막(70)은 모트 영역(15)의 에지 부분(B)에서 센터 부분으로 갈수록 좁아지도록 좌우에서 사다리꼴 형태를 깎아낸 형태로 형성된다. 이러한 모트 영역(15)의 에지 부분(B)에서 센터 부분으로 자연스럽게 증가된 층간 절연막(70)의 형태로 인하여 에지 부분(B)의 트랜지스터 전압은 소자 분리막(20)의 코너 쪽으로 갈수록 커지는 트랜지스터 전압 감소분에 대해 자연스럽게 보상해줄 수 있다. Here, the interlayer insulating film 70 is formed in a shape in which the trapezoidal shape is cut off from the left and right so as to become narrower from the edge portion B of the mote region 15 toward the center portion. Due to the shape of the interlayer insulating film 70 naturally increased from the edge portion B of the mote region 15 to the center portion, the transistor voltage of the edge portion B increases toward the corner of the device isolation layer 20. You can naturally compensate for.

상기와 같이 구성된 반도체 소자의 제조 과정을 첨부된 도 4a 내지 4b를 참조하여 상세히 설명하면 다음과 같다.The manufacturing process of the semiconductor device configured as described above will be described in detail with reference to FIGS. 4A to 4B.

먼저, 도 4a에 도시된 바와 같이, 반도체 기판(10)의 모트 영역(15)을 정의하기 위해 필드 영역에 소자분리막(20)을 형성하고, 이어, 웰-이온주입을 통해 반도체 기판(10) 내에 웰(미도시)을 형성한다. 그런 다음, 기판(10) 상에 게이트 산화막과 게이트 도전막을 차례로 형성하고, 게이트 산화막과 게이트 도전막을 패터 닝하여 게이트 전극(40)을 형성한다. 여기서, 게이트 도전막으로서는 넌-도프트(Non-doped) 폴리실리콘을 이용한다. 이어서, 게이트 전극(40) 양측의 기판 표면에 LDD(Lightly doped Drain) 영역(미도시)을 형성한다. 그런 다음, 게이트 전극(40)의 양측벽에 스페이서(50)를 형성하고, 이어, 스페이서(50)를 포함한 게이트 전극(40) 양측의 기판 표면에 소오스/드레인 영역(60)을 형성한다.First, as shown in FIG. 4A, the device isolation layer 20 is formed in the field region to define the mote region 15 of the semiconductor substrate 10, and then the semiconductor substrate 10 is formed through well-ion implantation. A well (not shown) is formed in the inside. Then, the gate oxide film and the gate conductive film are sequentially formed on the substrate 10, and the gate oxide film and the gate conductive film are patterned to form the gate electrode 40. Here, non-doped polysilicon is used as the gate conductive film. Subsequently, a lightly doped drain (LDD) region (not shown) is formed on the substrate surfaces on both sides of the gate electrode 40. Then, spacers 50 are formed on both side walls of the gate electrode 40, and then source / drain regions 60 are formed on the substrate surface on both sides of the gate electrode 40 including the spacers 50.

이어서, 도 4b에 도시된 바와 같이, 기판 결과물 상에 층간절연막(70)을 형성하고, 그 표면을 평탄화시킨다. Subsequently, as shown in FIG. 4B, an interlayer insulating film 70 is formed on the substrate resultant, and the surface thereof is planarized.

이때, 층간절연막(70)은 모트 영역(15)의 에지 부분(B)에서 센터 부분으로 갈수록 좁아지도록 좌우에서 사다리꼴 형태를 깎아낸 형태로 형성된다.At this time, the interlayer insulating film 70 is formed in a shape in which the trapezoidal shape is cut off from the left and right so as to narrow from the edge portion B of the mote region 15 toward the center portion.

그런 다음, 도시되지는 않았지만, 층간절연막(70)의 소정 부분들을 선택적으로 식각하여 게이트 전극(40) 및 소오스/드레인 영역(50)을 각각 노출시키는 콘택홀을 형성한다. Next, although not illustrated, predetermined portions of the interlayer insulating layer 70 are selectively etched to form contact holes that expose the gate electrode 40 and the source / drain regions 50, respectively.

이후, 공지의 후속 공정을 진행하여 반도체 소자를 완성한다.Thereafter, a known subsequent process is performed to complete the semiconductor device.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여 져야만 할 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

도 1은 종래에 따른 반도체 소자를 간략하게 나타낸 평면도.1 is a plan view briefly showing a semiconductor device according to the prior art.

도 2는 본 발명에 따른 반도체 소자를 나타낸 평면도.2 is a plan view showing a semiconductor device according to the present invention.

도 3은 도 2의 A-A`부분을 나타낸 단면도.FIG. 3 is a cross-sectional view illustrating a AA ′ portion of FIG. 2. FIG.

도 4a 내지 4b는 본 발명에 따른 반도체 소자의 제조방법을 나타낸 단면도.4A to 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (2)

모트 영역과 소자분리영역이 정의된 반도체 기판과, A semiconductor substrate having a moat region and an element isolation region defined therein; 상기 반도체 기판의 소자분리영역에 형성된 소자분리막과,An isolation layer formed in the isolation region of the semiconductor substrate; 상기 반도체 기판의 모트 영역 상에 형성된 게이트 절연막 및 게이트 전극과,A gate insulating film and a gate electrode formed on the mote region of the semiconductor substrate; 상기 게이트 전극의 측벽에 형성된 스페이서와,Spacers formed on sidewalls of the gate electrode; 상기 게이트 전극을 사이에 두고 이격하며 형성된 소스/드레인과,Source / drain formed apart from the gate electrode; 상기 게이트 전극을 포함한 상기 반도체 기판 상에 형성된 층간절연막을 포함하며, An interlayer insulating film formed on the semiconductor substrate including the gate electrode; 상기 층간절연막은 상기 모트 영역의 에지 부분에서 센터 부분으로 갈수록 좁아지는 형태로 형성되는 것을 특징으로 하는 반도체 소자.And the interlayer insulating film is formed to be narrower from the edge portion of the mote region toward the center portion. 제 1항에 있어서, The method of claim 1, 상기 층간절연막은 The interlayer insulating film 상기 모트 영역의 에지 부분에서 센터 부분으로 갈수록 좁아지는 형태로 좌우에서 사다리꼴 형태를 깎아낸 형태로 형성되는 것을 특징으로 하는 반도체 소자.And a trapezoidal shape cut from the left and right in a form that becomes narrower from the edge portion of the mote region toward the center portion.
KR1020070139995A 2007-12-28 2007-12-28 Semiconductor device KR20090072026A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109390408A (en) * 2017-08-11 2019-02-26 三星电子株式会社 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109390408A (en) * 2017-08-11 2019-02-26 三星电子株式会社 Semiconductor device
CN109390408B (en) * 2017-08-11 2023-12-29 三星电子株式会社 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

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