KR20090069859A - Nonvolatile memory device and method for manufacturing the same - Google Patents

Abstract

A nonvolatile memory device and a method for manufacturing the same are provided to reduce sheet resistance of a drain contact plug by connecting a string with a bit line through a contact plug of the drain. A plurality of bit lines(BL) meets at right angle to a plurality of word lines(WL0-WL31) in perpendicular direction. A plurality of cell strings(ST0,ST1) are composed of a plurality of cells while being connected between a firsts and a second transistor and a dummy transistor(DT) is serially connected with first transistors of adjacent cell strings. A first and a second drain contact plug connect a drain region of a first selection transistor with a bit line independently.

Description

Nonvolatile memory device and manufacturing method thereof {NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a nonvolatile memory device, and more particularly, to a NAND type flash memory device in which a plurality of memory cells are connected in series to form a string. It relates to a manufacturing method.

The NAND flash memory device, which is a nonvolatile memory device, includes a drain select transistor (hereinafter referred to as a first select transistor), a source select transistor (hereinafter referred to as a second select transistor), and a series between the first and second select transistors. It includes a plurality of strings consisting of a plurality of memory cells connected. Further, neighboring strings of the strings are connected to the drain contact plug by pairing two strings in which the first select transistor shares the drain region with each other, and the first select transistor shares the drain region with each other.

1 is an equivalent circuit diagram illustrating a memory cell array of a NAND flash memory device according to the prior art, and FIG. 2 is a cross-sectional view illustrating a string ST0 of the memory cell array shown in FIG. 1. Here, as an example, a string structure consisting of 32 memory cells is illustrated.

1 and 2, strings ST0 and ST1 of a NAND flash memory device according to the related art are arranged symmetrically with neighbors. That is, the first selection transistors DST share the drain region with each other. Each of the strings ST0 and ST1 includes a plurality of memory cells M0 to M31 connected in series between the first and second selection transistors DST and SST, and the first and second selection transistors DST and SST. ) In addition, the drain region 107 of the first select transistor DST is connected to the bit line BL through the drain contact plug DCT, and the source region of the second select transistor SST is commonly connected to the common source line. do. In addition, the gate of the first select transistor DST in each string is connected to the drain select line DSL, and the gate of the second select transistor SST is connected to the source select line SSL. In addition, gates of the memory cells M0 to M31 are connected to word lines WL0 to WL31, respectively.

Meanwhile, in FIG. 2, '100' is a semiconductor substrate, '101' is a tunnel insulating film (or gate insulating film), '102' is a floating gate, '103' is a dielectric film, '104' is a control gate, and '105' Is a cell gate, '106' is a transistor gate, '107' is a junction region (source and drain region), '108' is a spacer, '109' is an etch stop layer, and '110' and '111' are interlayer insulating films. Indicates.

However, the memory cell array of the NAND flash memory device according to the related art is connected to the drain region 107 of the first select transistor DST formed in two strings ST0 and ST1 adjacent to one drain contact plug DCT. Since the structure is connected in common, the sheet resistance between the bit line BL and the drain region of the first selection transistor DST is increased to limit the movement of electrons, thereby causing a problem in that the operation speed of the device is lowered.

Accordingly, the present invention is proposed to solve the problems of the prior art, and a nonvolatile memory device and a method of manufacturing the same, which can improve the operation speed of the device by reducing the resistance between the bit line and the drain region of the first selection transistor. The purpose is to provide.

According to an aspect of the present invention, a plurality of word lines, a plurality of bit lines orthogonal to a direction perpendicular to the word lines, first and second selection transistors, A plurality of cell strings consisting of a plurality of cells selected in series by second word transistors selected by the word line, a dummy transistor connected in series between first select transistors of neighboring cell strings, and the dummy transistors, respectively. A nonvolatile memory device including first and second drain contact plugs that independently connect drain regions of connected neighboring first select transistors to the bit lines, respectively, is provided.

In addition, according to another aspect of the present invention, a plurality of strings including a first and a second select transistor and a plurality of memory cells connected in series between the first and second select transistors, In a method of manufacturing a nonvolatile memory device in which neighboring ones of the strings are symmetrically arranged, a gate electrode of a first and a second selection transistor and a gate electrode of the memory cell are respectively formed on a substrate and adjacent to each other. Forming a gate electrode of the dummy transistor between the gate electrode of the first selection transistor, forming a junction region in the substrate exposed to both sides of the gate electrode, and forming spacers on both side walls of the gate electrode And forming an interlayer insulating film to cover the structure including the spacer. And forming a contact hole through which the junction region of the dummy transistor is exposed by etching the interlayer insulating layer, and forming first and second drain contact plugs to fill the contact holes, respectively. A method of manufacturing a memory device is provided.

According to the present invention including the above-described configuration, one drain contact plug is independently assigned to each string, and the string resistance of the drain contact plug is reduced by 1 by connecting each string to the bit line through the drain contact plug. / 2, which increases the movement of electrons, improving the device's operating speed.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and when referred to as being on or above another layer or substrate, it is different. It may be formed directly on the layer or the substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represents the same layer, and when the reference numerals include English, it means that the same layer is partially modified through an etching or polishing process.

Example

3 is an equivalent circuit diagram illustrating a memory cell array of a nonvolatile memory device according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view illustrating a string ST0 of the memory cell array illustrated in FIG. 3. Here, as an example, a string structure consisting of 32 memory cells is illustrated.

3 and 4, a nonvolatile memory device according to an embodiment of the present invention may include a plurality of word lines WL0 to WL31 and a plurality of bit lines orthogonal to a direction perpendicular to the word lines WL0 to WL31. And a plurality of cell strings ST0, which are connected in series between the BL and the first and second selection transistors DST and SST and are composed of a plurality of cells M0 to M31 selected by the word lines WL0 to WL31. The dummy transistor DT connected in series between the ST1, the first selection transistor DST of the neighboring cell strings ST0 and ST1, and the neighboring first selection transistor DST respectively connected to the dummy transistor DT. And the first and second drain contact plugs DCT1 and DCT2 connecting the drain regions 207 of FIG. 11 to the bit lines BL independently of each other.

In addition, the nonvolatile memory device may further include a dummy line DL connected to the gate electrode 206 of the dummy transistor DT. In this case, the dummy line DL is formed in a direction parallel to the word lines WL0 to WL31. In addition, the gate electrode 206 of the dummy transistor DT is integrally formed with the dummy line DL. Further, the width (width in the word line direction) of the gate electrode 206 of the dummy transistor DT is formed to have a width smaller than the width (width in the word line direction) of the gate electrode of the first selection transistor DST. do.

Hereinafter, a method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention shown in FIGS. 3 and 4 will be described with reference to FIGS. 5A to 5D. 5A through 5D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

First, as illustrated in FIG. 5A, triple n-wells (not shown) and p-wells (not shown) are formed in a semiconductor substrate 200, for example, a p-type substrate, and then ion implantation for adjusting the threshold voltage is performed. Carry out the process.

Subsequently, the semiconductor substrate 200 may be formed by performing a conventional-shallow trench isolation (C-STI), self-aligned STI (SA-STI), advanced self-aligned-sti (ASA-STI), or self-aligned floating gate (SAFG) process. A dummy transistor between the first and second selection transistors DST and SST and the gate electrodes 205 and 206 of the memory cells M0 to M31 at the same time, and between the gate electrodes 206 of the first selection transistor DST. Gate electrodes 205 and 206 of the DT are formed. In this case, the gate electrodes 205 and 206 include a gate insulating film (or tunnel insulating film) 201, a floating gate 202, a dielectric film 203, and a control gate 204.

Each of the gate electrodes 205 and 206 further includes a conductive layer (not shown) and a hard mask (not shown) formed on the control gate 204. In this case, the conductive layer may be formed of a transition metal, an alloy film in which two kinds of transition metals are mixed, a silicide layer made of a transition metal, or a laminated structure in which these are stacked. For example, iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), molybdenum (Mo) or titanium (Ti) is used as the transition metal. In addition, a tungsten silicide layer (Wsix) is used as the metal silicide layer.

In addition, the hard mask may be formed of a nitride film such as silicon nitride film (Si ₃ N ₄ ), and in this case, a buffer film (not shown) may be further formed between the conductive layer and the hard mask to protect the conductive layer. Can be. In this case, the buffer film is formed of an oxide film.

In detail, the gate electrode 205 connected to each of the word lines WL0 to WL31 and functioning as a memory cell, which is substantially integrally formed, includes the gate insulating film 201, the floating gate 202, the dielectric film 203, and the gate electrode 205. The control gate 204 is formed in a stacked structure. In contrast, the gate electrode 206 serving as the first and second selection transistors DST and SST has the same stacked structure as the gate electrode 205, but the dielectric film 203 penetrates the floating gate 202. And the control gate 204 are formed in a structure electrically connected to each other. In this case, the gate insulating film 201 may be formed in an oxide film or a stacked structure of an oxide film and a nitride film. In addition, the dielectric film 203 may be formed of a laminated structure of an oxide film-nitride film-oxide film, or a dielectric film of any one selected from high dielectric film Al ₂ O ₃ , HfO ₂ , and ZrO ₂ -or a mixed film or a laminated film thereof. .

Subsequently, a junction region 207 is formed in the substrate 200 exposed between the gate electrodes 205 and 206 to function as a source and a drain region, respectively. In this case, the junction region 207 may include a lightly doped drain (LDD) region to prevent short channel effects.

Subsequently, an insulating film for spacers is deposited along the upper surface of the structure including the gate electrodes 205 and 206, followed by a dry etching process such as an etch back process to perform the gate electrodes 205 and 206. Spacers 208 are formed on both side walls of the substrate. In this case, the spacer insulating film may be formed of an oxide film, a nitride film, or a laminated film in which these layers are stacked.

Subsequently, as illustrated in FIG. 5B, an etch stop layer 209 that functions as a self aligned contact (SAC) layer is formed along the upper surface of the structure including the spacer 208. In this case, the etch stop layer 209 may be formed of a nitride layer, for example, silicon nitride layer (Si ₃ N ₄ ), but is not limited thereto. The etch stop layer 209 may have sufficient insulating properties to secure an etch selectivity with a subsequent interlayer insulating layer. Any material that can be used can be used. For example, the etch stop layer 209 is formed at a temperature of 600 ° C. to 800 ° C. using DCS (DiChloroSilane (SiH ₂ Cl ₂ )) and NH ₃ gas.

Subsequently, an interlayer insulating film 210 (hereinafter referred to as a first interlayer insulating film) is formed on the etch stop layer 209 so as to fill the gap between the gate electrodes 205 and 206. In this case, the first interlayer insulating layer 210 is formed of an oxide-based material, preferably a silicon oxide film (SiO ₂ ). For example, BPSG (BoroPhosphoSilicate Glass) film, PSG (PhosphoSilicate Glass) film, USG (Un-doped Silicate Glass) film, TEOS (Tetra Ethyle Ortho Silicate) film, SOG (Spin On Glass) film, HDP (High Density Plasma) film , CDO (Carbon Doped Oxide) film formed of any one selected from. Preferably, it is formed of an HDP film having excellent embedding characteristics.

Subsequently, the top surface may be planarized by performing a planarization process on the first interlayer insulating layer 210. At this time, the planarization process is performed by a chemical mechanical polishing (CMP) process.

Next, an interlayer insulating film 211 (hereinafter referred to as a second interlayer insulating film) is formed on the first interlayer insulating film 210. In this case, the second interlayer insulating layer 211 may be formed of any one selected from materials used as the first interlayer insulating layer 210. Preferably, it is formed of a TEOS film.

Meanwhile, in the above, the interlayer insulating film is separated into the first and second interlayer insulating films 210 and 211 and formed in a stacked structure, but may be formed in a single layer structure using the same material.

Subsequently, as illustrated in FIG. 5C, the first and second interlayer insulating layers 210A and 211A and the etch stop layer 209A are etched to expose the junction region 207 of the dummy transistor DT, thereby contacting the hole 212. ). In this case, the contact hole 212 may be formed in a circular or bar shape.

Subsequently, as illustrated in FIG. 5D, the first and second drain contact plugs 213 are formed to fill the contact holes 212 (see FIG. 5C), respectively. In this case, the first and second drain contact plugs 213 may be formed of any one selected from conductive materials. For example, it is formed of any one of tungsten (W), aluminum (Al), copper (Cu) or a polycrystalline silicon film.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, although the embodiment of the present invention has been described as a NAND flash memory device as an example, this is an example, and the memory cell array can be applied to all nonvolatile memory devices having a string structure. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is an equivalent circuit diagram showing a memory cell array of a NAND flash memory device according to the prior art.

FIG. 2 is a cross-sectional view of the string ST0 of the memory cell array shown in FIG.

3 is an equivalent circuit diagram illustrating a memory cell array of a nonvolatile memory device according to an embodiment of the present invention.

4 is a cross-sectional view showing the string ST0 of the memory cell array shown in FIG.

5A through 5D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 200: semiconductor substrate

101, 201: gate insulating film (tunnel insulating film)

102, 202: floating gate

103,203: dielectric film

104, 204: control gate

105, 106, 205, 206: gate electrode

107, 207: junction area

108, 208: spacer

109, 209: etch stop film

110, 111, 210, 211, 210A, 211A: interlayer insulation film

212: contact hole

213: drain contact plug

Claims (10)

A plurality of word lines; A plurality of bit lines orthogonal to a direction perpendicular to the word line; A plurality of cell strings each having a plurality of cells selected by the word line connected in series between first and second select transistors and the first and second select transistors; A dummy transistor connected in series between first select transistors of the neighboring cell strings; And First and second drain contact plugs respectively connecting the drain regions of the neighboring first select transistors connected to the dummy transistors to the bit lines independently of each other; Nonvolatile memory device comprising a. The method of claim 1, And a dummy line connected to the gate electrode of the dummy transistor. The method of claim 2, And the dummy line is integrally formed with the gate electrode of the dummy transistor. The method of claim 2, The dummy line is formed in a direction parallel to the word line. The method of claim 1, And a width (width in a word line direction) of a gate electrode of the dummy transistor is smaller than a width of the gate electrode of the first selection transistor. A non-volatile memory device including a plurality of strings formed of first and second select transistors and a plurality of memory cells connected in series between the first and second select transistors, and neighboring ones of the strings are symmetrically arranged; In the manufacturing method of Forming a gate electrode of the dummy transistor between the first and second select transistors and a gate electrode of the memory cell, respectively, on a substrate, and simultaneously between the gate electrodes of the neighboring first select transistors; Forming a junction region in the substrate exposed to both sides of the gate electrode; Forming spacers on both sidewalls of the gate electrode; Forming an interlayer insulating film to cover the structure including the spacer; Etching the interlayer insulating film to form a contact hole exposing a junction region of the dummy transistor; And Forming first and second drain contact plugs to fill the contact holes, respectively. Method of manufacturing a nonvolatile memory device comprising a. The method of claim 6, After forming the spacer, And forming an etch stop layer along an upper surface of the structure including the spacers. The method of claim 6, The contact hole is a method of manufacturing a nonvolatile memory device to form a circular or bar (bar). The method of claim 6, The gate electrode of the dummy transistor is formed in a direction parallel to the word line. The method of claim 6, And a width (width in the word line direction) of the gate electrode of the dummy transistor is smaller than the width of the gate electrode of the first selection transistor.

Images