KR20090069096A - Method for manufacturing semiconductor device - Google Patents

Abstract

A manufacturing method of semiconductor device is provided to enhance the process margin of the etching process by inserting tab-pattern to the layout which has resistance to leaning phenomenon and having big length in comparison with the minimum line length. The manufacturing method of semiconductor device comprises a design phase(S1) of a first lay out, a comparison step(S2) of a minimum line length, and a correction step(S3) of the first lay out. A design phase of the first layout is performed to design the first layout implementing the intended circuit. A comparison step of the minimal line length is performed to apply DRC to the first layout and compares the length of the first layout and the minimum dimension which does not tumble down of the line. The manufacturing method of semiconductor device comprises an application phase(S4) of the optical proximity correction, a manufacturing process(S5) of mask, and an execution phase(S6) of the wafer process. The application phase of the optical proximity correction is performed to apply the optical proximity correction to the first layout and forms the second layout. The manufacturing process of mask is performed to make the mask corresponding to the second layout.

Description

Method for manufacturing semiconductor device

The present invention relates to a method of forming a semiconductor device, and more particularly, a minimum line that does not cause a collapse of a line pattern as a design rule for a line pattern when performing a DRC (Design Rule Check). Set the length to etch the micro bridge of the metal layer by inserting a tab (or pad) in the middle if the length of the line pattern is longer than the minimum line length in the layout of the currently designed target pattern. The present invention relates to a method of forming a semiconductor device capable of improving product yield by increasing an etch process margin.

In general, a lithography process is a process of performing exposure and development after applying a photoresist on a wafer, and is performed before an etching process or an ion implantation process requiring a mask.

As semiconductor devices become more integrated, the size and pitch of the patterns that make up the circuit are decreasing, so that during processing, the photolithography technology refines the mask design to properly control the amount of light emitted through the mask. The company is overcoming the technical limitations of semiconductor device manufacturing by developing new photosensitizers, developing scanners using high numerical aperture lenses, and developing modified masks. .

On the other hand, the most widely used UV lasers currently use KrF light sources with a wavelength of 248 nm, but the light source is converted to shorter wavelengths of EUV, including ArF with a wavelength of 193 nm and F2 laser with a wavelength of 157 nm. It is becoming.

In addition, as semiconductor devices are highly integrated, high resolution and accurate depth of focus (DOF) are required, and as the introduction of immersion technology in lithography technology, numerical aperture (NA) becomes extremely extreme. As the numerical aperture increases, the depth of focus decreases so that the actual resolution does not increase much. Therefore, research and development for increasing the resolution and the depth of focus have been conducted.

In particular, since the pattern of the semiconductor device is not repetitive and has an irregular geometry, very delicate Optical Proximity Correction (hereinafter referred to as OPC) is required in a short time while overcoming the optical resolution limit. This OPC technology can be used to compensate for the distortion of light in the optical exposure apparatus.

The main pattern formation when the exposure process is performed using a conventional optical device has many technical difficulties. In order to secure the isolation area margin required for the subsequent process through the current exposure process, the target critical dimension of the independent area that is finally formed after etching must be exposed to under exposure. Can be satisfied. Here, under exposure is an exposure method that expands more on a line basis than a design line width by exposing less than a reference exposure for forming a normal pattern. Therefore, there is a problem that the space becomes relatively smaller because the line becomes larger.

In order to improve this, there is a method such as applying a new high resolution exposure apparatus, applying a precision etching apparatus with less etching variation, changing the design, and adjusting the pattern arrangement of the mask.

Here, a method of applying a new high resolution exposure apparatus or a precision etching apparatus having a small etching deviation has a cost of ownership problem, and a method of changing a design has a problem of turn around time and a mask. The method of controlling the pattern placement of the mask (OPC) adds to the cost of manufacturing the mask because each time the pattern of the mask is adjusted, the mask manufacturing cost is added, and the difficulty is required at the same time that requires professional optical development experience, simulation program utilization and mask manufacturing accuracy. There is a problem with the application of the technology.

The general OPC method patterns a target pattern duty layout, measures CD (critical dimensions) of patterns for each pitch, and performs modeling to form an OPC rule using the pattern.

In the process of forming a semiconductor device, a pattern collapse occurs when the minimum line length of a metal layer is increased. In particular, when the thickness of the photoresist film is set low, a margin of the etching process is insufficient and a hard mask or the like must be used.

An object of the present invention is to provide a method of forming a semiconductor device capable of improving product yield by increasing an etch process margin for a micro bridge of a metal layer.

The method of forming a semiconductor device according to the present invention

Designing a first layout of the target pattern implementing the circuit;

Performing a first design rule check (DRC) on the first layout, and comparing a target line length of the layout with a minimum line length at which no collapse of the target pattern occurs;

Correcting the first layout by inserting a tab in the center of the target pattern when the length of the target pattern is longer than the minimum line length;

Performing an optical proximity correction (OPC) on the corrected second layout in the correcting of the first layout;

Manufacturing a mask in which the second layout is defined according to the optical proximity correction result; And

And performing a wafer process using the mask to perform an exposure and etching process.

The tab also includes a pad,

Performing secondary DRC on the second layout;

The etching process may include a damascene process.

The present invention sets a minimum line length that does not cause a collapse of a line pattern as a design rule for a line pattern when performing a DRC (Design Rule Check) to set a line in a layout of a currently designed target pattern. If the length of the pattern is longer than the minimum line length, a tab (or pad) is inserted in the middle to increase the etch process margin for the micro bridge of the metal layer to improve product yield. It can be effected.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

1 is a flowchart illustrating a method of forming a semiconductor device according to the present invention. Here, an etching process for the metal layer is described as an example, but is not limited thereto.

First, a layout of a target pattern for implementing a circuit is designed (S1), and a DRC (Design Rule Check) is performed (S2). At this time, the minimum line length (MLL) is set as a design rule for the line pattern so that the collapse of the line pattern does not occur. If the length is longer than the minimum line length, a tab (or pad) is inserted in the middle to change the layout of the target pattern (S3).

In general, in order to detect a collapsing of a target pattern, a mask is manufactured and then a wafer process is performed using the mask, and a collapsing of a line pattern on an actual wafer is observed. In the present invention, a procedure is performed to correct a defect by using a layout change in a layout design step (S1) in which a tap is inserted into a target pattern in which a collapse of a line pattern is expected by performing a DRC. The collapse of the line pattern can be prevented.

On the other hand, in general, the collapse of the line pattern (collapse) is more likely to occur as the aspect ratio of the photoresist film (large ratio). However, in the case of applying the technique of the present invention, even if the aspect ratio of the photoresist film is 4 or more, pattern collapse can be prevented.

Subsequently, OPC (Optical Proximity Correction) is performed on the result of DRC (S4), and a mask is fabricated according to the OPC result (S5), and the target pattern is formed on the wafer using a photosensitive film through an exposure and development process using the mask. A wafer process is performed to etch a metal layer using the photoresist target pattern as an etch mask to form a metal line pattern on the wafer (S6).

2A and 2B are plan views illustrating a layout correction method according to the present invention. Here, FIG. 2A is a plan view showing a layout in which a target pattern is designed to implement a circuit, and FIG. 2B is a plan view in which the layout is corrected by inserting the tab 22 into the line pattern 20a.

Design rule check (DRC) is performed on a layout in which a target pattern is designed to implement a circuit as shown in FIG. 2A, and the minimum length L of the line pattern 20 is set as a design rule. If the line length is longer than the MLL, a tab (or pad) 22 is inserted into the center portion of the line pattern 20a to change the layout of the target pattern as shown in FIG. 2B. Here, the minimum line length MLL refers to the maximum length of the line pattern 22 in which no collapse occurs.

Thus, the present invention can prevent the collapse of a line pattern having a high aspect ratio. In other words, the aspect ratio of the photosensitive film of the metal layer can be increased. The etching process for Al, W, etc. may be performed even without using a hard mask in the selective etching process for the metal layer, thereby simplifying the etching process.

As a result, the present invention can improve the product yield by increasing the etch process margin for the micro bridge of the metal layer.

In the above embodiment, a normal metal layer etching process has been described as an example, but is not limited thereto. That is, the present invention can also be applied to a damascene process.

In addition, another method of preventing the collapse of the line pattern is to reduce the aspect ratio by reducing the thickness of the photoresist film, and to use a hard mask such as silicon nitride (Si3N4) or amorphous carbon on top of Al and W. Can be used. As another method, a method of forming a curved line pattern may be used.

Meanwhile, in the layout design stage of the present invention, a limited design for manufacturing (DFM) for a minimum line length (MLL) may be used as a design rule in response to a collapse of a line pattern.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a flowchart illustrating a method of forming a semiconductor device according to the present invention.

2A and 2B are plan views illustrating a layout correction method according to the present invention.

<Description of the symbols for the main parts of the drawings>

S1: Design Target Pattern Layout

S2: DRC (L> MLL)

S3: Correct layout by inserting a tab in the center of the line pattern

S4: OPC

S5: Mask Making

S6: wafer process

Claims (4)

Designing a first layout of the target pattern implementing the circuit; Performing a first design rule check (DRC) on the first layout, and comparing a target line length of the layout with a minimum line length at which no collapse of the target pattern occurs; Correcting the first layout by inserting a tab in the center of the target pattern when the length of the target pattern is longer than the minimum line length; Performing an optical proximity correction (OPC) on the corrected second layout in the correcting of the first layout; Manufacturing a mask in which the second layout is defined according to the optical proximity correction result; And And performing a wafer process using the mask to perform an exposure and etching process. The method of claim 1, And the tab comprises a pad. The method of claim 1, And performing a secondary DRC on the second layout. The method of claim 1, The etching process includes a damascene process.

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