KR20090068634A - Method for forming trench of semiconductor device - Google Patents

Method for forming trench of semiconductor device Download PDF

Info

Publication number
KR20090068634A
KR20090068634A KR1020070136329A KR20070136329A KR20090068634A KR 20090068634 A KR20090068634 A KR 20090068634A KR 1020070136329 A KR1020070136329 A KR 1020070136329A KR 20070136329 A KR20070136329 A KR 20070136329A KR 20090068634 A KR20090068634 A KR 20090068634A
Authority
KR
South Korea
Prior art keywords
trench
pad nitride
semiconductor substrate
nitride layer
etching
Prior art date
Application number
KR1020070136329A
Other languages
Korean (ko)
Inventor
손승우
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020070136329A priority Critical patent/KR20090068634A/en
Publication of KR20090068634A publication Critical patent/KR20090068634A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

A method for forming a trench of a semiconductor device is provided to prevent contamination due to a phosphoric acid chemical by performing a moat-wet-dip process before a trench process. A pad oxide layer and a pad nitride layer are laminated on a semiconductor substrate(S101). An anti-reflective layer and a photoresist pattern are formed on the pad nitride layer in order to open a trench region(S102). An etch process is performed to etch the anti-reflective layer, the pad nitride layer, and the pad oxide layer(S103). The semiconductor substrate corresponding to the trench region is exposed by removing the pad nitride layer. The pad nitride layer is etched in a constant depth by performing a moat-wet-dip process(S104). The photoresist pattern and the anti-reflective layer are removed(S105). An exposed part of the semiconductor substrate is etched by using the pad nitride layer as an etch barrier. A trench is formed by etching the exposed part of the semiconductor substrate(S106).

Description

Trench Formation Method of Semiconductor Device {METHOD FOR FORMING TRENCH OF SEMICONDUCTOR DEVICE}

The present invention relates to a method for forming a trench in a semiconductor device, and more particularly to a method for forming a trench in a semiconductor substrate to form a device isolation film for electrical isolation.

As is well known, in semiconductor devices, a plurality of cells including unit elements such as transistors and capacitors are integrated in a limited area according to the capacity of the semiconductor device, and these cells are electrically connected for mutually independent operation characteristics. Isolation is required.

Therefore, as a means for electrical isolation between these cells, a LOCal Oxidation of Silicon (LOCOS) that recesses a semiconductor substrate and grows a field oxide film, and a wafer is vertically etched. Shallow Trench Isolation (STI), which is embedded in an insulating material, is well known.

Among these, STI makes narrow and deep trenches by using dry etching techniques such as reactive ion etching (RIE) or plasma etching, and fills the insulating film with the insulating film to fill the insulator with the buzz. The problem with the viking is eliminated. In addition, since the trench filled with the insulating film is flattened, the area occupied by the device isolation region is small, which is advantageous for miniaturization.

As described above, STI, which is advantageous in terms of securing an active region of the device, exhibits improved characteristics compared to LOCOS in terms of junction leakage current.

1A to 1J are process diagrams illustrating a device isolation film forming process to which a trench forming method of a semiconductor device according to the related art is applied. Referring to this, a trench forming method according to the prior art will be described.

Referring to FIG. 1A, a pad oxide film 12 is formed on a semiconductor substrate 11, and a pad nitride film 13 is laminated on the pad oxide film 12.

Referring to FIG. 1B, a bottom anti reflective coating 14 is formed on the pad nitride layer 13, and a photoresist pattern 15 is formed on the pad nitride layer 13.

Referring to FIG. 1C, after the photoresist pattern 15 is used as an etch barrier, the antireflection film 14 is selectively removed, and the pad nitride film 13 and the pad oxide film 12 are continuously removed to form a trench. The semiconductor substrate 11 is exposed.

Referring to FIG. 1D, the photoresist strip process and the cleaning process are performed to remove the photoresist pattern 15 and the anti-reflection film 14.

Referring to FIG. 1E, a trench T is formed by dry etching an exposed portion of the semiconductor substrate 11 to a predetermined thickness using the pad nitride film 13 as an etching barrier.

Referring to FIG. 1F, the pad nitride layer 13 is pulled back to a predetermined depth by performing a wet wet dip process using phosphoric acid having a good selectivity between the nitride and oxide layers as a wet etching chemical. As a result, the pad nitride film 13 is diped out wider than the trench formation region. This is to effectively bury the trench (T) in the subsequent process.

Referring to FIG. 1G, the trench liner oxide layer 16 is formed by performing an STI liner oxidation process, that is, growing the surface of the trench T through a thermal process.

Referring to FIG. 1H, a process of filling a trench is formed by forming an HDP (High Density Plasma) oxide film 17 on the entire surface of the structure including the trench T that has undergone the process of FIGS. 1A to 1G.

Referring to FIG. 1I, the surface of the entire structure having the trench embedded therein is subjected to a chemical mechanical polishing (CMP) process until the pad nitride layer 13 is exposed.

Referring to FIG. 1J, the pad nitride layer 13 is removed by performing a wet dip process using a phosphoric acid solution or the like.

As described above, in the trench forming method of the semiconductor device according to the related art, after forming the trench, the wet wet dip process is performed. When the phosphate chemical comes into contact with the trench surface, surface roughness becomes poor, and particles are formed. In addition, there was a problem in that the contamination of the furnace (furnace) equipment to perform the STI liner oxidation process, which is a subsequent process.

The present invention has been proposed in order to solve the problems of the prior art, and even before the trench is formed, a wet wet dip process may be performed so that the phosphate chemical may be removed through a subsequent trench etching process even if it contacts the surface of the semiconductor substrate.

The trench forming method of the semiconductor device according to the present invention includes forming a photoresist pattern in which a region in which a trench is to be opened after forming a pad nitride film on a semiconductor substrate, and using the photoresist pattern as an etching barrier. Exposing the semiconductor substrate in the region where the trench is to be formed by removing a nitride layer, performing a wet wet dip process, and performing full back etching of the pad nitride layer to a predetermined depth; and using the pad nitride layer as an etching barrier. Etching the exposed portion of the semiconductor substrate to form the trench.

According to the present invention, the moist wet dip process is performed prior to forming the trench so that even if the phosphate chemical comes into contact with the surface of the semiconductor substrate, it is removed through a subsequent trench etching process, thereby deteriorating the surface roughness of the semiconductor substrate, particularly the trench. It is effective to prevent contamination of the furnace equipment for subsequent processing.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

2 is a flowchart illustrating a trench forming method of a semiconductor device according to the present invention.

Referring to FIG. 2, the trench forming method according to the present invention may include forming a pad oxide film and a pad nitride film on a semiconductor substrate (S101), and forming a trench on the pad nitride film and then forming a trench on the pad nitride film. Forming a photoresist pattern in which the region is opened (S102); exposing the semiconductor substrate in the region where the trench is to be formed by removing the antireflection film, the pad nitride film, and the pad oxide film using the photoresist pattern as an etching barrier (S103). And performing a wet wet dip process to perform full back etching of the pad nitride layer by a predetermined depth (S104), and performing a photoresist strip process and a cleaning process to remove the photoresist pattern and the anti-reflection film (S105); Etching the exposed portion of the semiconductor substrate using the pad nitride layer as an etching barrier to form a trench (S106).

3A to 3I are process diagrams illustrating a device isolation film forming process to which a trench forming method of a semiconductor device according to the present invention is applied. With reference to this it will be described in detail a trench forming method according to the present invention.

Referring to FIG. 3A, a pad oxide film 202 is formed on a semiconductor substrate 201, and a pad nitride film 203 is stacked on a pad oxide film 202. Here, the pad oxide film 202 may be omitted as a film formed for the purpose of relieving stress between the semiconductor substrate 201 and the subsequent pad nitride film 203, and the low pressure furnace (Low Furnace) as the pad nitride film 203. Si 3 N 4 film formed in a manner is used.

Referring to FIG. 3B, an anti-reflection film 204 is formed on the pad nitride film 203, and a photoresist pattern 205 is formed on the pad nitride film 203. That is, after the photoresist is applied on the anti-reflection film 204, a photoresist pattern 205 is formed to open only the region where the trench is to be formed through an appropriate exposure and development process. The anti-reflection film 204 may be omitted as it is formed to reduce diffuse reflection during the etching process.

Referring to FIG. 3C, after the photoresist pattern 205 is used as an etching barrier, the anti-reflection film 204 is selectively removed, and the pad nitride film 203 and the pad oxide film 202 are successively removed to form the trench. The semiconductor substrate 201 is exposed.

Referring to FIG. 3D, the pad nitride layer 203 may be full-etched by a predetermined depth by performing a wet wet dip process using phosphoric acid having a good selectivity between the nitride layer and the oxide layer as a wet etching chemical solution. Dip out 203). This is to effectively bury the trench (T) in the subsequent process.

Here, according to the present invention, even before the trench is formed, a moist wet dip process may be performed so that the phosphate chemical may be removed through a subsequent trench etching process even if it contacts the surface of the semiconductor substrate. In addition, the reason for performing the wet wet dip process before removing the photoresist pattern 205 is that if the wet wet dip process is performed after removing the photoresist pattern 205, the thickness of the pad nitride layer 203 may be changed, and subsequent trench etching processes may be performed. This is to prevent the etching condition of the metal from changing.

Referring to FIG. 3E, the photoresist strip process and the cleaning process are performed to remove the photoresist pattern 205 and the anti-reflection film 204, and the exposed portion of the semiconductor substrate 201 using the pad nitride film 203 as an etching barrier. Dry etching to a predetermined thickness to form a trench (T). In this case, the etching of the semiconductor substrate 201 is stopped at an appropriate time by using an etch rate of the etching equipment and a trend of the progress lot.

Referring to FIG. 3F, a trench liner oxide layer 206 is formed by performing an STI liner oxidation process, that is, growing the surface of the trench T through a thermal process. When the liner oxide film 206 is used in this way, the stress agglomerated on the silicon substrate is reduced, and the diffusion action of dopants from the device isolation film to the silicon substrate is suppressed. It is known that the refresh characteristic is improved.

Referring to FIG. 3G, a process of filling the trench is formed by forming an HDP oxide layer 207 having excellent step coverage on the entire surface of the structure including the trench T that has been processed in FIGS. 3A to 3F.

Referring to FIG. 3H, the surface of the entire structure having the trench embedded therein is subjected to a chemical mechanical polishing process until the pad nitride layer 203 is exposed.

Referring to FIG. 3I, the pad nitride layer 203 is removed by performing a wet dip process using a phosphoric acid solution or the like.

It has been described so far limited to one embodiment of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.

1A to 1I are process diagrams illustrating a device isolation film forming process to which a trench forming method of a semiconductor device according to the prior art is applied;

2 is a process flowchart for explaining a trench forming method of a semiconductor device according to the present invention;

3A to 3I are process drawings for explaining a device isolation film forming process to which a method for forming a trench in a semiconductor device according to the present invention is applied;

<Explanation of symbols for the main parts of the drawings>

201: semiconductor substrate 203: pad nitride film

204: antireflection film 205: photoresist pattern

T: Trench

Claims (3)

Forming a photoresist pattern in which a region in which a trench is to be formed is opened after forming a pad nitride film on the semiconductor substrate; Exposing the semiconductor substrate in a region where the trench is to be formed by removing the pad nitride layer using the photoresist pattern as an etching barrier; Performing a wet wet dip process to etch the pad nitride layer back to a predetermined depth; Etching the exposed portion of the semiconductor substrate using the pad nitride layer as an etching barrier to form a trench Trench formation method of a semiconductor device comprising a. The method of claim 1, The trench forming method may further include removing the photoresist pattern by performing a photoresist strip process before performing the trench forming step after the full back etching step. Trench formation method of a semiconductor device comprising a. The method of claim 1, The wet wet dip process uses phosphoric acid as a wet etching chemical solution. Trench formation method of a semiconductor device.
KR1020070136329A 2007-12-24 2007-12-24 Method for forming trench of semiconductor device KR20090068634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070136329A KR20090068634A (en) 2007-12-24 2007-12-24 Method for forming trench of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070136329A KR20090068634A (en) 2007-12-24 2007-12-24 Method for forming trench of semiconductor device

Publications (1)

Publication Number Publication Date
KR20090068634A true KR20090068634A (en) 2009-06-29

Family

ID=40996003

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070136329A KR20090068634A (en) 2007-12-24 2007-12-24 Method for forming trench of semiconductor device

Country Status (1)

Country Link
KR (1) KR20090068634A (en)

Similar Documents

Publication Publication Date Title
KR100590383B1 (en) Method of forming a field oxide layer in semiconductor device
KR100741876B1 (en) Manufacturing method of semiconductor device having trench isolation prevented from divot
KR20080095621A (en) Method of forming an isolation layer in semiconductor device
US6503815B1 (en) Method for reducing stress and encroachment of sidewall oxide layer of shallow trench isolation
CN112786524B (en) Method for forming semiconductor device
KR100703836B1 (en) Method for forming trench type isolation layer in semiconductor device
KR20090068634A (en) Method for forming trench of semiconductor device
KR100344765B1 (en) Method for isolating semiconductor devices
KR100895382B1 (en) Method for manufacturing semiconductor device
KR100419754B1 (en) A method for forming a field oxide of a semiconductor device
KR100769127B1 (en) method for forming isolation film of semiconductor device
KR20090128914A (en) Method for gapfill in semiconductor device
KR100770455B1 (en) Manufacturing method for semiconductor device
KR20060075402A (en) Method of forming a isolation layer in semiconductor device
KR100430582B1 (en) Method for manufacturing semiconductor device
KR20090069364A (en) Method for forming trench of semiconductor device
KR100351905B1 (en) method for forming isolation film semiconductor device
KR100390240B1 (en) Manufacturing method for semiconductor device
KR100700283B1 (en) Method of fabricating the trench for isolation in semiconductor device
KR20060128152A (en) Method for manufacturing semiconductor device
KR20050118489A (en) Method for isolation in semiconductor device
KR20090071864A (en) Method for forming device isolation layer of semiconductor device
KR20020054666A (en) A method for forming a field oxide of semiconductor device
KR20010068403A (en) Method for isolating semiconductor devices
KR20030000132A (en) Forming method for field oxide of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application