KR20090066941A - Method for fabricating landing plug contact in semicondutor device - Google Patents

Abstract

A method for forming a landing plug contact of a semiconductor device is provided to improve a yield of the semiconductor device by performing efficiently a cell operation such as a normal read operation or a normal write operation. A gate electrode(130) including a hard mask layer is formed on a substrate(100). A spacer(140) is formed on a sidewall of the gate electrode. An interlayer dielectric(150) is formed to cover the gate electrode in which the spacer is formed. The interlayer dielectric is selectively etched to form a contact hole for exposing a substrate part between the gate electrodes. An oxidation process is performed to oxidize selectively a sidewall part of the gate electrode which is partially exposed in a contact hole forming process. A contact material is formed to bury a contact hole between the oxidized gate electrodes.

Description

Landing plug contact formation method of semiconductor device {Method for fabricating landing plug contact in semicondutor device}

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a landing plug contact of a semiconductor device.

As semiconductor devices are highly integrated, various methods have been attempted to manufacture semiconductor devices having better characteristics. In particular, as more unit cells have to be formed in the limited area, the contact size is also reduced with the substantial reduction of the cell area. Accordingly, in order to increase the operation efficiency of the device in the cell region and to further secure contact margins, a self aligned contact (SAC) process is applied to obtain an etch profile using an etch selectivity between oxide and nitride films. have.

However, in the process of forming a landing plug using a self-aligned contact process, various problems such as a SAC fail have occurred. In particular, as the size of the gate electrode required for the cell region is reduced, the open area is reduced during the self-aligned contact process. As the SAC open area decreases, the SAC process margins are approaching their limits, as well as the thickness of the spacers becoming thinner. Accordingly, the gate electrode sidewalls are partially exposed when the contact hole is formed to expose the portion of the cell region where the landing plug is to be formed. The exposed portion of the gate electrode causes a bridge defect between the contact material film, for example, a landing plug poly (LPP), embedded in the contact hole.

Such bridging defects make cell operation impossible, for example, normal operation of read or write, thereby lowering the yield of the device.

Accordingly, studies have been made to improve cell characteristics by stably securing SAC process margins.

According to an aspect of the present invention, there is provided a method of forming a landing plug contact of a semiconductor device, the method including: forming a gate electrode including a hard mask layer on a substrate; Forming a spacer on sidewalls of the gate electrode; Forming an interlayer insulating film covering the gate electrode on which the spacer is formed; Selectively etching the interlayer insulating film to form a contact hole exposing a substrate portion between the gate electrodes; Selectively oxidizing partially exposed gate electrode sidewall portions during the formation of the contact hole; And filling a contact material in a contact hole between the gate electrode in which the sidewall portion is selectively oxidized to form a landing plug contact.

Preferably, the gate electrode is made of an insulating film, a polysilicon film, and a tungsten film.

The hard mask layer and the spacer may be formed of a material layer having an etch selectivity with the interlayer insulating layer.

The material film having an etch selectivity with the interlayer insulating film is preferably formed of a silicon nitride film.

The forming of the contact hole is preferably performed by performing a self-aligned contact process.

Selectively oxidizing the gate electrode sidewall portion may include forming an oxide film on a portion of the exposed gate electrode sidewall portion and a substrate portion between the gate electrode by performing an oxidation process on the substrate on which the contact hole is formed; And selectively removing the oxide film formed on the substrate portion between the gate electrodes by performing a dry etching process.

The oxidation process is preferably performed by a selective oxidation process, a plasma oxidation process, or a thermal oxidation process.

In the oxidation process, it is preferable to perform an oxidation process using an oxygen plasma or an ozone plasma.

The oxidation process is preferably carried out at a process temperature of 700 to 750 ℃.

The oxide film is preferably formed to a thickness of 20 to 30 kPa.

The dry etching process is preferably performed for 30 to 60 seconds using an etching element containing NH ₃ and HF.

The forming of the landing plug contact may include forming a contact plug film on the gate electrode on which the sidewall portion is selectively oxidized; And a step of forming a landing plug contact, which is node-separated by a gate electrode by performing a planarization process on the contact plug film.

The contact plug film is preferably formed of a polysilicon film.

The polysilicon film is preferably formed to a thickness of 500 to 2000 kPa.

(Example)

Referring to FIG. 1, a trench isolation layer 110 may be formed to form an active region of a semiconductor substrate 100 by performing a trench trench isolation (STI) process.

Specifically, although not shown in detail, after forming the pad oxide film pattern and the pad nitride film pattern on the semiconductor substrate 100, the portions of the semiconductor substrate 100 exposed by the pad nitride film pattern and the pad oxide film pattern are selectively etched. To form an isolation trench. Subsequently, a high density plasma (HDP) oxide film is formed on the entire surface of the semiconductor substrate 100 on which the device isolation trench is formed, and then a planarization process, for example, chemical mechanical polishing (CMP), is embedded. The trench isolation layer 110 is formed to set the active region of the semiconductor substrate 100.

Subsequently, impurity ion implantation and heat treatment are performed to form a well or a channel on the semiconductor substrate 100 on which the trench device isolation layer 110 is formed.

Referring to FIG. 2, the recess trench 120 is formed by selectively etching the active region on the semiconductor substrate 100 where the active region is set by the trench isolation layer 110.

Specifically, after forming a mask pattern (not shown) for selectively exposing the position where the recess trench is to be formed on the semiconductor substrate 100, an etching process using the mask pattern as an etching mask is performed to obtain a channel length. It forms a recess trench 120 that extends further.

At this time, before forming the recess trench 120, in order to form a saddle fin transistor, the trench isolation layer 110 is etched by a predetermined thickness so that the active regions protrude from both sides of the active region. And the top surface can be exposed. By forming the recess trench in the protruding active region, it is possible to increase the width of the channel while increasing the length of the channel.

Referring to FIG. 3, the gate electrode 130 including the hard mask layer 134 is formed on the semiconductor substrate 100 on which the recess trench 120 is formed.

Specifically, after the insulating film 131, the conductive film 132, and the metal film 133 are formed on the semiconductor substrate 100, and the hard mask film 134 for the hard mask is formed, The gate etching process is performed to form the gate electrode 130 including the hard mask layer 134. In this case, the insulating film 131 may be formed of an oxide film having a thickness of 30 to 60 Å. The conductive film 132 may be formed of a polysilicon film having a thickness of 400-1500 mm. The metal film 133 may be formed of a hybrid tungsten film having a thickness of 400 to 600 Å.

 The hard mask layer 134 may be formed of an interlayer insulating layer that insulates a subsequent gate electrode and a material layer having a high etching selectivity. For example, the hard mask layer 134 may include an insulating material such as silicon nitride and may have a thickness of about 2000 to 2500 μm. The hard mask layer 134 serves to protect the gate electrode in a subsequent self-aligned contact process.

The spacer 130 is formed on sidewalls of the gate electrode 130 including the hard mask layer 134. The spacer 130 may include an insulating material such as silicon nitride film. The spacer 130 serves to protect the gate electrode during a subsequent process, for example, a self-aligned contact (SAC) process for forming a landing plug.

On the other hand, as the cell area is reduced as the device is highly integrated, the required critical width (CD) of the gate electrode 130 is reduced, and the thickness of the spacer 140 is also reduced.

Referring to FIG. 4, an interlayer insulating film 150 covering the gate electrode 130 on which the spacer 140 is formed is formed. The interlayer insulating layer 150 may be formed of an oxide film, for example, a spin on didlectric (SOD) film, but is not limited thereto.

A mask pattern 151 is formed on the interlayer insulating layer 150 to selectively expose the interlayer insulating layer 150 at the position where the landing plug contact is to be formed.

Referring to FIG. 5, the landing plug contact hole 160 exposing the semiconductor substrate 100 between the gate electrodes 130 by etching the exposed interlayer insulating layer 150 using the mask pattern 151 as an etch mask. Form.

In this case, the mask pattern 151 is used as an etch mask to perform a Self Aligned Contact (SAC) process, so that the hard mask 134 and the spacer 130 are barriers to etching during the formation of the landing plug contact hole 160. Act as a layer.

On the other hand, as the cell area of the semiconductor device is reduced, the open area is reduced during the self-aligned contact process. Accordingly, as the margin of the self-aligned contact process is insufficient and the thickness of the spacer becomes thinner, as shown in FIG. 5 in the process of forming the landing plug contact hole, the spacer 140 of the sidewall of the gate electrode 130 is damaged, The conductive film 132, for example, the polysilicon film of the gate electrode 130 is partially exposed.

The exposed portion 162 of the conductive layer 132 may have a subsequent landing plug poly (LPP) layer embedded in the landing plug contact hole 160 to form a conductive layer, for example, a polysilicon layer and a bridging property. Will cause defects.

Accordingly, in the exemplary embodiment of the present invention, the bridge defect between the landing plug poly and the conductive film can be suppressed by performing the following process.

Referring to FIG. 6, after removing the mask pattern, an oxidation process is performed to selectively oxidize the exposed portion of the conductive film 132 and the semiconductor substrate 100 during the formation of the landing plug contact hole 160 to selectively oxidize the oxide film 170. ). The oxidation process may be performed by a selective oxidation process, a plasma oxidation process or a thermal oxidation process. Alternatively, an oxide film may be formed by selectively oxidizing the exposed portion of the gate electrode and the exposed portion of the semiconductor substrate using oxygen plasma or ozone plasma.

In this case, the oxide film may be oxidized at a process temperature of 700 to 750 ° C. such that a portion of the conductive film 132 and the semiconductor substrate 100 exposed during the formation of the landing plug contact hole 160 are oxidized by about 20 to 30 kPa. Can be.

By selectively oxidizing the exposed conductive film portion, the conductive film exposed and damaged during the landing plug contact hole formation process is cured, and by the formed oxide film, a subsequent landing plug poly film and a conductive film such as a polysilicon film are formed. The bridge defect of the liver can be suppressed.

Referring to FIG. 7, an oxide film 170 formed on a portion of the semiconductor substrate 100 between the gate electrodes 130 may be selectively removed by performing a vertical dry etching process. The vertical dry etching process may be performed for 30 to 60 seconds using an etching source including NH ₃ and HF. By selectively removing only the oxide film formed on the semiconductor substrate 100 by performing a vertical etching process, the portion of the oxide film 171 formed on the exposed conductive film portion remains.

On the other hand, the dry dry etching process corresponds to a pre-cleaning process performed to remove the native oxide film formed on the semiconductor substrate before the landing plug poly film is formed.

Referring to FIG. 8, a landing plug contact hole is filled to form a landing plug poly (LPP) 180. Specifically, after the landing plug poly film is formed on the semiconductor substrate 100 on which the landing plug contact hole is formed, the gate electrode 130 is separated by performing a planarization process, for example, a chemical mechanical polishing (CMP) process. . The landing plug poly film may be formed to a thickness of about 500 to 2000 mm 3.

At this time, since the oxide film is formed on the exposed conductive film portion during the formation of the landing plug poly, it is possible to suppress the bridge defect of the landing film pole poly and the conductive film of the gate electrode.

According to an exemplary embodiment of the present invention, a semiconductor substrate portion which is oxidized together during the oxidation process after selectively oxidizing a conductive film, such as a polysilicon layer, of the gate electrode exposed during the landing plug contact hole formation process by a self-aligned contact process Is removed by performing a dry etching process so that the oxide film remains only on the exposed conductive film portion. Thereafter, the landing plug poly is embedded in the landing plug contact hole to secure the SAC process margin, and the bridge defect of the landing plug poly film and the gate conductive film can be suppressed. Accordingly, the yield of the device may be improved by effectively performing the normal operation of the cell operation, for example, read or write.

Although the present invention has been described in detail with reference to preferred embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the preferred technical spirit of the present invention. Of course.

1 to 8 are cross-sectional views illustrating a method for forming a landing plug contact of a semiconductor device according to the present invention.

Claims (14)

Forming a gate electrode including a hard mask film on the substrate; Forming a spacer on sidewalls of the gate electrode; Forming an interlayer insulating film covering the gate electrode on which the spacer is formed; Selectively etching the interlayer insulating film to form a contact hole exposing a substrate portion between the gate electrodes; Selectively oxidizing partially exposed gate electrode sidewall portions during the formation of the contact hole; And And forming a landing plug contact by filling a contact material in a contact hole between the gate electrode, the sidewall portion of which is selectively oxidized, to form a landing plug contact. The method of claim 1, And the gate electrode comprises an insulating film, a polysilicon film, and a tungsten film. The method of claim 1, And the hard mask layer and the spacer are formed of a material layer having an etch selectivity with respect to the interlayer insulating layer. The method of claim 3, And a material film having an etch selectivity with respect to the interlayer insulating film is formed of a silicon nitride film. The method of claim 1, The forming of the contact hole may be performed by performing a self-aligned contact process. The method of claim 1, Selectively oxidizing the gate electrode sidewall portion, Performing an oxidation process on the substrate on which the contact hole is formed to form an oxide film on a portion of the exposed gate electrode sidewall and a portion of the substrate between the gate electrode; And And selectively removing an oxide film formed on a portion of the substrate between the gate electrodes by performing a dry etching process. The method of claim 6, The oxidation process may be performed by a selective oxidation process, a plasma oxidation process, or a thermal oxidation process. The method of claim 6, The oxidation process is a landing plug contact forming method of a semiconductor device performing an oxidation process using an oxygen plasma or an ozone plasma. The method of claim 6, The oxidation process is a landing plug contact forming method of a semiconductor device performed at a process temperature of 700 to 750 ℃. The method of claim 6, The oxide film is a landing plug contact forming method of a semiconductor device formed to a thickness of 20 to 30Å. The method of claim 6, The dry etching process is a landing plug contact forming method of a semiconductor device performed for 30 to 60 seconds using an etching element containing NH ₃ and HF. The method of claim 1, Forming the landing plug contact, Forming a contact plug film on the gate electrode on which the sidewall portion is selectively oxidized; And And a step of forming a landing plug contact, the node being separated by a gate electrode by performing a planarization process on the contact plug film. The method of claim 12, And forming the contact plug film as a polysilicon film. The method of claim 13, The polysilicon film is a landing plug contact forming method of a semiconductor device to form a thickness of 500 to 2000Å.

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