KR20090066936A - Method for fabricating dielectric layer in semiconductor device - Google Patents

Method for fabricating dielectric layer in semiconductor device Download PDF

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KR20090066936A
KR20090066936A KR1020070134681A KR20070134681A KR20090066936A KR 20090066936 A KR20090066936 A KR 20090066936A KR 1020070134681 A KR1020070134681 A KR 1020070134681A KR 20070134681 A KR20070134681 A KR 20070134681A KR 20090066936 A KR20090066936 A KR 20090066936A
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insulating film
ion implantation
semiconductor device
forming
boron
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KR1020070134681A
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Korean (ko)
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노대호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

A method for forming an insulating layer of a semiconductor device is provided to minimize damage of a lower structure by performing a process at low temperature in comparison with a conventional process. A predetermined electrode is formed on a semiconductor substrate(100). An insulating layer is formed on the semiconductor substrate in order to fill a gap between the electrodes by using a liquid coating method. The insulating layer is formed at the temperature of 100 to 200 degrees centigrade. A thermal process is performed at the temperature of 200 to 400 degrees centigrade. A partial ion implantation process is performed on the insulating layer buried between the electrodes. The ions are one or more elements which are selected from a group including B, P, N, Cs, and As.

Description

반도체 소자의 절연막 형성방법{Method for fabricating dielectric layer in semiconductor device} Method for fabricating dielectric layer in semiconductor device

본 발명은 반도체 소자의 절연막 형성방법으로서, 좀 더 구체적으로 전극 간의 절연막 형성방법에 관한 것이다.The present invention relates to a method of forming an insulating film of a semiconductor device, and more particularly to a method of forming an insulating film between electrodes.

트랜지스터가 발명된 이후, 지난 20여 년간 반도체 메모리 소자의 디자인 룰(Rule)이 점차 축소됨에 따라, 한정된 면적 내에 수많은 메모리 소자를 구현할 수 있는 고도의 반도체 기술이 요구되고 있다. Since the invention of transistors, the design rules of semiconductor memory devices have been gradually reduced over the last 20 years, and thus, there is a demand for a high level of semiconductor technology capable of implementing a large number of memory devices in a limited area.

반도체 제조를 위한 단위공정들은 적층 공정, 식각 공정, 이온 주입 공정, 포토리소그라피 공정 등을 포함한다. 이와 같은 단위공정들 중에서 이온 주입 공정은, 강한 전기장에 의해 보론(B), 알세닉(As) 및 인(P) 등과 같은 도펀트 이온들을 가속시켜 웨이퍼 표면을 통과시키는 공정기술로서, 이와 같은 이온 주입을 통해 물질의 전기적인 특성을 변화시킬 수 있다.Unit processes for semiconductor manufacturing include a lamination process, an etching process, an ion implantation process, a photolithography process, and the like. Among these unit processes, the ion implantation process is a process technology for accelerating dopant ions such as boron (B), alcenic (As), and phosphorus (P) through a wafer surface by a strong electric field. This can change the electrical properties of the material.

현재 90nm 내지 75nm 정도의 디램 디바이스 제조의 절연 공정에서 하부 전극의 절연막으로 보론과 인이 포함된 산화규소를 사용하고 있으며, 일반적으로 가장 많이 사용되고 있는 물질로는 비피에스지(Boron Phosphorus Silicate Glass; BPSG) 가 있다. Currently, silicon oxide containing boron and phosphorus is used as an insulating film of the lower electrode in the insulation process of DRAM device manufacturing of about 90 nm to 75 nm, and the most commonly used material is BPSG (Boron Phosphorus Silicate Glass; BPSG). There is.

비피에스지(BPSG)의 경우 보론과 인의 농도를 조절하여 절연 공정을 수행하는데, 디바이스의 크기와 용도에 따라 일정한 전류특성을 유지할 수 있기 때문에, 깊이와 넓이가 각기 다른 전극 사이의 공극을 채울 수 있는 장점이 있다.In the case of BPSG, insulation process is performed by adjusting the concentration of boron and phosphorus, and it is possible to fill a gap between electrodes having different depths and widths because it can maintain constant current characteristics according to the size and use of the device. There is an advantage.

종래에는 보론과 인이 포함된 산화 규소, 즉 BPSG를 형성한 후 고온에서 열처리를 수행하여 전극 사이에 공극을 감소시켰다. BPSG막은 현재 상압 또는 준압의 화학증착법(CVD)을 이용하여 증착하고 있으며, 후속으로 흐름성을 주기 위한 열처리 공정이 진행되고 있다. Conventionally, silicon oxide containing boron and phosphorus, that is, BPSG was formed, and then heat treatment was performed at high temperature to reduce voids between the electrodes. BPSG films are currently deposited by using chemical vapor deposition (CVD) at atmospheric or semi-pressure, and a heat treatment process for providing flowability is subsequently performed.

그런데, 보론과 인이 산화규소 증착시 동시에 주입되기 때문에 전체의 농도 구배 조절이 어려우며, 후속 열처리에 따라서 내부에 존재하는 보론과 인이 일정한 채널을 형성할 경우 전기적 손실이 발생할 수 있다. 이러한 전기적 손실을 유발할 수 있는 채널은 대부분 보론의 급격한 확산으로 발생할 수 있다. However, since boron and phosphorus are simultaneously injected during the deposition of silicon oxide, it is difficult to control the overall concentration gradient, and electrical loss may occur when boron and phosphorus are formed in a constant channel according to subsequent heat treatment. Most of the channels that can cause such electrical loss can be caused by the rapid diffusion of boron.

따라서 디바이스의 크기가 달라짐에 따라 산화규소의 유동성을 주는 보론과 경화성을 부여하는 인의 농도를 조절함으로써 각 디바이스의 홀의 깊이와 넓이에 맞는 적당한 비율의 조정이 필요하므로 많은 공정 조정이 이루어져야 한다. 그리고 보론과 인이 장비 내벽에 흡착되면서 일정한 농도 이상으로 유지되어 일정시간이 지난 후 박막 내 보론과 인의 농도가 변하게 되어 절연특성 조절에 어려움이 있다.Therefore, as the size of the device is changed, it is necessary to adjust the boron giving the silicon oxide fluidity and the phosphorus concentration giving the hardenability, so that an appropriate ratio adjustment for the depth and width of the hole of each device is required. And boron and phosphorus is adsorbed on the inner wall of the equipment is maintained above a certain concentration and after a certain time the concentration of boron and phosphorus in the thin film is difficult to control the insulation properties.

본 발명의 반도체 소자의 절연막 형성방법은, 소정의 전극이 형성된 반도체기판 상에 액상 코팅법으로, 상기 전극 사이를 채우도록 절연막을 형성하는 단계; 및 상기 전극 사이에 매립된 절연막에 부분 이온 주입 공정을 수행하는 단계를 포함한다.An insulating film forming method of a semiconductor device of the present invention comprises the steps of: forming an insulating film to fill between the electrodes by a liquid coating method on a semiconductor substrate on which a predetermined electrode is formed; And performing a partial ion implantation process on the insulating film embedded between the electrodes.

상기 절연막을 100℃∼200℃의 온도에서 형성할 수 있다.The insulating film may be formed at a temperature of 100 ° C to 200 ° C.

상기 절연막을 형성한 다음에 200℃∼400℃에서 열처리를 수행하는 단계를 더 포함할 수 있다.After forming the insulating film, the method may further include performing heat treatment at 200 ° C. to 400 ° C. FIG.

절연막 형성-이온 주입의 공정을 반복적으로 수행할 수 있다.The process of insulating film formation-ion implantation can be performed repeatedly.

상기 이온 주입 원소는 보론(B), 인(P), 질소(N), 세슘(Cs), 알세닉(As) 중 어느 하나 이상으로 수행할 수 있다.The ion implantation element may be performed by any one or more of boron (B), phosphorus (P), nitrogen (N), cesium (Cs), and alcenic (As).

부분 이온 주입 후, 열처리를 수행하는 단계를 더 포함할 수 있다.After partial ion implantation, the method may further include performing a heat treatment.

상기 열처리는 300℃∼400℃에서 수행할 수 있다.The heat treatment may be carried out at 300 ℃ to 400 ℃.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다. 그러나 본 발명은 여러 가지 다양한 형태로 구현될 수 있으며 여기에서 설명하는 실시예에 한정되지 않는다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

도1 내지 도 4는 본 발명의 실시예에 따른 게이트 전극 사이를 절연시키는 절연막 형성에 관한 방법을 설명하기 위하여 나타낸 도면들이다.1 to 4 are diagrams for explaining a method for forming an insulating film to insulate between gate electrodes according to an embodiment of the present invention.

도 1을 참조하면, 반도체기판(100) 상에 게이트 절연막(110), 게이트 도전층 으로서의 폴리실리콘막(120), 저저항층으로서의 금속실리사이드막(130) 및 하드마스크(140)를 차례로 적층한다. 다음으로 선택적인 노광, 현상 및 식각 공정을 수행하여 게이트 스택(110∼140)을 형성한다. Referring to FIG. 1, a gate insulating layer 110, a polysilicon layer 120 as a gate conductive layer, a metal silicide layer 130 as a low resistance layer, and a hard mask 140 are sequentially stacked on the semiconductor substrate 100. . Next, the gate stacks 110 to 140 are formed by performing selective exposure, development, and etching processes.

다음, 실리콘을 포함하는 전구체, 예를 들면 실란(SiH4) 또는 디클로로실란(SiH2C12; DCS) 전구체와 암모니아(NH3) 반응가스를 유입시켜 게이트 스택(110~140)을 감싸는 캡핑막(150)을 형성한다. 캡핑막(150)은 게이트 패턴의 비정상적인 산화를 억제한다. Next, a capping layer surrounding the gate stacks 110 to 140 by introducing a precursor including silicon, for example, a silane (SiH 4 ) or dichlorosilane (SiH 2 C 12 ; DCS) precursor and an ammonia (NH 3 ) reaction gas. 150 is formed. The capping layer 150 suppresses abnormal oxidation of the gate pattern.

도 2를 참조하면, 저온공정으로 이루어지는 액상 코팅법 또는 액상 증착법을 이용하여 상기 게이트 패턴이 형성된 사이를 절연막(160)으로 매립한다.Referring to FIG. 2, an insulating layer 160 is filled between the gate patterns formed by using a liquid coating method or a liquid deposition method.

액상 코팅법은, 잘 알려진 바와 같이, 100℃∼200℃ 정도의 온도에서 반도체기판을 소정 속도로 회전시키면서 액상의 절연막을 코팅하는 방법이고, 액상 증착법은 반도체기판 상에 예를들면, 졸-겔 형태의 절연물질을 분사시켜 증착하는 방법이다.As is well known, the liquid coating method is a method of coating a liquid insulating film while rotating a semiconductor substrate at a predetermined speed at a temperature of about 100 ° C. to 200 ° C., and the liquid vapor deposition method is, for example, a sol-gel on a semiconductor substrate. It is a method of depositing by spraying an insulating material of the form.

종래에는 보론과 인이 동시에 함유된 준압 증착법으로 실리콘막으로 절연막을 형성한다. 400℃∼600℃의 온도에서 절연막을 증착하면서 동시에 보론 및 인이 주입되도록 하였다. 절연막을 증착한 다음에는, 박막의 치밀화를 위하여 500℃∼800℃에서 후속 열처리를 수행하였다. 이때 절연막의 형성 및 후속 열처리 공정에서 주입된 불순물들의 확산이 이루어지므로 간헐적인 전류의 손실이 발생할 수 있고, 하부 층에 고온 공정으로 인한 영향을 줄 수 있다.Conventionally, an insulating film is formed of a silicon film by a quasi-pressure deposition method simultaneously containing boron and phosphorus. Boron and phosphorus were implanted at the same time while depositing an insulating film at a temperature of 400 ℃ to 600 ℃. After the deposition of the insulating film, subsequent heat treatment was performed at 500 ° C to 800 ° C for densification of the thin film. At this time, since the impurity implanted in the formation of the insulating film and the subsequent heat treatment is performed, an intermittent loss of current may occur, and the lower layer may be affected by the high temperature process.

반면에, 본 발명의 저온 액상 코팅법은 공정 온도 자체가 낮아서, 하부 층에 주는 영향을 감소시킬 수 있으며 불순물들의 확산을 최소화할 수 있다.On the other hand, the low temperature liquid coating method of the present invention has a low process temperature itself, thereby reducing the influence on the lower layer and minimizing the diffusion of impurities.

도 3을 참조하면, 상기 절연막(160)에 절연막의 치밀화 및 공극의 발생을 억제하기 위하여 이온 주입공정을 수행한다. 이때, 상기 이온 주입은 게이트 패턴(150) 사이의 절연막에 부분적으로 수행한다. Referring to FIG. 3, an ion implantation process is performed on the insulating layer 160 to suppress densification of the insulating layer and generation of voids. In this case, the ion implantation is partially performed on the insulating film between the gate patterns 150.

부분 이온 주입공정은 액상 코팅으로 형성된 박막의 물성을 조절하기 위하여 사용할 수 있다. 또한 부분 이온 주입시 이온의 농도를 조절함으로써 절연성을 높일 수 있다. 그리고 이온 주입 공정은 게이트 패턴 사이의 깊은 하단까지 이온을 전달시키기 위하여 높은 에너지를 가할 경우가 존재하므로 게이트 패턴 사이의 폭이 좁고 깊이가 깊은 경우 높은 이온에너지를 통하여 이온을 전달하도록 한다.Partial ion implantation process can be used to control the properties of the thin film formed by the liquid coating. In addition, insulation can be improved by controlling the concentration of ions during partial ion implantation. In the ion implantation process, high energy is applied to transfer ions to deep bottoms between the gate patterns, and thus, when the widths between the gate patterns are narrow and deep, the ions are transferred through the high ion energy.

이때 주입되는 이온의 양과 에너지는 게이트 패턴 사이의 간격과 깊이에 따라 달라진다. 상기 절연성을 높이기 위한 이온으로는, 질소(N), 세슘(Cs) 등의 이온이나 흐름성과 밀도를 조절하기 위한 다른 이온을 사용할 수 있다.In this case, the amount and energy of implanted ions vary depending on the spacing and depth between the gate patterns. As the ions for increasing the insulation, ions such as nitrogen (N) and cesium (Cs), and other ions for adjusting the flowability and density can be used.

또한 부분 이온주입시 에너지와 방향을 조절하여 게이트 패턴의 측면 쪽에는 인, 바닥 쪽에는 보론을 주입시킬 수 있으며, 이 경우 기존의 절연막보다 높은 절연성을 유지할 수 있다. 본 발명의 경우, 후속의 저온 열처리 공정에서의 불순물의 이동이 기존의 준압 증착법보다 적으므로 적당한 밀도를 유지하면서 우수한 절연성을 가질 수 있다. In addition, by controlling the energy and direction during partial ion implantation, it is possible to inject boron into the side of the gate pattern, and boron to the bottom side, in which case it can maintain a higher insulation than the conventional insulating film. In the case of the present invention, since the impurity movement in the subsequent low temperature heat treatment process is smaller than the conventional semi-pressure deposition method, it can have excellent insulation while maintaining a suitable density.

열처리 공정에서의 보론의 확산에 의한 전기적 손실을 막기 위하여, 국부적인 이온 주입시 인이 많은 층을 게이트 패턴 사이의 절연층 외벽에 형성시키면 보 론의 확산이 상당부분 억제되고 이에 따라 전기적 손실을 미리 예방할 수 있다.In order to prevent the electrical loss caused by the diffusion of boron in the heat treatment process, forming a phosphorus-rich layer at the local ion implantation on the outer wall of the insulating layer between the gate patterns significantly suppresses the diffusion of the boron and accordingly prevents the electrical loss in advance. It can be prevented.

또한 이온 주입에 의하여 얻을 수 있는 다른 효과는 표면 개질이다. 이온 주입 공정의 특성상 표면에 이온밀도가 증가하게 되는 부수적인 효과를 얻을 수 있다. 그리고 효과적인 이온 주입을 하기 위하여 증착 - 이온주입 - 증착 - 이온 주입의 공정을 여러 차례 반복 수행도 가능하다.Another effect that can be obtained by ion implantation is surface modification. Due to the nature of the ion implantation process, the side effect of increasing the ion density on the surface can be obtained. In order to effectively carry out ion implantation, the process of deposition-ion implantation-deposition-ion implantation can be repeated several times.

도 4를 참조하면, 부분 이온 주입 공정이 수행된 절연막에 300℃∼400℃에서 열처리를 수행하여 하부 전극 간의 절연막(160)을 완성한다.Referring to FIG. 4, an insulating film 160 between lower electrodes is completed by performing heat treatment at 300 ° C. to 400 ° C. on the insulating film on which the partial ion implantation process is performed.

본 발명에 따르면, 기존의 공정에 비하여 낮은 온도로 공정을 수행할 수 있어, 하부구조의 손상을 최소화시킬 수 있다. 부분 이온 주입을 이용하여 기능성 있는 절연막을 형성할 수 있고, 기존의 준압 증착 공정에 비하여 우수한 절연 특성을 유지할 수 있다. 그리고 이온 주입 농도, 주입되는 이온의 종류를 변화시킴으로써, 다양한 특성의 절연막의 제조가 가능하고 다른 절연막 형성에도 응용이 가능하다.According to the present invention, it is possible to perform the process at a lower temperature than the existing process, it is possible to minimize damage to the underlying structure. By using partial ion implantation, a functional insulating film can be formed, and excellent insulating properties can be maintained as compared with conventional quasi-pressure deposition processes. By changing the ion implantation concentration and the kind of implanted ions, it is possible to manufacture an insulating film having various characteristics and to apply to other insulating film formation.

이상 본 발명은 게이트 스택의 절연막을 형성하는 공정에 적용한 것을 예를 들어 설명하였으나, 금속 배선의 매립공정, 캐패시터의 매립공정, 플래쉬, CMOS 등의 형성공정에도 본 발명을 유용하게 적용할 수 있다.Although the present invention has been described with reference to an example applied to the process of forming the insulating film of the gate stack, the present invention can be usefully applied to the process of embedding the metal wiring, the process of embedding the capacitor, the process of forming a flash, a CMOS, and the like.

도 1 내지 도 4는 본 발명에 따른 반도체 소자의 절연막 형성방법을 설명하기 위하여 나타낸 도면이다.1 to 4 are diagrams for explaining a method of forming an insulating film of a semiconductor device according to the present invention.

Claims (7)

소정의 전극이 형성된 반도체기판 상에 액상 코팅법으로, 상기 전극 사이를 채우도록 절연막을 형성하는 단계; 및Forming an insulating film on the semiconductor substrate on which a predetermined electrode is formed by a liquid coating method to fill the gaps between the electrodes; And 상기 전극 사이에 매립된 절연막에 부분 이온 주입 공정을 수행하는 단계를 포함하는 반도체 소자의 절연막 형성방법.And performing a partial ion implantation process on the insulating film embedded between the electrodes. 제1항에 있어서,The method of claim 1, 상기 절연막을 100℃∼200℃의 온도에서 형성하는 반도체 소자의 절연막 형성방법.An insulating film forming method for a semiconductor device, wherein the insulating film is formed at a temperature of 100 ° C to 200 ° C. 제1항에 있어서,The method of claim 1, 상기 절연막을 형성한 다음에 200℃∼400℃에서 열처리를 수행하는 단계를 더 포함하는 반도체 소자의 절연막 형성방법.Forming an insulating film, and then performing heat treatment at 200 ° C to 400 ° C. 제1항에 있어서,The method of claim 1, 절연막 형성-이온 주입의 공정을 반복적으로 수행하는 반도체 소자의 절연막 형성방법.An insulating film formation method of a semiconductor device which repeatedly performs a process of insulating film formation-ion implantation. 제1항에 있어서,The method of claim 1, 상기 이온 주입원소는 보론(B), 인(P), 질소(N), 세슘(Cs), 알세닉(As) 중 어느 하나 이상으로 수행하는 반도체 소자의 절연막 형성방법.The ion implantation element is a method of forming an insulating film of a semiconductor device performed by any one or more of boron (B), phosphorus (P), nitrogen (N), cesium (Cs), alcenic (As). 제1항에 있어서,The method of claim 1, 부분 이온 주입 후, 열처리를 수행하는 단계를 더 포함하는 반도체 소자의 절연막 형성방법.And performing a heat treatment after the partial ion implantation. 제6항에 있어서,The method of claim 6, 상기 열처리는 300℃∼400℃에서 수행하는 반도체 소자의 절연막 형성방법.The heat treatment is a method of forming an insulating film of a semiconductor device performed at 300 ℃ to 400 ℃.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020520120A (en) * 2017-05-13 2020-07-02 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ Fluid deposition and high density plasma treatment process cycles for high quality void filling.
WO2023132446A1 (en) * 2022-01-06 2023-07-13 삼성디스플레이 주식회사 Light-emitting element, method for manufacturing same, and display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020520120A (en) * 2017-05-13 2020-07-02 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ Fluid deposition and high density plasma treatment process cycles for high quality void filling.
WO2023132446A1 (en) * 2022-01-06 2023-07-13 삼성디스플레이 주식회사 Light-emitting element, method for manufacturing same, and display device

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