KR20090063078A - Semiconductor storage device and method for operating the same - Google Patents

Abstract

A semiconductor memory and its operation method are provided, which maintain the capacitive balance of the reference dataline and sense line to the utmost. A semiconductor memory comprises the memory cells and sense circuit(100). Memory cells are connected to the first and the second column trees. Sensing circuit reads memory cells. A column tree connected to the memory cell which is once selected among the first and second column trees is electrically connected to the sense line by the sensing circuit(SA). The column tree connected to the memory cell which is not selected to read among the first and second column trees is electrically connected to the reference sense line(RSA) by the sensing circuit.

Description

Semiconductor memory device and its operation method {SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR OPERATING THE SAME}

The present invention relates to a semiconductor memory device and an operation method thereof.

As described in Japanese Laid-Open Patent Publication No. 202-90, hereinafter referred to as Reference Document 1, one of a plurality of bit lines constituting a memory array in a nonvolatile semiconductor memory is selectively connected to one of the main bit lines. One of the plurality of main bit lines is selectively connected to one of the data lines. In addition, the sense signal input terminal of the differential amplifier constituting the sense circuit is connected to the sense line connected to the data line, and the reference signal input terminal is respectively connected to the reference sense line to determine the data read from the memory cell.

In the differential amplifier constituting the sense circuit, in terms of read speed and immunity to noise, it is difficult to accurately match the capacitance of the reference sense line to the capacitance of the sense line, and becomes weak against noise because of the different places where the capacitance is placed. There is a problem such as a disadvantage occurs.

In order to solve such a problem, Reference Document 1 describes a first and second column tree including a memory array in which first and second memory cells are disposed and a wiring group through which data of the first and second memory cells are transferred. A configuration is described in which a first memory cell is selected to couple a first column tree side to a sense signal input of a differential amplifier and a second column tree side to a reference signal input to obtain a capacitance balance.

2 is a memory block diagram illustrating a memory array configuration for obtaining a capacity balance of an input terminal of a differential amplifier. Referring to FIG. 2, a first column tree is a wiring group through which data of a first memory cell is transferred, and includes a first intermediate data line IDL01, a main bit line MBL0-01 and MBL1-01, and a bit line Bi. : BL0, Bi: BL1, Bi: BL4, Bi: BL5, Bj: BL0, Bj: BL1, Bj: BL4, Bj: BL5). A memory cell (not shown) is connected to the bit line BL. Bi and Bj represent blocks.

The second column tree is a wiring group through which data of another memory cell is transferred, and includes a second intermediate data line IDL23, a main bit line MBL0-23 and MBL1-23, and a bit line Bi: BL2, Bi: BL3, Bi: BL6, Bi: BL7, Bj: BL2, Bj: BL3, Bj: BL6, Bj: BL7). As in the case of the first column tree, a memory cell is connected to the bit line BL.

When the memory cells in the first column tree are read, the column conversion gate 0101 couples the first column tree to the data line DL in response to the first column conversion signal SW01, referring to the second column tree. To the data line RDL. In addition, when the memory cells in the second column tree are read, the column conversion gate 0101 couples the second column tree to the data line DL in response to the second column conversion signal SW23, and the first column. Join the tree to the reference data line (RDL).

The data line DL is coupled to the sense signal input side of the differential amplifier in the sense circuit, and the reference data line RDL is coupled to the reference signal input side. The sensing circuit is described below. In this way, among the first and second column trees, the column tree including the read-selected memory cells is coupled to the data line DL, and the non-selected column tree is coupled to the reference data line RDL. Since the configurations of the first and second column trees are the same, the capacity of the tree is the same. That is, it is possible to equalize the capacitance added to the data line DL with the capacitance added to the reference data line RDL.

3 is a circuit diagram illustrating a sense amplifier circuit. Referring to FIG. 3, the sense amplifier circuit 200 is a circuit connected to the data line DL and the reference data line RDL of FIG. 2 to determine the read data. The sense amplifier circuit 200 includes a separation circuit 50-2, a sense line SA and a data line DL for controlling by applying a predetermined bias so that the potential of the data line DL does not exceed a predetermined voltage. The read data is confirmed by amplifying a minute potential difference between the load circuit 30-2, the sense line SA, and the reference sense line RSA, which operate as a load of the reference sense line RSA and the reference data line RDL. The differential amplifier 20, and the output buffer circuit 10 for temporarily storing the data determined in the differential amplifier 20.

The gates of the isolation NMOS transistors 51 and 52 of the isolation circuit 50-2 are all connected to the bias line BIAS, and the source of the NMOS transistor 51 is connected to the reference data line RDL and the NMOS transistor ( The source of 52 is connected to the data line DL, respectively. In addition, the source of the NMOS transistor 51 is connected to the drain of the NMOS transistor 56, the source of the NMOS transistor 56 is grounded, and the gate of the NMOS transistor 56 is connected to the reference potential signal line VREF. do. Isolation circuit 50-2 includes NMOS transistors 54 for equalizing, both ends of which are connected to NMOS transistors 53 and 55 for capacitance balance, respectively, and the gates of the equalization signal lines EQ. ) Is connected. Each source and drain of the NMOS transistors 53 and 55 for capacitance balancing are shorted and connected to the reference data line RDL and the data line DL, respectively. A reference current source (not shown) is connected to the reference data line RDL.

In the PMOS transistors 35 to 38 constituting the load of the load circuit 30-2, the source of the PMOS transistor 35 is connected to the power supply line VCC, and the gate and the drain are connected to the source of the PMOS transistor 36. Connected. The gate of the PMOS transistor 36 is connected to the load enable signal LOADEN, and the drain is connected to the drain of the isolation NMOS transistor 51. Similarly, the source of the PMOS transistor 37 is connected to the power supply line VCC, and the gate and the drain are connected to the source of the PMOS transistor 38. The gate of the PMOS transistor 38 is connected to the load enable signal line LOADEN, and the drain is connected to the gate of the isolated NMOS transistor 52.

The source of the PMOS transistor 31 and the source of the PMOS transistor 36 are connected to the power supply line VCC, and each gate is connected to the enable inversion signal line nEN. The drain of the PMOS transistor 31 is connected to the source of the PMOS transistor 32, and the drain of the PMOS transistor 33 is connected to the source of the PMOS transistor 34. The gates of the PMOS transistor 32 and the PMOS transistor 34 are connected to the drain of the PMOS transistor 32 to form a mirror circuit, and are connected to the drain side of the separated NMOS transistor 51. The drain of the PMOS transistor 34 is connected to the drain side of the isolation NMOS transistor 52.

The load circuit 30-2 includes an equalization PMOS transistor 40, and both ends of the equalization PMOS transistor 40 are connected to the capacitive balance PMOS transistors 39 and 41, respectively, and the gate is the equalization inversion signal line nEQ. Is connected to. Each source and drain of the capacitor balanced PMOS transistors 39 and 41 are shorted and connected to the drain side of the separate NMOS transistors 51 and 52. The load circuit 30-2 includes capacitive balanced PMOS transistors 42 to 44, and each source and drain of the capacitive balanced PMOS transistors 42 and 43 are shorted to drain and NMOS transistor 51 of the PMOS transistor 36. Are connected between the drain of the PMOS transistor 38 and the drain of the NMOS transistor 52, and each gate is connected to the drain of the PMOS transistor 38. Similarly, the source and drain of the PMOS transistor 44 are shorted and connected to the power supply line VCC, and the gate is connected to the connection node of the PMOS transistors 42 and 43.

The source of the PMOS transistor 21 of the differential amplifier 20 is connected to the power supply line VCC, and the gate is connected to the enable inversion signal line nEN. The sources of the PMOS transistors 22 and 24 are both connected to the drains of the PMOS transistors 21, and the gates are connected to the drains of the NMOS transistors 23 and 25, respectively. The gates of the PMOS transistors 22 and 24 are connected to the drains of the PMOS transistors 38 and 36 through the sense line SA and the reference sense line RSA, respectively. The sources of the NMOS transistors 23 and 25 are grounded, and each gate is connected to the drain of the NMOS transistor 25 to form a mirror circuit. Both ends of the equalizing NMOS transistor 26 are connected to the drains of the PMOS transistors 22 and 24, respectively, and the gate is connected to the equalizing signal line EQ.

The input terminal of the inverter 11 of the output buffer circuit 10 is connected to the connection node of the drain of the PMOS transistor 22 and the drain of the NMOS transistor 23, and the output terminal is connected to the output signal line nSAOUT.

In the following, a read operation is described. Referring to FIG. 2, the first column select decoder 0102 decodes a column select internal address signal, so that one of the plurality of first column select signals Bi: H0 to Bi: H3 and Bj: H0 to Bj: H3 is decoded. Select to activate. As a result, the gate of one of the first column gates 0103-Bi: 0 and 0103-Bj: 1 is turned on, and one of the bit lines Bi: BL0 to Bi: BL3 and Bj: BL0 to Bj: BL3 is turned on. Is connected to the main bit lines MBL0-01 and MBL0-23. At the same time, the gate of one of the first column gates 0103-Bi: 1 and 0103-Bj: 1 is turned on, so that one of the bit lines Bi: BL4 to Bi: BL7 and Bj: BL4 to Bj: BL7 is main It is connected to the bit lines MBL1-01 and MBL1-23.

The second column select decoder 0104 decodes the column select internal address signal to select and activate one of the plurality of second column select signals D0 and D1. As a result, one of the main bit lines MBL0-01 and MBL1-01 is connected to the first intermediate data line IDL01, and at the same time, one of the main bit lines MBL0-23 and MBL1-23 is connected to the second intermediate data line. It is connected to the data line IDL23.

The column transform selection decoder 0160 decodes the column select internal address signal to select one of the first column transform signals SW01 and SW23.

When the memory cell in the first column tree is selected, the conversion signal SW01 is high and the conversion signal SW23 is low. As a result, the first intermediate data line IDL01 is connected to the data line DL, and the second intermediate data line IDL23 is connected to the reference data line RDL.

When the memory cell in the second column tree is selected, the conversion signal SW0 is low and the conversion signal SW23 is high. As a result, the second intermediate data line IDL23 is connected to the data line DL, and the first intermediate data line IDL01 is connected to the reference data line RDL. That is, the column tree including the read-selected memory cell is coupled to the data line DL to transfer the data signal of the memory cell, and the unselected column tree is coupled to the reference data line RDL to obtain the capacity balance.

Referring to FIG. 3, the source of the isolation NMOS transistor 51 of the isolation circuit 50-2 is connected to the reference data line RDL and the source of the isolation NMOS transistor 52 is connected to the data line DL, respectively. Receive a read data signal. Prior to reception of the read data signal, the equalizing NMOS transistor 54, the equalizing PMOS transistor 40, and the equalizing NMOS transistor of the separation circuit 50-2, the load circuit 30-2, and the differential amplifier 20. The gate of 26 receives the equalization signal EQ or the equalization inversion signal nEQ, and sets the potential of each node to the equipotential. In this case, the gate capacitances of the capacitance balanced PMOS transistors 42 to 44 are set to be equivalent to the gate capacitances of the PMOS transistors 32 and 34 constituting the mirror circuit, and to the wiring of the load circuit 30-2. Balance the incidental capacity.

When the selected memory cell is an on cell that holds data "1", the read data signal is transferred to the sense line SA via the data line DL. Since the reference current source connected to the reference data line RDL is set to half of the amount of current flowing on the on-cell, it is amplified by passing through each of the separate NMOS transistors 51 and 52, so that the load circuit 30-2 The sense line SA goes low and the reference sense line RSA goes high. This potential difference is amplified by the differential amplifier 20 and output as data "1" to the output signal line nSAOUT via the output buffer circuit 10.

When the selected memory cell is an off cell that holds data "0", the memory cell does not flow current, so the potential of the data line DL is higher than the potential of the reference data line RDL. This potential is amplified by passing through the separate NMOS transistors 51 and 52, so that in the load circuit 30-2 the sense line SA is at high level and the reference sense line RSA is at low level. This potential difference is amplified by the differential amplifier 20 and output as data " 0 " through the output buffer circuit 10 to the output signal line nSAOUT.

In this configuration, however, the column conversion gate 0101 is disposed between the first and second column trees and the sensing circuit 200, so an independent circuit for the column conversion gate is required, and a layout area for it is also required. In other words, the increase of the circuit and the increase of the chip area are caused, which is a factor that increases the design and the cost of the chip.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a column conversion function that maintains the capacity balance of the sense line and the reference data line to the maximum, and minimizes the increase of the conversion circuit and the increase of the chip area. There is provided a semiconductor memory device including a sensing circuit.

In an embodiment, a semiconductor memory device may include memory cells connected to first and second column trees; And a sensing circuit for reading the memory cells, the sensing circuit electrically coupling a column tree connected to a read selected memory cell of the first and second column trees to a sense line and to a non-selected memory cell. The tree is electrically connected to the reference sense line to perform a read operation.

In example embodiments, the sensing circuit electrically connects the first and second column trees to the sensing line and the reference sensing line, thereby balancing the capacitance connected to the sensing line with the capacitance connected to the reference sensing line. Adjust.

In example embodiments, the sensing circuit electrically connects the first and second column trees to the sensing line and the reference sensing line, respectively, in response to a first control signal. The sensing circuit electrically connects the first and second column trees to the reference sense line and the sense line, respectively, in response to a second control signal. The sense circuit equalizes the nodes inside the sense circuit in response to the first and second control signals.

A method of operating a semiconductor memory device including memory cells connected to first and second column trees and a sensing circuit for reading the memory cells may be configured in response to first and second control signals. Equalize nodes within the sense circuit; Electrically connecting the first and second column trees to a sense line and a reference sense line of the sense circuit, respectively, in response to the first control signal; The first and second column trees are electrically connected to the reference sense line and the sense line, respectively, in response to the second control signal.

In example embodiments, a column tree connected to a read selected memory cell among the first and second column trees may be electrically connected to the sensing line.

In example embodiments, the first and second column trees are connected to the sensing line and the reference sensing line, thereby balancing capacitances connected to the sensing line and the reference sensing line, respectively.

In an embodiment, a memory system may include a semiconductor memory device; And a controller for controlling the semiconductor memory device, the semiconductor memory device comprising: memory cells connected to first and second column trees; And a sensing circuit for reading the memory cells, the sensing circuit electrically coupling a column tree connected to a read selected memory cell of the first and second column trees to a sense line and to a non-selected memory cell. The tree is electrically connected to the reference sense line to perform a read operation.

In an embodiment, the semiconductor memory device and the controller are integrated into one semiconductor device.

According to the present invention, since the column conversion circuit included in the sensing circuit operates as an equalization circuit, it is possible to provide a semiconductor memory device capable of minimizing the increase of the circuit and the increase of the chip area and enabling a read operation resistant to noise at high speed. It is possible.

An embodiment of a semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings. 1 is a circuit diagram illustrating a sensing circuit according to an exemplary embodiment of the present invention. Referring to FIG. 1, the sensing circuit 100 is a circuit that determines data read by being connected to first and second data lines DL1 and DL2 connected to first and second column trees described below. The sensing circuit 100 includes a separation circuit 50-1 and a first data line DL1 for applying and controlling a predetermined bias so that the potentials of the first and second data lines DL1 and DL2 do not exceed a predetermined potential. ) And the minute circuit between the load circuit 30-1, the sense line SA, and the reference sense line RSA, which operate as a load of the sense line SA, the second data line DL2, and the reference sense line RSA. A differential amplifier 20 for amplifying a potential difference to confirm the read data, and an output buffer circuit 10 for temporarily storing the data determined by the differential amplifier 20.

In an embodiment of the present invention, since the column conversion gate 0101 described in FIG. 2 does not exist, and the same function as the column conversion gate 0101 of FIG. 2 is included in the sensing circuit, the reference data line RDL is It functions as a data line. As a result, the first and second column trees are connected to the first data line DL1 and the second data line DL2, respectively. In addition, a reference current source (not shown) connected to the reference data line RDL in FIG. 2 is also included in the sensing circuit.

Referring back to FIG. 1, in the isolation circuit 50-1, the drains of the NMOS transistors 57 and 58 are connected to the second data line DL2 and the first data line DL1, respectively, and the source is the NMOS transistor. It is connected to the drain of 56, and the gates of the NMOS transistors 57 and 58 are different from the isolation circuit 50-2 in Fig. 3 because they are connected to the reference inversion signal line nREF and the reference signal line REF. .

The load circuit 30-1 includes the column conversion circuit 49, and in that there is no equalizing PMOS transistor 40 and the capacity balance PMOS transistors 39 and 41 in FIG. Different from 30-2). Since the differential amplifier 20 and the output buffer circuit 10 are the same as in FIG. 3, detailed descriptions thereof will be omitted.

In the column conversion circuit 49, one end of the first PMOS transistor 45 and the second PMOS transistor 46 is connected to the reference sense line RSA, and the third PMOS transistor 47 and the fourth PMOS transistor 48 are connected. One end of) is connected to the sense line SA. The other ends of the first PMOS transistor 45 and the third PMOS transistor 47 are connected to the second data line DL2, and the other ends of the second PMOS transistor 46 and the fourth PMOS transistor 48 are first data. It is connected to the line DL1. Gates of the first PMOS transistor 45 and the fourth PMOS transistor 48 are connected to the first column conversion signal line SEL1, and gates of the second PMOS transistor 46 and the third PMOS transistor 47 are connected to each other. It is connected to the second column conversion signal line SEL2.

In the following, a read operation is described. Referring to FIG. 1, sources of the isolation NMOS transistors 51 and 52 of the isolation circuit 50-1 are connected to the second data line DL2 and the first data line DL1, respectively, to receive a read data signal. do. Prior to the reception of the read data signal, the gates of the equalization NMOS transistor 54 and the equalization NMOS transistor 26 of the isolation circuit 50-1 and the differential amplifier 20 receive the equalization signal to reduce the potential of each node. Set to equipotential. The equalization operation of the load circuit 30-1 will be described with reference to the column converter circuit 49. Capacitance balance The gate capacitance of the PMOS transistors 42-44 is set equivalent to the gate capacitances of the PMOS transistors 32 and 34 constituting the mirror circuit to balance the capacitance accompanying the wiring of the load circuit 30-1. .

When reading data, the column conversion circuit 49 receives the low level first column conversion signal from the first column conversion signal line SEL1 when the memory cell of the first column tree is selected, and the second column conversion signal. A high level second column conversion signal is received from the line SEL2. As a result, the first PMOS transistor 45 and the fourth PMOS transistor 48 are turned on, so that the first data line DL1 is on the sense line SA and the second data line DL2 is on the reference sense line ( RSA).

When the memory cell of the second column tree is selected, the column conversion circuit 49 receives the high level first column conversion signal from the first column conversion signal line SEL1 and from the second column conversion signal line SEL2. Receive a low level second column conversion signal. As a result, since the second PMOS transistor 46 and the third PMOS transistor 47 are turned on, the first data line DL1 is connected to the reference sense line SA, and the second data line DL2 is connected to the sense line. SA) respectively.

As such, regardless of whether the selected memory cell holds data "1" or "0", the data line of the selected column tree is always connected to the sense line SA, and the data line of the non-selected column tree. Is connected to the reference sense line RSA, so that the capacity balance of the sense line SA and the reference sense line RSA is kept even.

Thus, regardless of whether the data in the memory cell is "1" or "0", the read data signal is sent to the sense line SA via the respective data lines DL1 and DL2 and the isolation NMOS transistors 51 and 52. Delivered. A reference current source (not shown) is connected to the reference data line RDL, and since the reference current source is set to half of the amount of current flowing through the on-cell, a read data signal of data " 1 " is input to the load circuit 30-1. When the sense line SA is at a low level, the reference sense line RSA is at a high level. When the read data signal "0" of data is input, the sense line SA is at a high level and the reference sense line RSA is at a low level. This potential difference is amplified by the differential amplifier 20 and output as data "1" or "0" through the output buffer circuit 10 to the output signal line nSAOUT.

In the equalization operation of the column conversion circuit 49, the column conversion circuit 49 simultaneously receives a low level equalization signal from the first column conversion signal line SEL1 and the second column conversion signal line SEL2, Turn on the PMOS transistors 45-48. As a result, the potentials of all nodes of the load circuit 30-1 are set to the equipotential.

As described above, according to the present invention, since the column conversion circuit included in the load circuit of the sense circuit also operates the equalization circuit, it is possible to maintain the maximum capacity balance between the sense line and the reference modulation line, and to reduce the increase in the elements required for selection. In this way, it is possible to suppress the increase of the circuit and the increase of the chip area to a minimum. As a result, it is possible to provide a semiconductor memory device capable of a fast read operation that is resistant to noise.

In summary, a semiconductor memory device according to an embodiment of the present invention may read first and second column trees including bit lines and intermediate data lines, and memory cells connected to the first and second column trees, respectively. And a sensing circuit. The sensing circuit electrically connects a column tree connected to a read-selected memory cell among the first and second column trees to a sense line and electrically connects a column tree connected to a non-selected memory cell to a reference sense line to perform a read operation. do. Thus, the balance between the capacitance connected to the sense line and the capacitance connected to the reference sense line is adjusted.

In addition, the sense circuit electrically connects the first column tree to the sense line in response to the first control signal and electrically connects the second column tree to the reference sense line and in response to the second control signal. Is electrically connected to the reference sense line and the second column tree is electrically connected to the sense line and equalizes the nodes within the sense circuit in response to the first and second control signals.

4 is a block diagram illustrating a memory system 100 according to an exemplary embodiment of the inventive concept. Referring to FIG. 4, a memory system 100 according to an embodiment of the present invention includes a memory device 110 and a controller 120.

The controller 120 is connected to the host and the memory device 110. The controller 110 transfers the data read from the memory device 120 to the host, and stores the data transferred from the host in the memory device 110.

Controller 100 will include well known components such as RAM, processing unit, host interface, and memory interface. The RAM will be used as the operating memory of the processing unit. The processing unit will control the overall operation of the controller 120. The host interface will include a protocol for performing data exchange between the host and the controller 120. In an exemplary embodiment, the controller 120 may include one of various interface protocols such as USB, MMC, PCI-E, Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, SCSI, ESDI, and Integrated Drive Electronics (IDE). It will be configured to communicate with the outside (host) through one. The memory interface will interface with the memory device 110. The controller 120 may further include an error correction block. The error correction block will detect and correct an error of data read from the memory device 110.

As illustrated in FIG. 2, the memory device 110 may include a plurality of bit lines connected to the memory cells, main bit lines connected to the bit lines, and intermediate data lines connected to the main bit lines. And first and second column trees. In addition, the sensor circuit shown in FIG. 1 may be further included to read memory cells connected to the first and second column trees.

The controller 120 and the memory device 110 may be integrated into one semiconductor device. In exemplary embodiments, the controller 120 and the memory device 110 may be integrated into one semiconductor device to constitute a memory card. For example, the controller 120 and the memory device 110 may be integrated into one semiconductor device such that a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM / SMC), a memory stick, and a multimedia card ( MMC, RS-MMC, MMCmicro, SD cards (SD, miniSD, microSD), universal flash memory (UFS), and so on.

As another example, the controller 120 and the memory device 110 may be integrated into one semiconductor device to constitute a solid state disk / drive (SSD). When the memory system 100 is used as the semiconductor disk SSD, an operating speed of a host connected to the memory system 100 may be improved.

As another example, the memory system 100 may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or information. It will be applied to devices that can transmit and receive in a wireless environment.

The memory device 110 according to the embodiment of the present invention may be implemented in various forms. For example, the memory device 110 may include a volatile memory device such as SRAM, DRAM, SDRAM, and the like, and a ROM, PROM, EPROM, EEPROM, flash memory device, PRAM, MRAM, RRAM, FRAM, or the like. It will be appreciated that it can be implemented with a nonvolatile memory device.

FIG. 5 is a block diagram illustrating an embodiment of a computing system 200 including the memory system 100 of FIG. 4. Referring to FIG. 5, a computing system 200 according to an embodiment of the present invention may include a central processing unit 210, a random access memory (RAM), a user interface 230, a power source 240, and a memory. System 100.

The memory system 100 is electrically connected to the CPU 210, the RAM 220, the user interface 230, and the power supply 240 through the system bus 250. Data provided through the user interface 230 or processed by the central processing unit 210 is stored in the memory system 100. The memory system 100 includes a controller 120 and a nonvolatile memory device 110.

It will be appreciated that the memory device 110 according to the embodiment of the present invention is not limited to the controller 120 and the memory system 100, which are connected to the system bus 250. For example, it will be appreciated that the memory device 110 (see FIG. 4) according to an embodiment of the inventive concept may be provided as the RAM 220 of the computing system 200.

In the detailed description of the present invention, specific embodiments have been described, but it is obvious that various modifications can be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

1 is a circuit diagram illustrating a sensing circuit according to an exemplary embodiment of the present invention.

2 is a memory block diagram illustrating a configuration of a memory array that acquires a capacity balance of an input terminal of a differential amplifier.

3 is a circuit diagram illustrating a sense amplifier circuit.

4 is a block diagram illustrating a memory system according to an example embodiment.

FIG. 5 is a block diagram illustrating an embodiment of a computing system including the memory system of FIG. 4.

Claims (10)

Memory cells coupled to the first and second column trees; And A sensing circuit for reading the memory cells, The sensing circuit performs a read operation by electrically connecting a column tree connected to a read selected memory cell among the first and second column trees to a sense line and electrically connecting a column tree connected to a non-selected memory cell to a reference sense line. A semiconductor memory device to perform. The method of claim 1, The sensing circuit electrically connects the first and second column trees to the sense line and the reference sense line, thereby adjusting a balance of capacitance connected to the sense line and capacitance connected to the reference sense line. Device. The method of claim 1, And the sensing circuit electrically connects the first and second column trees to the sense line and the reference sense line, respectively, in response to a first control signal. The method of claim 3, wherein And the sensing circuit electrically connects the first and second column trees to the reference sense line and the sense line, respectively, in response to a second control signal. The method of claim 4, wherein And the sensing circuit equalizes nodes within the sensing circuit in response to the first and second control signals. A method of operating a semiconductor memory device comprising memory cells connected to first and second column trees and a sensing circuit for reading the memory cells: Equalize nodes inside the sense circuit in response to first and second control signals; Electrically connecting the first and second column trees to a sense line and a reference sense line of the sense circuit, respectively, in response to the first control signal; And And electrically connecting the first and second column trees to the reference sense line and the sense line, respectively, in response to the second control signal. The method of claim 6, And a column tree connected to a read selected memory cell of the first and second column trees is electrically connected to the sense line. The method of claim 6, Balancing the capacities connected to the sense line and the reference sense line, respectively, by connecting the first and second column trees to the sense line and the reference sense line. Semiconductor memory devices; And A controller for controlling the semiconductor memory device, The semiconductor memory device Memory cells coupled to the first and second column trees; And A sensing circuit for reading the memory cells, The sensing circuit performs a read operation by electrically connecting a column tree connected to a read selected memory cell among the first and second column trees to a sense line and electrically connecting a column tree connected to a non-selected memory cell to a reference sense line. Memory system to perform. The method of claim 9, And the semiconductor memory device and the controller are integrated into one semiconductor device.

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