KR20090056042A - Band gap reference voltage generation circuit - Google Patents

Abstract

A band gap reference voltage generation circuit is provided to supply a stable reference voltage by reducing offset interference from an operational amplifier. An operational amplifier(10) outputs operational amplification signal by receiving a first voltage and a second voltage which are compensated by a offset change. A first voltage generating unit(20) outputs a first voltage by using a first bipolar transistor which is formed by a multi-stage to compensate offset change in response to the operational amplifier signal. A second voltage generating unit(30) outputs a second voltage by using a second bipolar transistor which is formed by a multi-stage to compensate offset change in response to the operational amplifier signal.

Description

Band Gap Reference Voltage Generation Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a band gap reference voltage generator circuit for generating a reference voltage suitable for a low voltage integrated circuit.

A band gap reference voltage generation circuit (hereinafter, referred to as a BGR circuit) is employed in a semiconductor integrated circuit to supply a stable bias.

The BGR circuit mainly provides a reference voltage of an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC), and is stable to temperature or process changes.

Such a BGR circuit typically utilizes the junction voltage characteristic of the bipolar transistor (junction voltage between the emitter bases of Q1 and Q2) and the thermal voltage characteristic (VT = kT / q) to provide a constant level of reference regardless of process change and temperature change. The voltage Vref is output.

Referring to FIG. 1, a conventional BGR circuit includes an operational amplifier OP, PMOS transistors P1 to P3, resistors R1 to R4, and bipolar transistors Q1 and Q2.

The operational amplifier OP continuously adjusts the amount of current supplied through the PMOS transistors P1 to P3 according to the output voltage until the levels of the voltages Va and Vb applied to the two input terminals are the same. That is, the operational amplifier OP generates a reference voltage Vref having a constant level when the voltages Va and Vb applied to the two input terminals are the same.

The PMOS transistors P1 to P3 are all the same size, and are connected between the power supply voltage terminal VDD and the output voltage terminals Va, Vb, and Vref, respectively, and the output of the operational amplifier OP is connected to the gate.

The resistors R1, R2, and R4 are connected between the ground voltage terminal VSS and the output voltage terminals Va, Vb, and Vref, respectively, and the bipolar transistor Q1 is connected between the output voltage terminal Va and the ground voltage terminal VSS. R3) and bipolar transistor Q2 are connected in series between output voltage terminal Vb and ground voltage terminal VSS.

Hereinafter, the voltage level of the reference voltage Vref will be described.

Here, since the gates of the PMOS transistors P1 to P3 are commonly connected to the output voltage of the operational amplifier OP, the currents I1, I2, and I3 flowing through them are almost the same. If the voltages Va and Vb applied to the two input terminals of the operational amplifier OP are the same and the resistance values of the resistors R1 and R2 are the same, the currents I1b and I2b flowing through the resistors R1 and R2 are the same.

For example, if the voltages applied to the bipolar transistors Q1 and Q2 are Vf1 and Vf2, respectively, the voltage dVf applied to the resistor R3 is expressed by Equation 1 below.

Where VT is the thermal voltage and kT / q is the voltage proportional to the absolute temperature. q is the charge amount and k is the Boltzmann constant.

Subsequently, the current I2 flowing through the PMOS transistor P2 is expressed as in Equation (2).

Therefore, the reference voltage Vref is defined as shown in equation (3).

As such, the BGR circuit of FIG. 1 has an effect of lowering the reference voltage Vref by adjusting the resistance values R4 and R2. The BGR circuit of FIG. 1 has a problem that current consumption increases because current must continue to flow in the paths of currents I1b and I2b.

Another conventional BGR circuit that improves this is shown in FIG. 2.

2, another conventional BGR circuit is configured similarly to the BGR circuit of FIG. However, the currents I1b and I2b flowing through the resistors R1 and R2 in the configuration of the BGR circuit of FIG. 1 are made to flow in one pass by making common voltage levels of the voltage terminals Va and Vb.

In detail, resistors R1 and R2 respectively connected between voltage terminals Va and Vb and ground voltage terminals VSS in FIG. 1 are connected in series between voltage terminals Va and Vb in FIG. 2 and common to the resistors R1 and R2. A resistor R5 is further connected between the voltage terminal Vc of the node and the ground voltage terminal VSS.

Here, since the resistance values of the resistors R1 and R2 are substantially the same, the voltages Va, Vb, and Vc have the same voltage level because the voltage Vc of the common node becomes the common voltage level of the operational amplifier OP. Therefore, the current Ib flowing in the resistor R5 is equal to the current I1b current value in FIG. 1. That is, the current Ib flowing in the resistor R5 flows through the PMOS transistors P1 and P2 by 1/2 each.

Therefore, the current I2 flowing through the PMOS transistor P2 is expressed as shown in equation (4).

 Therefore, the reference voltage Vref is defined as in equation (5).

Since the coefficient of the conventional BGR circuit shown in FIG. 1 is changed from R2 / R3 (Equation 3) to that of the conventional improved BGR circuit shown in FIG. 2, it is changed to 2 * R5 / R3 (Equation 5). The value of (R5) can be reduced or the area ratio of the bipolar transistor can be reduced. It also has the effect of reducing the current path.

Meanwhile, in the conventional BGR circuit of FIG. 2, the operational amplifier OP may output a constant reference voltage Vref when the voltages Va and Vb applied to the input terminal are at the same voltage level.

However, in practice, the operational amplifier OP may have an offset due to various changes such as a process or a voltage. 3 is another conventional BGR circuit considering the offset voltage Vos of the operational amplifier OP.

Referring to FIG. 3, a conventional BGR circuit considering an offset of an operational amplifier is configured similarly to FIG. 2. However, the offset voltage Vos is reflected and input to any one of the voltages (here, voltage Va) input to the operational amplifier OP in the BGR circuit configuration of FIG. 2.

Specifically, the operational amplifier OP generates a constant reference voltage Vref when the voltage obtained by subtracting the offset voltage Vos from the voltage Va is at the same voltage level as the voltage Vb. That is, the following equation (6) is established.

Therefore, the voltage dVf applied to the resistor R3 is expressed by Equation 7 below.

Subsequently, the current I2 flowing through the PMOS transistor P2 is expressed as in Equation (8).

 The reference voltage Vref is defined as shown in equation (9).

That is, an error of (-) R4 / R3 * Vos occurs due to the offset voltage Vos. As a result, the reference voltage Vref becomes unstable.

The present invention provides a bandgap reference voltage generation circuit that reduces the influence of offset by an operational amplifier and outputs a stable reference voltage.

The bandgap reference voltage generation circuit of the present invention includes an operational amplifier for outputting an operational amplified signal by inputting at least one of a first voltage and a second voltage to which an offset change value is applied; A first voltage generator configured to output the first voltage using first bipolar transistors configured in multiple stages to correct the offset change value in response to the operational amplification signal; A second voltage generator configured to output the second voltage using second bipolar transistors configured in multiple stages to correct the offset change value in response to the operational amplification signal; A common current path unit connected to an output node of the first voltage and an output node of the second voltage to generate a current path according to a common voltage level of the first voltage and the second voltage; And a reference voltage generator outputting a reference voltage in response to the operational amplification signal.

The first voltage generator includes: a first PMOS transistor connected between a power supply voltage terminal and an output node of the first voltage and forming a source-drain path controlled by the operational amplification signal; And the first bipolar transistors connected in cascode form between an output node of the first voltage and a ground voltage terminal.

The second voltage generator includes: a second PMOS transistor connected between the power supply voltage terminal and an output node of the second voltage and controlled by the operational amplification signal to form a source-drain path; A first resistor having one end connected to an output node of the second voltage; And the second bipolar transistors connected in cascode form between the other end of the first resistor and the ground voltage terminal.

Preferably, the first bipolar transistors have the same junction voltage characteristics, and the second bipolar transistors each have the same junction voltage characteristics. The first and second bipolar transistors are preferably configured in the same number.

The common current path unit includes: a second resistor having one side connected to an output node of the first voltage; A third resistor coupled between the other side of the second resistor and the output node of the second voltage; And a fourth resistor coupled between the common node of the second and third resistors and the ground voltage terminal.

Preferably, the second resistor and the third resistor have substantially the same resistance value.

The reference voltage generator includes: a third PMOS transistor connected between the power supply voltage terminal and an output node of the reference voltage and controlled by the operational amplification signal applied to a gate to form a source-drain path; And a fifth resistor connected between the ground voltage terminal and the reference voltage output node.

Preferably, the first and third PMOS transistors have substantially the same size.

According to the present invention, a band gap reference voltage generator circuit in which bipolar transistors are connected in a cascode form reduces the influence of offset by an operational amplifier, thereby providing a stable reference voltage.

The present invention relates to a bandgap reference voltage generation circuit for generating a reference voltage suitable for a low voltage integrated circuit, and a preferred embodiment for reducing the influence of the offset of the operational amplifier constituting the bandgap reference voltage generation circuit. It is presented as 4.

Referring to FIG. 4, in the BGR circuit considering the offset of the operational amplifier of the present invention, an operation of outputting an operational amplified signal by inputting voltage Va-Vos and voltage Vb in which the offset voltage Vos of the operational amplifier is reflected in voltage Va The amplifier 10, the voltage generators 20 and 30 for outputting the voltage Va and the voltage Vb in response to the operational amplification signal, and the common current path unit 40 for generating a current path according to the common voltage level of the voltage Va and the voltage Vb. And a reference voltage generator 50 for outputting a reference voltage Vref in response to the operational amplification signal.

The operational amplifier 10 provides an operational amplification signal until the levels of voltages Va-Vos and Vb applied to the two input terminals are equal to each other, thereby providing the amount of current supplied to the voltage generators 20 and 30 and the reference voltage generator 50. Adjust That is, when the levels of the two voltages Va-Vos and Vb applied to the input terminal of the operational amplifier 10 are the same, a reference voltage Vref of a constant level is generated.

The voltage generator 20 is connected between the power supply voltage terminal VDD and the output node ND1 of the voltage Va and controlled by an operational amplification signal applied to a gate to form a source-drain path and an output of the voltage Va. Bipolar transistors Q1 and Q2 connected in a cascode form between the node ND1 and the ground voltage terminal VSS are included. Here, the junction voltage characteristics of each of the bipolar transistors Q1 and Q2 are preferably the same.

The voltage generator 30 is connected between the power supply voltage terminal VDD and the output node ND2 of the voltage Vb to be controlled by an operational amplification signal applied to the gate to form a source-drain path and an output of the voltage Vb. A resistor R3 having one end connected to the node ND2 and bipolar transistors Q3 and Q4 connected in cascode form between the other end of the resistor R3 and the ground voltage terminal VSS. Here, the junction voltage characteristics of each of the bipolar transistors Q3 and Q4 are preferably the same.

Each of the voltage generators 20 and 30 connects the same number of bipolar transistors in a cascode form.

The common current path part 40 includes a resistor R1 and a resistor R1 and R2 connected between a resistor R1 having one end connected to the output node ND1 of the voltage Va and the other end of the resistor R1 and the output node ND2 of the voltage Vb. It includes a resistor (R5) connected between the common node and the ground voltage terminal VSS.

The reference voltage generator 50 is connected between the power supply voltage terminal VDD and the output node ND3 of the reference voltage Vref and controlled by an operational amplification signal applied to a gate to form a source-drain path and a reference voltage. Resistor R4 connected between the output node ND3 of Vref and the ground voltage terminal VSS.

The present invention shown in FIG. 4 connects a plurality of identical bipolar transistors in cascode form instead of the bipolar transistors Q1 and Q2 of the conventional BGR circuit considering the offset of the operational amplifier shown in FIG. The influence of the offset voltage Vos on the reference voltage Vref can be reduced.

Here, since the gates of the PMOS transistors P1 to P3 are commonly connected to the operational amplification signal, the currents I1, I2, and I3 flowing through them are almost the same. If the voltages Va-Vos and Vb applied to the two input terminals of the operational amplifier 10 are the same and the resistance values of the resistors R1 and R2 are the same, the current Ib flowing through the resistor R5 is the PMOS transistors P1 and P2. Each half flow through.

For example, when the voltage applied to the bipolar transistors Q1 and Q2, that is, the voltage Va is 2Vf1 and the voltage applied to the bipolar transistors Q3 and Q4 is 2Vf2, the voltage dVf applied to the resistor R3 is expressed by Equation 10 below. It is expressed as

Subsequently, the current I2 flowing in the PMOS transistor P2 is expressed as in Equation (11).

 The reference voltage Vref is defined as in Equation 12.

The reference voltage Vref of the conventional BGR circuit considering the offset of the operational amplifier shown in FIG. 3 is affected by the offset corresponding to (ln (N) * VT−Vos) (Equation 9). On the other hand, the reference voltage Vref of the BRG circuit of the present invention shown in FIG. 4 is affected by an offset corresponding to (2ln (N) * VT−Vos) (Equation 12), which is smaller than that.

As a result, the BGR circuit of the present invention can output a stable reference voltage Vref by connecting the bipolar transistors in the form of a cascode to reduce the offset influence by the operational amplifier.

1 is a bandgap reference voltage generation circuit diagram according to the prior art;

2 is another band gap reference voltage generation circuit diagram according to the prior art.

3 is a bandgap reference voltage generation circuit diagram considering an offset of an operational amplifier according to the prior art.

4 is a bandgap reference voltage generation circuit diagram in accordance with the present invention.

Claims (10)

An operational amplifier configured to output an operational amplifier signal by inputting a first voltage and a second voltage to which at least one of the offset change values is applied; A first voltage generator configured to output the first voltage using first bipolar transistors configured in multiple stages to correct the offset change value in response to the operational amplification signal; A second voltage generator configured to output the second voltage using second bipolar transistors configured in multiple stages to correct the offset change value in response to the operational amplification signal; A common current path unit connected to an output node of the first voltage and an output node of the second voltage to generate a current path according to a common voltage level of the first voltage and the second voltage; And A reference voltage generator for outputting a reference voltage in response to the operational amplification signal; Band gap reference voltage generation circuit comprising a. The method of claim 1, The first voltage generator, A first PMOS transistor connected between a power supply voltage stage and an output node of the first voltage and forming a source-drain path controlled by the operational amplified signal; And The first bipolar transistors connected in cascode form between an output node of the first voltage and a ground voltage terminal; Band gap reference voltage generation circuit comprising a. The method of claim 2, The second voltage generator, A second PMOS transistor coupled between the power supply voltage stage and an output node of the second voltage and controlled by the operational amplification signal to form a source-drain path; A first resistor having one end connected to an output node of the second voltage; And The second bipolar transistors connected in cascode form between the other end of the first resistor and the ground voltage terminal; Band gap reference voltage generation circuit comprising a. The method of claim 3, wherein And the first bipolar transistors each have the same junction voltage characteristic. The method of claim 3, wherein And the second bipolar transistors each have the same section voltage characteristic. The method of claim 3, wherein And a band gap reference voltage generation circuit comprising the same number of first and second bipolar transistors. The method of claim 3, wherein The common current path unit, A second resistor having one side connected to the output node of the first voltage; A third resistor coupled between the other side of the second resistor and the output node of the second voltage; And A fourth resistor coupled between the common node of the second and third resistors and the ground voltage terminal; Band gap reference voltage generation circuit comprising a. The method of claim 7, wherein And the second resistor and the third resistor have substantially the same resistance value. The method of claim 7, wherein The reference voltage generator, A third PMOS transistor connected between the power supply voltage terminal and an output node of the reference voltage and controlled by the operational amplification signal applied to a gate to form a source-drain path; And A fifth resistor connected between the ground voltage terminal and the reference voltage output node; Band gap reference voltage generation circuit comprising a. The method of claim 9, And the first and third PMOS transistors have substantially the same magnitude.

Images