KR20090053872A - Digital to analog converter having binary decoder type - Google Patents

Abstract

The present invention relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter having a binary decoder structure.

The present invention provides an input buffer unit 100 for receiving N bits of digital data and outputting N input signals, a binary decoder unit for receiving ^N input signals and outputting 2 ^N -1 output signals; , 2 ^N -1 receives the output signal 2 (2 ^N -1) of the differential output signals and outputting a switch driving, being applied to the reference current and the bias voltage from the bias (bias) receives the output signals of switch driver A current source cell unit for outputting the non-inverted output current and the inverted output current, and a load resistor unit for receiving the non-inverted output current and the inverted output current to convert the output voltage.

The present invention as described above has the effect of reducing the glitches due to current source mismatch, improve the linearity of the output signal to improve the static performance and dynamic performance of the digital-to-analog converter.

Digital-to-Analog Converter, DAC, Binary Decoder

Description

Digital to analog converter having a binary decoder structure

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter having a binary decoder structure that reduces glitches due to current source mismatch and improves linearity of the output signal, thereby improving the static and dynamic performance of the digital-to-analog converter. It relates to an analog converter.

Recently, mobile communication, digital broadcasting, home network, image sensor, and the like require low power consumption, miniaturization, and fast conversion speed, and are being implemented as a single chip using system on chip (SoC) technology. For the implementation of a system on a chip, the technology of the analog-to-digital interface is important, among which a high-speed, high-resolution, low-power digital-to-analog converter has a wide range of applications.

In particular, digital-to-analog converters used in wireless communication applications have a high resolution of more than 10 bits and a relatively high operating speed of more than 100 MHz, and low power consumption is essential for system-on-chip implementation. Therefore, a current-driven digital-to-analog converter that meets these high-speed, high-resolution conditions is used.

Current-driven digital-to-analog converters are generally divided into binary weight structures, thermometer decoder structures, and mixed structures using a mixture of binary weight structures and thermometer decoder structures, depending on the digital input signal processing method.

In the case of N bits, the binary weight structure is composed of only N current source cells and switches, respectively, so that the structure is simple and the total power consumption is small. However, due to current sources having different sizes, mismatch occurs, resulting in a large amount of glitch energy and a decrease in linearity of an output signal.

In addition, as shown in FIG. 1, the thermometer decoder structure converts an input signal into a thermometer code and converts data by a current source cell of the same size in a predetermined order. Thermometer Decoder Structure The digital-to-analog converter has the same current source cell size as 1 LSB, so the matching characteristics of the current source are superior to the binary-weighted structure, resulting in better linearity, better static and dynamic performance, but higher resolution. As the number of current sources and decoder circuits increases, the chip area increases, and power consumption also increases in proportion.

Here, the characteristics of the digital-to-analog converter are generally classified into static and dynamic characteristics. Static characteristics are features that appear in a digital-to-analog converter regardless of the type of input signal, and dynamic characteristics are features that change dynamically according to the type of input signal. At this time, the static characteristics include resolution (Resolution), INL (Integral Non-Linearity) and DNL (Differential Non-Linearity), and the dynamic characteristics include SNDR (Signal to Noise and Distortion Ratio) and Supurious Free Dynamic Range (SFDR). have.

The mixed structure is a general current-driven digital-to-analog converter, in which only the advantages of the binary weight structure and the thermometer decoder structure are mixed, and the upper bits are mixed into the thermometer decoder structure and the lower bits into the binary weight structure.

Conventionally, the technology for the digital-to-analog converter has been published and published in a number of applications other than Korean Patent Publication No. 2006-0124326 'D / A converter module'.

The D / A converter module may include: a thermometer decoder configured to convert a digital code of an upper m bit input into a thermometer code and output the thermometer code; A latch unit for synchronizing and outputting the thermometer code and the digital code of the lower n bits to be input according to an input clock signal; A thermometer code current cell matrix driven by the thermometer code output from the latch unit and converting the thermometer code into an analog current and outputting the analog current; First and second binary weighted current cells that are driven by the lower n-bit digital codes output from the latch unit and convert the lower n-bit digital codes into analog currents and output the analog codes; And the lower n bits of the digital code output from the latch unit according to the mode selection signal input from the outside, and the lower n bits of the digital code output from the latch unit according to the mode selection signal input from the first binary external source. And a switching unit configured to selectively output the first binary weighted current cell or the second binary weighted current cell.

However, the conventional technology has a problem of increasing chip area and power consumption according to the increase in the number of decoder circuits, and the limitation of the static and dynamic characteristics due to the asynchronous input signal due to the mixing of the thermometer decoder and the binary weight structure. There is this.

An object of the present invention is to solve the above problems, to provide a digital-to-analog converter having a binary decoder structure to reduce the glitches caused by the current source mismatch of the binary-weighted structure digital-to-analog converter and to improve the linearity of the output signal. Is in.

Another object of the present invention is to provide a digital-to-analog converter having a binary decoder structure that can reduce power consumption and reduce chip area.

The present invention provides an input buffer unit 100 for receiving N bits of digital data and outputting N input signals, a binary decoder unit for receiving ^N input signals and outputting 2 ^N -1 output signals; , 2 ^N -1 receives the output signal 2 (2 ^N -1) of the differential output signals and outputting a switch driving, being applied to the reference current and the bias voltage from the bias (bias) receives the output signals of switch driver A current source cell unit for outputting the non-inverted output current and the inverted output current, and a load resistor unit for receiving the non-inverted output current and the inverted output current to convert the output voltage.

The present invention as described above has the effect of reducing the glitches due to current source mismatch, improve the linearity of the output signal to improve the static performance and dynamic performance of the digital-to-analog converter.

In addition, the present invention has the effect of reducing the power consumption and chip area than the thermometer decoder digital-to-analog converter.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

A digital-to-analog converter having a binary decoder structure according to an embodiment of the present invention will be described with reference to FIGS. 2 to 6 as follows.

As shown in FIG. 2, the digital-to-analog converter having a binary decoder structure according to an embodiment of the present invention includes an input buffer unit 100, a binary decoder unit 200, a switch driver 300, and a current source. The cell unit 400 and the load resistor unit 500 are included.

First, the input buffer unit 100 receives N bits of digital data and outputs N input signals.

In addition, as illustrated in FIG. 3, the binary decoder 200 receives N input signals, which are outputs of the input buffer unit 100, into the N parallel buffers 220 through the input terminal 210 and receives 2 ^N. One output signal is output to the output terminal 230. Here, the delay times for the 2 ^N −1 output signals coming through the parallel buffer 220 are the same.

The binary decoder 200 according to the present embodiment is a 4-bit binary decoder, and the input four bits are output as 15 output signals through four parallel buffers to drive the switching driver 300. Here, the binary decoder unit 200 according to the present embodiment drives the current source cell unit 400 having the same size for each output signal of the binary decoder unit 200 when the switch driving unit 300 is driven, and thus has a binary weight structure. -It has the effect of improving the mismatch of current source which is a disadvantage of analog converter.

In addition, the switch driver 300 receives 2 ^N −1 output signals from the binary decoder unit 200, synchronizes the output signals received from the binary decoder unit 200 according to a clock signal, and 2 (2 ^N −). Deglitch that suppresses glitches by adjusting the cross-point of the latch module 310 that outputs 1) differential output signals and the differential output signal synchronized through the latch module 310. The switch driving module 330 receives a control signal of the intersection point of the differential output signal through the module 320 and the diglych module 320, and reduces the voltage swing of the differential output signal having the intersection point adjusted. Include.

In addition, the current source cell unit 400 receives a reference current and a bias voltage from a bias B, and receives 2 (2 ^N −1) differential output signals, which are outputs of the switch driver 300, to receive non-inverted output. Output current and inverted output current. In this case, the bias B according to the present exemplary embodiment may use a bias resistor therein, or adjust the current magnitude through an external variable resistor. Here, the current source cell unit 400 is composed of a plurality of cells, it is composed of a plurality of current sources and switches.

In addition, the load resistor unit 500 receives the non-inverting output current and the inverting output current of the current source cell unit 400 to convert the output voltage.

The digital-to-analog converter having the binary decoder structure according to the present invention has an effect of significantly reducing the number of gates compared to the digital-to-analog converter of the thermometer decoder structure, thereby reducing power consumption.

In addition, since a current source having the same size is used, it is possible to improve the mismatch of the current source, which is a disadvantage of the binary weight structure, while eliminating a complicated logic circuit such as a thermometer decoder, thereby reducing the chip area due to the simple structure.

In addition, by reducing the voltage swing of the differential output signal at which the crossing point is adjusted, there is an effect of preventing the degradation of the dynamic performance.

On the other hand, as shown in Figure 4, the digital-to-analog converter having a binary decoder structure according to an embodiment of the present invention conditions with a digital-to-analog converter of the existing thermometer decoder structure and a resolution of 12 bits and a conversion rate of 400MHz The result of comparing the power consumption with the same design is as follows.

As a result of comparing the power consumption under the same conditions, when the power consumption of the digital-analog converter of the conventional thermometer decoder structure is 100%, the digital-analog converter having the binary decoder structure according to the present embodiment consumes more than 50% of the power consumption. Decrease.

In addition, the result of comparing the signal to noise and distortion ratio (SNDR) and the effective bit change with respect to the digital-to-analog converter having the binary decoder structure and the digital-to-analog converter of the existing thermometer decoder structure according to the present embodiment is shown in FIG. 5 and 6 as shown.

That is, the digital-to-analog converter having the binary decoder structure according to the present embodiment reduces the power consumption even when the input frequency is increased, thereby reducing the voltage swing of the differential output signal whose intersection is adjusted, thereby preventing the degradation of dynamic performance. There is.

As described above and described with reference to a preferred embodiment for anticipating the technical idea of the present invention, the present invention is not limited to the configuration and operation as shown and described as described above, it is a deviation from the scope of the technical idea It will be understood by those skilled in the art that many modifications and variations can be made to the invention without departing from the scope of the invention. Accordingly, all such suitable changes and modifications and equivalents should be considered to be within the scope of the present invention.

1 is a structural diagram of a thermometer decoder according to the prior art.

2 is a block diagram of a digital-to-analog converter having a binary decoder structure in accordance with an embodiment of the present invention.

3 is a binary decoder structure diagram according to an embodiment of the present invention.

4 is a graph illustrating a result of comparing power consumption with respect to a digital-to-analog converter having a binary decoder structure and a digital-to-analog converter having a conventional thermometer decoder structure according to an embodiment of the present invention.

5 is a graph illustrating a result of comparing a noise signal ratio SNDR with respect to a digital-to-analog converter having a binary decoder structure and a digital-to-analog converter having a conventional thermometer decoder structure according to the present embodiment.

FIG. 6 is a graph showing a result of comparing effective bit changes with respect to a digital-to-analog converter having a binary decoder structure and a digital-to-analog converter having a conventional thermometer decoder structure according to the present embodiment. FIG.

<Description of Drawing>

100: input buffer unit 200: binary decoder unit

210: input terminal 220: parallel buffer

230: output terminal 300: switch drive unit

310: latch module 320: deglitch module

330: switch drive module 400: current source cell portion

500: load resistance portion B: bias

Claims (4)

In a digital-to-analog converter, An input buffer unit 100 for receiving N bits of digital data and outputting N input signals; A binary decoder unit 200 which receives N input signals that are outputs of the input buffer unit and outputs 2 ^N -1 output signals; A switch driver 300 receiving 2 ^N -1 output signals from the binary decoder and outputting 2 (2 ^N -1) differential output signals; A current source cell unit 400 receiving a reference current and a bias voltage from a bias B, receiving an output signal of the switch driver, and outputting a non-inverted output current and an inverted output current; And And a load resistor unit (500) configured to receive the non-inverting output current and the inverted output current of the current source cell unit and convert the non-inverting output current into an output voltage. The method of claim 1, The binary decoder unit 200, Digital-to-analog converter having a binary decoder structure characterized in that the current source is supplied from the current source cell unit 400 through the switch driver (300). The method of claim 1, The binary decoder unit 200, An input terminal 210 for receiving N input signals from the input buffer unit 100; A parallel buffer 220 which receives the N input signals through the input terminal and outputs 2 ^N −1 output signals having the same delay time; And And an output terminal (230) for outputting the 2 ^N -1 output signals. The method of claim 1, The switch driver 300, A latch for receiving 2 ^N -1 output signals from the binary decoder unit 200, synchronizing the output signals received from the binary decoder unit according to a clock signal, and outputting 2 (2 ^N- 1) differential output signals. Module 310; Deglitch module 320 for adjusting the intersection of the differential output signal synchronized through the latch module; And And a switch driving module (330) for reducing the voltage swing of the differential output signal whose intersection point is adjusted through the diglych module.

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