JPH05267730A - Superconductive analog-digital converter - Google Patents

Abstract

PURPOSE:To devise a parallel type (flash type) ADC using comparators comprising QFP used for a quantizer and a sampler for composing a decoder converting gray code into natural binary numbers by QFP. CONSTITUTION:A comparator circuit is composed of a quantizer 300 using QFP and a sampler 400. Next, analog signals transmitted to an input line are converted into almost rectangular wave signals meeting the requirements excitation characteristics of QFP. Next, the DC compound of the quantizer output is cancelled by the sampler 400 to be sampled at the first transition of the sampler transient excitation for further conversion into digital signals. Finally, the title analog.digital converter can be composed if only proper input circuit and bias circuit are arranged and several comparators are connected in parallel with one another.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting switching circuit which operates at a very low temperature, and in particular to an analog using a quantum flux parametron which is a parametron type switching circuit using Josephson elements. Regarding a digital converter.

[0002]

2. Description of the Related Art Quantum magnetic flux parametron (Quantum flux parametron) which is a parametron type switching circuit using a superconducting element showing the Josephson effect (hereinafter referred to as Josephson element)
um Flux Parametron, hereinafter abbreviated as QFP) is well known in the art, and is a summary of the 1994 RIKEN symposium proceedings pages 1-3 and 48-78. -13 pages, Showa 6
It is disclosed in the first year RIKEN symposium proceedings, pages 53-58. The QFP is a switching circuit that uses quantized DC magnetic flux as a signal medium, and is excellent as a computer element because it operates at high speed with extremely small power consumption. In addition, since a weak signal is amplified with a high gain, it has an excellent property as an analog circuit such as a magnetic sensor.

Analog using a Josephson element. A method for realizing a digital converter (hereinafter abbreviated as ADC) is known. For example, CA Hamilton, et al., "Supercond
ucting A / D Converter Using Latching Comparators "I
EEE Trans. Magn. Vol. MAG-21, No.2, pp197-199, Mar
1985. discloses an ADC composed of a quantum interference circuit using Josephson elements. It has been shown that this ADC operates at a speed ten times or more higher than that made of a semiconductor. A circuit using a conventional Josephson junction causes a so-called latching operation. The state of the junction has two stable states, a superconducting state and a voltage state, for a small current flowing through the junction. The Josephson device in the superconducting state can be easily transited to the voltage state by applying a control current. However, the transition of the Josephson element in the voltage state to the superconducting state cannot be executed only by removing the control current. The device is said to be latched in a voltage state. Therefore, in the conventional Josephson element, in order to transition the element in the voltage state to the superconducting state, it is necessary to perform an operation (reset) of interrupting the power supply applied to the element once for each latch operation. ..

AD using rf-SQUID and QFP consisting of a superconducting loop including a superconducting inductor and a Josephson element
Methods for realizing C are known. For example, N.Shimizu, e
t al., "A New A / D Converter with Quantum Flux Para
metron "IEEE Trans. Magn.Vol. MAG-25, No.2, pp865-
868, 1989, using rf-SQUID as a quantizer, QF
An ADC constructed using P as a sampler and an amplifier is disclosed. In addition, the ADC is Japanese Patent Application No. Sho 62
-Also disclosed in 295780. A QFP that does not perform a latch operation can operate at a high frequency.

[0005]

In order to operate the ADC at a high speed, the high frequency AC power supply is used, but the use of the latch type Josephson element imposes the following restrictions on the operation of the ADC. (1) If the reset operation is performed at a high speed, a malfunction called punch-through occurs with a probability other than zero, so that the operation speed of the ADC is limited. (2) Make sure that the input data does not change during sampling.
Very narrow high frequency pulses are required.

Since the QFP does not use the voltage state of the Josephson device, punchthrough does not become a problem. The problem (2) can be avoided because it is an element that samples, amplifies, and outputs the input signal at the rise of the excitation transient characteristic. However, since rf-SQUID is used as a quantizer, there are the following operation restrictions. (1) The rf-SQUID outputs a sawtooth waveform with respect to a linearly changing input, and when the rf-SQUID output in the low part is sampled, noise is likely to cause the sampler to malfunction. (2) Since the maximum operating speed of the QFP increases as the absolute value of the input increases, the low output of the quantizer limits the speeding up of the sampling frequency.

In the prior art, an ADC using QFP as a quantizer has not been discussed yet.

An object of the present invention is to realize an ADC that operates more accurately and at a higher frequency by using QFP.

[0009]

To this end, according to the present invention, a comparator circuit constructed by using a QFP for a quantizer and a sampler and a QFP for converting a gray code to a natural binary number are used. We propose an ADC that uses a decoder.

[0010]

When the QFP is used as the quantizer, an output close to an ideal rectangular wave can be obtained. By injecting this output into a sampler composed of QFP, sampling and amplifying it, an ADC operating at extremely high frequency can be obtained. Further, if a decoder for converting a gray code to a natural binary number is constructed by QFP, code conversion can be performed at the same frequency as sampling by the pipelined method.

[0011]

EXAMPLES The present invention will be described below with reference to examples. FIG. 2 is an example of the QFP used in the present invention. QFP is 2
Number of Josephson elements 201, 202 and loop. As an inductor, superconducting loops 210 are composed of superconducting inductors 203a and 204a. This superconducting loop 21
A superconducting load inductor 205 is connected to 0.
Inductors 203b and 204b are magnetically coupled to the superconducting inductors 203a and 204a as excitation inductors. The magnetic flux supplied from the excitation power source 206 and generated by the excitation current flowing through the excitation wiring 207 is linked to the superconducting loop via the superconducting inductors 203a and 204a and the inductors 203b and 204b to excite the QFP. QF
The behavior of P is pp. 1-3 and 48-78 of the 1994 RIKEN symposium proceedings, 1960 of the RIETI symposium proceedings page 1-13, and 1986 RIETI symposium proceedings 53. -Page 58. The input signal of QFP is injected into the superconducting loop 210 and the load inductor 205 via the input line 211,
The input signal is sampled and amplified at the rising edge of the excitation transient corresponding to the direction in which the signal current flows.

The quantizer 300 according to claim 1 of the present invention.
Is a single QFP 30 as shown in the embodiment of FIG.
0 and bias line 301 and control line 302 connected to it
And the QFP loop. The input inductors 203c and 204c magnetically coupled to the inductor and the input line 303 connected thereto are used. The output characteristic of this quantizer is the same as the excitation characteristic of the QFP. However, the input line 303 and the bias line 301 of the quantizer
The magnetic flux supplied to the QFP corresponds to the excitation magnetic flux supplied by the QFP excitation line, and the control line 302 of the quantizer corresponds to the input line of the QFP. FIG. 4 shows the excitation characteristics of QFP. This figure is also the output characteristic of the quantizer. As can be seen from Fig. 4, analog with the average output of the quantizer as the origin. The duty cycle of digital conversion can be changed by the control current. Therefore, the control current may be adjusted so that the duty-cycle becomes exactly half of the quantizer cycle so as to satisfy the condition of the equation (1).

[0013]

[Equation 1]

Here, Φ ₀ is a magnetic flux quantum, L _S is a load inductance value, and I _in is an input current value.

To use the quantizer, the analog signal to be converted is supplied from the input line of the quantizer,
The magnetic flux supplied from the bias line of the quantizer may be used to move the boundary between "0" and "1" of the output digital signal.

FIG. 5 shows another structure of the quantizer of the present invention. The structure shown in FIG. 5 is a form in which an electric current is directly injected to apply an input signal, not through magnetic coupling as in FIG. For that purpose, the input line 303 is a loop of the quantizer. Inductor 203a
And the Josephson element 201, and the input return line is the Quantizer loop. It was directly connected between the inductor 204a and the Josephson element 202. Therefore, depending on the input current, the superconducting inductors 203 a, 20
All the magnetic flux generated in 4a is a superconducting rule of a quantizer.
Interlink The control line 302 of the quantizer is connected to a load via an inductor 314, a superconducting transformer 315 and a superconducting inductor 316. The circuit of FIG. 5 has no leakage magnetic flux as compared with the circuit of FIG. 3, and may be considered to operate almost the same.

FIG. 1 shows a third embodiment of the present invention.
The comparator used in the ADC is composed of the quantizer shown in FIG. 3 or 5 and the sampler using QFP.
Hereinafter, only the quantizer of FIG. 3 is shown for simplification, but the quantizer of FIG. 5 is also applicable. In FIG. 1, the Quantizer-300 outputs the output current to the superconducting inductor 311,
It is supplied to the input of the sampler 400 via the superconducting transformer 312 and the superconducting inductor 313. However, the output current of the quantizer 300 only flows in the same direction as the control current. To use it as a digital signal, it is necessary to remove the DC part of this output current. Therefore, the input current is input to the input line 314 of the sampler so as to cancel the DC portion of the output current of the quantizer. As a result, when a linearly varying analog input signal is applied to the quantizer, the effective input of the sampler becomes a square wave signal of approximately positive and negative symmetry. By applying a high frequency to the excitation line of the sampler 400, the effective input can be sampled and amplified at high speed.

FIG. 6 shows the result of circuit simulation by a computer of the operation of the quantizer circuit according to the present invention. In this example, the input current is increased from zero at a constant rate, and the output waveform is repeated in units of magnetic flux quantum with respect to the magnetic flux generated by the current and interlinking with the quantizer. FIG. 7 shows the result of circuit simulation of the effective input of the sampler, which is obtained by subtracting the average value from the waveform of FIG. FIG. 8 shows the result of circuit simulation of the output of the sampler. The sampler excites both polarities with a sine wave of 50 GHz, samples and amplifies an input signal, and performs a predetermined operation.

FIG. 9 shows another example of the comparator used in the ADC of the present invention. In the circuit of FIG. 9, the quantizer-30
0 is a sampler 400 via a superconducting inductor 318.
To form a comparator.

FIG. 10 shows a constitution in which the sampling characteristic of the sampler according to claim 6 of the present invention is improved. In the circuit of FIG. 10, the superconducting inductor 203a of the sampler 600,
A Josephson device 216 is connected in parallel with 204a,
It is the example which constituted the magnetic flux regulator of excitation magnetic flux. The operation principle of this magnetic flux regulator is Japanese Patent Application No. 62-22620.
2 is disclosed. With this structure, Josephson device 2
16 critical currents and superconducting inductors 203a, 204a
When the product of the inductance value of is increased, a hysteresis phenomenon appears in the characteristics of the magnetic flux regulator. By utilizing this hysteresis phenomenon, the sampler can be transited from the non-excited state to the excited state within an extremely short time, so that the sampling time can be made extremely short.

Using the comparator circuit according to the present invention, A
To configure DC, DAPetersen et al., "A High-Spee
d Analog-to-Digital Converter Using Josephson Self
-Gating-AND Comparators, "IEEE Trans. Magn., Vol.M
AG-21, No.2, pp.200-203, Mar 1985, A method of shunting the input current in half using a ladder-type resistor network, CA Hamilton et al., "Superconducting A / D Co
nverter Using Latching Comparators, "IEEE Trans. M
agn., Vol. MAG-21, No.2, pp.197-199, Mar 1985, JWSpargo et al., "A Pipelined Gray Code-to- Na
tural Binary Decoder for Use in a Josephson A / D Co
nverter, "IEEE Trans. Magn., Vol. MAG-19, No.3, pp.
The analog signal disclosed in 1255-1258, May 1983 is first converted into a gray code, and then further processed by a decoder circuit.
There is a method to convert to a base number. Whichever method you use,
An ADC can be constructed using the comparator circuit of the present invention.

FIG. 11 shows an example in which an ADC is constructed by using a ladder type circuit. The ladder circuit is a circuit in which a series resistor 501 and a parallel resistor 502 are alternately connected in series and parallel, and has a structure in which the final stage is terminated by a resistor 503. The resistance value of the parallel resistance 502 is twice the resistance value of the series resistance 501 and the termination resistance 503. In this circuit configuration, the current flowing through each parallel resistor 502 is sequentially divided into 1/2. The comparator circuit 500 of the present invention is connected to the end of each parallel resistor 502, and the current flowing through the parallel resistor is sampled in a magnetic flux quantum unit.
Amplify.

FIG. 12 shows an example of the configuration of an ADC which is effective in the embodiments of FIGS. 1 and 9 for inputting an input signal through an input transformer. The method of FIG. 12 uses the input transformers 103A and 103
In this configuration, the coupling coefficients of B, 103C, and 103D are sequentially reduced by 1/2, and each input transformer is connected to the comparator 500 having the same template. It is clear that this configuration also performs the same operation as the ADC of FIG.

An analog circuit having the circuit configuration shown in FIGS. The principle of digital conversion is explained in FIG. In order to convert an analog signal into a digital signal, as shown in FIG. 13, templates each having a different cycle by a number corresponding to the number of conversion bits are prepared and the position of the input signal is examined. For example, in the example of FIG. 13, when the input signal is (11), (1011) is output using this template. In the circuit example of FIG. 12, instead of preparing a template having a double period, the current is successively reduced to 1/2 and conversion is performed by one type of template. The example in FIG. 13 is
This is an example of converting an analog signal into a natural binary number. In order that the boundary between "0" and "1" of the output digital signal becomes as shown in FIG. 13, a bias resistor circuit is provided in the ADC, and the magnetic flux is set to -1 by the bias line of the quantizer of the comparator.
It is sufficient to apply / 4Φ ₀ . Therefore, the resistors 504, 505, 506 and 507 of the bias circuits of FIGS. 11 and 12 have the same resistance value.

FIG. 14 shows a ladder type AD using a gray code.
It is a structural example of C. The input resistance circuit is connected as shown in the figure, but unlike the input resistance circuit of FIG. 11, the input of the comparator of the maximum effective bit cannot be further divided. The bias resistance circuit is connected only to the comparator of the maximum effective bit as shown in the figure. FIG. 15 shows an example of the configuration of an input transformer type ADC using a gray code. Input transformer 103
Although the coupling coefficient of A, 103B, and 103C becomes smaller by 1/2, the input transformer 103D becomes the input transformer 1.
The same as the coupling coefficient of 03C. Gray analog signal
The principle of code conversion is shown in FIG. An example of the structure of a decoder for converting a gray code into a natural binary number is shown in FIG. The decoder sequentially obtains the lower significant bits from the maximum significant bit by the XOR logical operation by the conversion method of Equation 2, but since it has a completely pipelined system configuration, the decoder has the same frequency as the sampling rate of the comparator. -It can be converted. The XOR logic operation gate used for the decoder is composed of two stages of QFP, and an example is shown in FIG.

[0026]

[Equation 2]

[0027]

As described above, according to the present invention,
An ADC having the following advantages can be constructed. (1) The power supply margin is large because sampling is performed at the rising edge of the excitation transient. (2) Less erroneous conversion due to noise and a larger number of conversion bits (3) Since the output of the quantizer has almost the same absolute value, it is possible to perform sampling at a higher speed than the ADC configured by QFP so far. (4) If a gray code is used, erroneous conversion can occur in only 1 bit at the maximum, so that a more accurate ADC can be performed.

Therefore, the present invention provides an important means for realizing a high speed ADC.

[Brief description of drawings]

FIG. 1 is a schematic view of a first embodiment of a comparator according to the present invention.

FIG. 2 is a schematic diagram of an example of an example of a QFP used in the present invention.

FIG. 3 is a schematic diagram of a first embodiment of a quantizer according to the present invention.

FIG. 4 is a graph showing output characteristics of the quantizer shown in FIG.

FIG. 5 is a schematic view of another quantizer embodiment according to the present invention.

FIG. 6 is a graph showing the output of a quantizer according to the present invention.

FIG. 7 is a graph showing the execution input of the sampler obtained by adding the output of FIG. 6 and the bias input of the sampler.

FIG. 8 is a graph showing the output of the comparator according to the present invention.

FIG. 9 is a schematic view of an embodiment of another comparator according to the present invention.

10 is a schematic view showing a structure in which a Josephson device is attached to the comparator shown in FIG.

FIG. 11 is a block diagram of a resistance shunt type ADC circuit having a 4-bit configuration without using a gray code according to the present invention.

FIG. 12 is a block diagram of an input transformer type ADC circuit having a 4-bit configuration without using a gray code according to the present invention.

FIG. 13: Analog without gray code. The graph explaining a digital conversion method.

FIG. 14 is a block diagram of a 4-bit resistance shunting ADC circuit using a gray code according to the present invention.

FIG. 15 is a configuration diagram of an input transformer type ADC circuit having a 4-bit configuration using a gray code according to the present invention.

FIG. 16 is an analog diagram using a gray code. The graph explaining a digital conversion method.

Figure 17: Pipeli to convert gray code to natural binary
The block diagram of a ned system decoder circuit.

FIG. 18 is a configuration diagram of an XOR operation circuit using QFP.

[Explanation of symbols]

103A, 103B, 103C, 103D ... Input transformer, 201, 202 ... Josephson element, 203a, 2
04a ... Superconducting inductor, 203b, 204b ... Inductor, 203c, 204c ... Inductor, 205 ... Superconducting load inductor, 206 ... Excitation power supply, 207 ... Excitation wiring, 210 ... QFP superconducting loop, 216 ... Josephson element, 300 ... Quantizer, 301 ... Quantizer bias line, 302 ... Quantizer control line, 303 ... Quantizer input line, 311, 313
… Superconducting inductors 312… Superconducting transformers 314
Inductor 315 Superconducting transformer 316 Superconducting inductor 318 Superconducting inductor 400 Sampler 500 Comparator 501 502 5
03 ... resistance, 504, 505, 506, 507 ... resistance,
600 ... Decoder, 700a, 700b, 700c ... Quantum magnetic flux parametron.

Claims (10)

[Claims] 1. Two loops. A superconducting loop including an inductor and a Josephson element, a load inductor connected to the superconducting loop, and the loop. A quantum flux parametron composed of an exciting inductor magnetically coupled to the inductor, a control line connected to the contact point of the superconducting loop and the load inductor, a bias line connected to the exciting inductor, and the loop. A superconducting analog having a superconducting quantizer composed of an input inductor magnetically joined to the inductor and a means for sending an analog signal to the input line connected to the input inductor. Digital converter. 2. An input line according to claim 1, wherein the input line is directly connected to the loop of the quantizer. A superconducting analog having a superconducting quantizer, which is connected between an inductor and a Josephson element and has means for flowing an analog signal. Digital converter. 3. The quantum flux parametron according to claim 1, an input line connected to a contact point of the superconducting loop and a load inductor, and an excitation connected to the excitation inductor. A sampler comprising a means for flowing an excitation current through a line, and the quantizer, wherein an analog input signal is input to the sampler via the quantizer, and sampling is performed by causing the excitation signal to flow through the excitation line of the sampler. A superconducting analog composed of a comparator which is characterized by being amplified. Digital converter. 4. The quantizer according to claim 1 or 2, wherein the quantizer forms a superconducting loop independent of the sampler, and the load inductor of the quantizer and the sampler are connected to each other. By providing a superconducting transformer in parallel with a load inductor, the quantizer and the sampler are magnetically coupled, and an analog input signal is supplied from an input line of the quantizer. analog. Digital converter. 5. The input according to claim 1 or 2, wherein the quantizer is connected in series with the sampler via a superconducting inductor and is connected to an exciting inductor of the quantizer. A superconducting analog characterized in that an analog input signal is supplied from the wire. Digital converter. 6. Claims 3, 4, or 5
Section of the sampler loop. A superconducting analog in which a Josephson element is connected in parallel with an inductor. Digital converter. 7. An input resistance circuit for shunting an input current is provided in claim 3, and each current shunted by the input resistance circuit is supplied to each of the comparators. , A superconducting analog in which a bias resistance circuit is provided to supply a bias current to each comparator. Digital converter. 8. The superconducting analog device according to claim 7, wherein the input resistance circuit is formed by arranging resistors in a ladder shape. Digital converter. 9. The method according to claim 3 or 7, wherein the coupling coefficient with each of the plurality of comparators is different, and a current signal of a specific multiple or a specific multiple of the input signal is supplied to each comparator. -A superconducting analog circuit characterized in that an input transformer for supplying the bias current to the comparator and a bias resistance circuit for supplying the bias current to the comparator are provided. Digital converter. 10. The gray code according to claim 1, when the output digital signal is a gray code.
A superconducting analog characterized in that a pipelined type decoder composed of quantum flux parametrons is provided to convert the codes into natural binary numbers. Digital converter.