KR20090053670A - Apparatus of image tracking soc chip development for ntsc/pal camera - Google Patents

Abstract

An image tracking chip development apparatus for performing image tracking in response to an image signal input from a camera moving by a motor detects a motion image by receiving the image signal from the camera and outputs coordinate information of the detected motion image. And a controller for driving the motor in response to the coordinate information output from the processor module, and a personal computer for displaying the image signal output from the camera and the coordinate information from the processor module.

NTSC / PAL Camera, Video Tracking, SoC, FPGA

Description

Device for developing video tracking chip for NTS / P.A. Camera {APPARATUS OF IMAGE TRACKING SOC CHIP DEVELOPMENT FOR NTSC / PAL CAMERA}

The present invention relates to a chip development apparatus, and more particularly, to a device and method for developing an image tracking chip for NTSC / PAL (NTSC / PAL) camera.

The present invention is derived from the research conducted as part of the core technology development project of IT new growth engine of the Ministry of Knowledge Economy and ICT [Innovation of IT SoC core design manpower].

Recently, according to the trend of high performance and intelligence in the field of surveillance cameras, many SoC (System on a chip) chips for image detection and tracking have been developed. The existing SoC development method for NTSC / PAL cameras first implements algorithms in a software base using sample pictures or PC cameras on a personal computer (PC), and then converts these algorithms into field-programmable (FPGA) fields. The procedure of porting a target board, called a gate array, into a language of a hardware base and implementing and testing it was carried out.

If algorithms are not easy to develop and verify on personal computers, they have been implemented at the FPGA level to perform error correction. However, if the development of the core algorithm for image tracking and the implementation at the hardware level are separated from each other, it takes not only a long development period but also a lot of effort and time in the process of verifying the SoC later.

Therefore, there is an urgent need for new development methods and devices to cope with short development cycles and short development cycles of NTSC / PAL camera image processing chips.

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems, NTSC / PAL that can simultaneously verify and test the SoC logic using the target FPGA board while simulating the image input from the NTSC / PAL camera in real time An apparatus and method for developing an image tracking chip for a camera are provided.

In order to achieve the above object, an image tracking chip development apparatus for performing image tracking in response to an image signal input from a camera moving by a motor of the present invention includes: receiving the image signal from the camera and detecting a moving image, A processor module for outputting coordinate information of the detected motion image; a controller for driving the motor in response to the coordinate information output from the processor module; and an image signal output from the camera and the coordinate information from the processor module. A personal computer to display. The video signal output from the camera is an analog video signal, and further includes an analog-to-digital converter for converting the analog video signal into a digital video signal and providing the same to the processor module and the personal computer, respectively.

In this embodiment, the image tracking chip development device, USB device for converting the digital video signal output from the analog-to-digital converter into a universal serial bus (USB) signal, and provides the converted USB signal to the personal computer It further includes.

In this embodiment, the personal computer stores the coordinate information output from the processor module.

In this embodiment, the personal computer includes a display device for displaying the coordinate information output from the processor module in the form of an on-screen display (OSD).

In this embodiment, the processor module is a field-programmable gate array (FPGA).

According to another aspect of the present invention, there is provided a method of developing an image tracking chip for tracking a motion image in response to an image signal input from a camera moving by a motor, the method comprising: detecting a motion image by receiving the image signal from the camera, Outputting coordinate information of the detected motion image; driving the motor in response to the coordinate information output from the processor module; and displaying the image signal from the camera and the coordinate information from the processor module. It includes a step.

In the present embodiment, the outputting of the coordinate information includes outputting coordinates respectively representing a start position and an end position of the motion image.

In this embodiment, the displaying step includes displaying a movement area defined by the start position coordinates and the end position coordinates of the motion image on the image signal from the camera.

In this embodiment, the displaying step further includes displaying parameter information set in the processor module.

In this embodiment, the processor module is a field-programmable gate array (FPGA).

According to the present invention as described above, it is possible to perform a real-time simulation by high-speed transmission of the image of the NTSC / PAL camera to the PC. The interface with the target FPGA board allows simultaneous verification and testing of SoC logic.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing an image tracking chip development apparatus according to a preferred embodiment of the present invention.

The novel image tracking chip development apparatus 100 of the present invention includes an NTSC / PAL camera 110, a motor 120, an analog-to-digital converter 130, a processor module 140, a controller 150, a personal computer ( 160 and a USB device 170. In this embodiment, the processor module 140 is implemented with a field-programmable gate array (FPGA).

The NTSC / PAL camera 110 converts an image input through a lens (not shown) into an analog image signal and outputs the analog image signal. The motor 120 moves the NTSC / PAL camera 110 under the control of the controller 150. For example, the camera 110 may be connected to the motor 120 through a rotating shaft (not shown), and may be configured such that the camera 110 rotates left and right by the rotating shaft according to the driving of the motor 120. The rotation direction, rotation angle, and rotation speed of the camera 110 by the motor may be variously changed.

The analog-digital converter 130 converts an analog video signal output from the NTSC / PAL camera 110 into a digital video signal and outputs the digital video signal. The digital video signal output from the analog-to-digital converter 130 is provided to the FPGA 140. The FPGA 140 includes logic for detecting a moving object in the digital image signal, and logic for tracking a moving path of the detected object. The FPGA 140 detects a moving object from the digital image signal input through the analog-to-digital converter 130, and outputs coordinates (X, Y) indicating a moving path of the moving object. The controller 150 outputs a control signal CTRL for driving the motor 120 to move the NTSC / PAL camera 110 according to the coordinates X and Y output from the FPGA 140.

The process of detecting the moving object and outputting coordinates (X, Y) by the FPGA 140 is as follows. When the position of the camera 110 is fixed and the digital image signals of the two series of image frames input from the camera 110 are the same, the FPGA 140 determines that there is no moving object. FPGA 140 includes a memory (not shown) for storing at least two image frames for image signal comparison of a series of two image frames.

If the position of the camera 110 is fixed and the digital video signals of some regions of the two image frames input from the camera 110 are different from each other, the FPGA 140 may indicate that there are moving objects in the regions. And the center coordinates (X, Y) of the moving object are output. The at least two series of image frames for detecting the moving object may be frames consecutive in time or image frames input at predetermined time intervals. For example, the FPGA 140 may compare the n th frame and the n + 1 th frame or the n th frame and the n + 3 th frame to detect a moving object. The FPGA 140 selects the coordinates of the upper left and the lower right of the region in which the two image signals of the series are different, and outputs the coordinates of the center position of the region as the center coordinates (X, Y).

The FPGA 140 outputs coordinates (X, Y) of the moving object when the digital image signals of some regions of the series of two image frames input from the camera 110 are different from each other, and the controller 150 coordinates ( The control signals CTRL corresponding to X and Y are output. The motor 120 rotates the camera 110 in response to the control signal CTRL from the controller 150. As a result, the camera 110 may rotate along the moving path of the moving object. The control signal CTRL output from the controller 150 is a signal for controlling the rotation speed, the rotation angle, and the like of the motor.

The camera 110 continuously receives an image while rotating, and outputs an analog image signal corresponding to the input image. However, in order to detect the moving object, a series of two image frames input from the camera 110 must be provided to the FPGA 140 while the position of the camera 110 is fixed. If the rotational speed of the camera 110 is controlled by driving the motor 120, a series of two image frames input from the camera 110 may be provided to the FPGA 140 while the position of the camera 110 is fixed. Can be.

The USB device 170 converts the digital video signal 130 output from the analog-to-digital converter 130 into a USB 2.0 signal and transmits the digital video signal 130 to the personal computer 160. The personal computer 160 displays an image corresponding to the digital image signal input through the USB device 170 on the display device 162. Therefore, the user can monitor the same image as that provided from the NTSC / PAL camera 110 to the FPGA 140 in real time.

Coordinates X and Y output from the FPGA 140 described above are also provided to the personal computer 160. Since the personal computer 160 of the present invention is equipped with software implementing the image tracking algorithm, the user may debug the image tracking algorithm in real time while monitoring the image displayed on the display device 162.

For example, while designing the FPGA 140, a user may compare the n th frame and the n + 1 th frame of the video signal input from the camera 110 to detect the moving object, or compare the n th frame and the n + 3 th frame. Should be selected. The user monitors whether the camera 110 properly tracks a moving object while viewing the image input from the camera 110 through the analog-digital converter 130 and the coordinates (X, Y) output from the FPGA 140. In addition, the algorithm stored in the personal computer 160 may be modified to adjust the interval between two frames to be compared.

In addition, the software implemented in the personal computer 160 stores the digital image signal input from the NTSC / PAL camera 110 and the coordinates (X, Y) output from the FPGA 140 in the form of an OSD (On Screen Display). In the future, the user can debug the image tracking algorithm by comparing the image state with the stored coordinates (X, Y).

2A to 2D are diagrams illustrating examples in which a moving object is detected by the image tracking chip development apparatus illustrated in FIG. 1.

As shown in FIGS. 2A-2D, the FPGA 140 detects moving object regions M1-M4 by comparing a series of video signals of two frames, and displays the current frame displayed on the display device 162. The moving object regions M1-M4 are indicated. The FPGA 140 outputs coordinates (X, Y) of the center positions of the detected moving object regions M1-M4. In addition to the center point coordinates X and Y of the moving object regions M1 to M4, the FPGA 140 may not only detect the starting point coordinates of the upper left and the end points of the lower right of the detected moving object regions M1 to M4. It can be provided to the personal computer 160. In this case, the personal computer 160 adds markers representing the moving object regions M1-M4 to the image signal input from the camera 110 and displays them on the display device 162. In addition, the difference values of the video signals of the two frames may be further displayed on the display device 162 as a graph.

Since the accuracy of detecting the moving object by the video tracking chip integrated into the SoC may vary depending on the surrounding environment, the parameter values such as sensitivity, noise threshold, and target size are set in the video tracking chip. do. Here, the sensitivity refers to an ability to detect change of an image due to illuminance around the camera. The noise limit refers to a signal change range for discriminating noise included in an image signal, that is, whether to recognize a change range of two frames of a received signal as a moving object or noise. The size means the size of an image signal input from the camera 110, that is, the size of one frame.

In the development of such an image tracking chip, parameters such as sensitivity, size, and noise limit are also set in the FPGA 140. The personal computer 160 of the present invention includes a function of extracting these parameters into an optimized value. To enable the development of video tracking chips. That is, when the personal computer 160 displays the parameters set in the FPGA 140 on the display device 162, the user can easily determine whether the motion tracking is normally performed according to the currently set values of the parameters. In addition, the user may change the parameters to be set in the FPGA 140 while viewing the image displayed on the display device 162.

As described above, according to the present invention, the time required for repeating the circuit implementation and verification countless times in the development of image-related SoC can be significantly reduced. In other words, not only algorithm derivation, simulation, FPGA logic implementation, test and verification, and algorithm modification are performed sequentially, but also the FPGA logic can be monitored and the operation result of the FPGA logic on the personal computer can be monitored. Debugging is possible.

Therefore, by making SoC chip development such as image detection and tracking faster and easier, it is possible not only to cope with the shorter development cycle but also to develop more accurate SoC chip.

In addition, by applying such a development device, it is possible to use not only logic test limited by a simple test vector but also a mounting tester that can determine whether an SoC chip is defective by an image monitoring function.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a view showing an image tracking chip development apparatus according to a preferred embodiment of the present invention.

2A to 2D are diagrams illustrating an example of optimal image tracking parameter extraction by the image tracking chip development apparatus illustrated in FIG. 1.

Claims (11)

In an image tracking chip development apparatus for performing image tracking in response to an image signal input from a camera moving by a motor: A processor module configured to receive the video signal from the camera, detect a motion image, and output coordinate information of the detected motion image; A controller for driving the motor in response to the coordinate information output from the processor module; And And a personal computer for displaying the image signal output from the camera and the coordinate information from the processor module. The method of claim 1, The video signal output from the camera is an analog video signal; And an analog-to-digital converter for converting the analog video signal into a digital video signal and providing the analog video signal to the processor module and the personal computer, respectively. The method of claim 2, And a USB device for converting the digital video signal output from the analog-digital converter into a universal serial bus (USB) signal and providing the converted USB signal to the personal computer. . The method of claim 1, And the personal computer stores the coordinate information output from the processor module. The method of claim 1, And the personal computer includes a display device for displaying the coordinate information output from the processor module in the form of an on-screen display (OSD). The method of claim 1, And the processor module is a field-programmable gate array (FPGA). In a method of developing an image tracking chip that tracks a moving image in response to an image signal input from a camera moving by a motor: Receiving the video signal from the camera, detecting a motion image, and outputting coordinate information of the detected motion image; Driving the motor in response to the coordinate information output from the processor module; And And displaying the image signal from the camera and the coordinate information from the processor module. The method of claim 7, wherein The step of outputting the coordinate information, And outputting coordinates respectively representing a start position and an end position of the motion image. The method of claim 8, The display step, And displaying a motion area defined by the start position coordinates and the end position coordinates of the motion image on the image signal from the camera. The method of claim 7, wherein The display step, And displaying parameter information set in the processor module. The method of claim 7, wherein And the processor module is a field-programmable gate array (FPGA).

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