KR20090049270A - Phase change random access memory and method of manufacturing the same - Google Patents

Abstract

A phase change memory device having a diode that can be manufactured simultaneously with a MOS transistor, and a method of manufacturing the same. The disclosed phase change memory device is divided into a plurality of unit memory cell regions and includes a semiconductor substrate having a recess having a predetermined depth formed in each unit memory cell region, a word line structure formed at a portion of the recess, and the word line structure. A conductive layer having a first conductivity type remaining in a bottom portion of the remaining portion of the recess while electrically connected to the conductive layer, and being in contact with the conductive layer of the first impurity type to form a diode to overlap the word line structure. And a plug of a conductive layer having a second conductivity type.

Phase Change Memory, Diodes, Morse Transistors, Recesses

Description

Phase Change Random Access Memory And Method of manufacturing The Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory device and a method of manufacturing the same, and more particularly, to a phase change memory device in which a peripheral region and a cell region are simultaneously manufactured.

Phase change random access memory (PRAM) stores data using a phase change material whose crystal state varies with temperature. That is, the phase change material changes to a crystalline state or an amorphous state with temperature, and the resistance of the phase change material changes with the change of the crystal state. In addition, since the phase change material can be mutually reversible, it can be used as a storage medium of a memory device. As the phase change material, for example, chalcogenide material such as GST (GeSbTe) may be used.

As illustrated in FIG. 1, a plurality of phase change memory devices are formed in regions where word lines WLn-1 to WLn + 2 and bit lines BLn-2 to BLn + 2 cross each other. It may be configured as a cell MC. The phase change memory cell MC includes a resistor R that changes in size according to a through current, and a switching element SW that controls a current provided to the resistor R. Here, the resistor R may be a phase change material layer, and as the switching device SW, a PNP bipolar transistor, a MOS transistor, or a PN diode may be used, and as a switching device of a currently integrated phase change memory device. PN diodes occupying a small area are mainly used.

Such a PN diode is formed in a vertical type to occupy a narrow area. The vertical type diode is formed by injecting P-type impurities into an N-type selective epitaxial growth (SEG) pillar.

However, as is known, the phase change memory device includes a peripheral area including elements for driving a phase change memory cell MC, and these peripheral areas are provided with MOS transistors similarly to general DRAM devices. . Therefore, the memory cell (MC) region using the vertical type diode as the switching element and the peripheral region including the MOS transistor are formed independently by different processes.

Therefore, the conventional phase change memory device has a problem of increasing the process time since the process of forming the memory cell region and the process of forming the peripheral region must be performed separately.

Accordingly, it is an object of the present invention to provide a phase change memory device having a diode that can be fabricated simultaneously with a MOS transistor.

In addition, another object of the present invention is to provide a method of manufacturing a phase change memory device capable of simultaneously manufacturing a memory cell region and a peripheral region.

In order to achieve the above object of the present invention, a phase change memory device according to an embodiment of the present invention is divided into a plurality of unit memory cell regions and includes a semiconductor having a predetermined depth formed in each unit memory cell region. A substrate, a word line structure formed in a portion of the recess, a conductive layer having a first conductivity type electrically connected to the word line structure and remaining at a bottom of the remaining portion of the recess, and the first impurity type And a plug having a second conductive type having a second conductivity type formed in contact with the conductive layer of the semiconductor layer and overlapping the word line structure.

In addition, a method of manufacturing a phase change memory device according to another embodiment of the present invention is as follows. First, a semiconductor substrate in which a plurality of unit memory cell regions are defined is prepared, and a recess is formed in each unit memory cell region. Thereafter, a word line structure including a conductive layer having a first conductivity type is formed in a portion of the recess, and a conductive layer having the first conductivity type is left in the remaining portion of the recess. The plug is formed of a conductive layer having a second conductivity type to be in contact with the conductive layer having the remaining first conductivity type.

Also, a phase change memory device according to still another embodiment of the present invention may include a plurality of word lines, a plurality of bit lines crossing each of the plurality of word lines, and defining a plurality of unit memory cells, and the word line and the bit. And a diode and a phase change material layer as switching elements respectively formed at the intersections of the lines, the cathode of the diode being configured to be connected with the phase change material layer and its anode connected to the word line.

According to this embodiment, a recess is formed in the unit memory cell region, and a plug connected to the word line structure and the word line structure is formed in the recess to form a diode. As a result, a diode in the memory cell region is formed on the sidewalls of the MOS transistor in the form of a recess gate. Therefore, since the MOS transistor and the diode can be simultaneously implemented, the peripheral region where the MOS transistor is mainly formed and the memory cell region where the diode is mainly formed can be simultaneously manufactured. As a result, ancillary processes can be reduced.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 2, an N well 105 is formed in a region predetermined as a memory cell region mc of a semiconductor substrate 100, for example, a P-type silicon substrate. The N well 105 may be formed by a known ion implantation process of N-type impurities. Next, an element isolation film 110 is formed in a predetermined portion of the semiconductor substrate 100, between the semiconductor substrate 100 and the N well 105 region, and in a predetermined portion of the N well 105. For example, a shallow trench isolation (STI) film may be used as the device isolation film 110. Here, the device isolation layer 110a formed between the semiconductor substrate 100 and the N well 105 serves to electrically separate the memory cell region MC from the peripheral region (not shown), and the N well ( The device isolation layer 110b formed in the 105 divides the plurality of unit memory cells.

Referring to FIG. 3, a buffer layer 115 is formed on a result of the semiconductor substrate 100, and a mask pattern 120 for opening a unit memory cell is formed on the buffer layer 115. The mask pattern 120 may be integrally formed with a mask pattern (not shown) for defining a recess gate electrode in a peripheral area (not shown). The buffer layer 115 may reduce a stress between the semiconductor substrate 100 or the device isolation layer 110 and the mask pattern 120. For example, a polysilicon layer may be used.

The buffer layer 115 is patterned in the form of the mask pattern 120, and then the exposed N well 105 region is etched using the patterned buffer layer 115 as a mask, thereby forming a recess r in the unit memory cell region. ) Is provided. At the same time, a recess (not shown) is formed in the gate electrode predetermined region in the peripheral region (not shown).

Next, the mask pattern 120 and the buffer layer 115 are removed by a known method. Subsequently, although not shown in the drawing, a gate insulating film of a thin film is formed on the exposed recess r surface. Thereafter, a polysilicon layer 125 doped with P-type impurities is deposited on the result of the semiconductor substrate 100 to fill the recess r. The polysilicon layer 125 doped with the P-type impurity then serves as a word line of the PRAM device. The conductive silicide layer 130 may be further formed on the polysilicon layer 125 doped with the P-type impurity to improve the conductivity of the polysilicon layer 125 doped with the P-type impurity. The conductive silicide layer 130 may be, for example, a tungsten silicide layer Wsi2. The hard mask layer 135 is formed on the tungsten silicide layer. The hard mask layer 135 is provided for facilitating the patterning of the conductive silicide layer 130 and the polysilicon layer 125, and for arranging the lower electrode (diode) to be formed later and the word line in a self-aligned manner. . For example, a silicon nitride film may be used as the hard mask film 135.

As shown in FIG. 5, a word pattern defining mask pattern (not shown) is formed on the hard mask layer 135. The hard mask layer 135 is patterned in the form of a word line defining mask pattern, and then the conductive silicide layer 130 and the polysilicon layer 125 are etched in the form of the patterned hard mask layer 135 to form a word line structure. 140 is formed. During the etching, the etch stop point is adjusted so that the polysilicon film 125 remains in the recess r.

As shown in FIG. 6, an insulating film 145 for the spacer is formed along the surface of the semiconductor substrate 100. The spacer insulating film 145 may be formed of a silicon oxide film, a silicon nitride film, and a stacked film of a silicon oxide film and a silicon nitride film. Next, a first interlayer insulating layer 150 having a planarized surface is formed on the spacer insulating layer 145. The first interlayer insulating film 150 having the planarized surface may be obtained, for example, by forming an insulating film such that the word line structure 140 is sufficiently buried, and then chemically mechanical polishing the insulating film.

Referring to FIG. 7, a mask pattern 155 is formed on the first interlayer insulating layer 150 to expose the polysilicon layer 125a remaining in the recess r. The mask pattern 155 may be integral with a mask that opens a junction region when fabricating a MOS transistor in a peripheral region. Next, the exposed interlayer insulating layer 150 and the spacer insulating layer 145 are anisotropically etched using the mask pattern 155. As a result, a contact hole H is formed in the first interlayer insulating layer 150 to expose a portion of the word line structure 140 and the remaining polysilicon layer 125a on the recess r. In addition, when the contact hole H is formed, a spacer 145a is formed on the sidewall of the word line structure 140 by anisotropic etching of the spacer insulating layer 145.

Referring to FIG. 8, the mask pattern 155 is removed in a known manner. Thereafter, a conductive film doped with N-type impurities, for example, a polysilicon film doped with N-type impurities, is deposited on the first interlayer insulating layer 150 to fill the contact hole H. Thereafter, the conductive film doped with N-type impurities is planarized so that the first interlayer insulating layer 150 is exposed to form the N-type plug 160.

The N-type plug 160 forms a PN junction with the P-type polysilicon film 125a remaining in the recess r, and is driven as a PN diode of the unit memory cell MC. 200 in the figure represents a PN diode. At this time, the N-type plug 160 is self-aligned with the silicide layer 130 which actually functions as a word line by the hard mask layer 135 and the spacer 145 and the polysilicon layer 125 doped with P-type impurities. Insulation can be achieved.

Next, referring to FIG. 9, the phase change material layer 165 and the upper electrode 170 are sequentially formed on the N-type plug 160. In this case, the phase change material layer 165 may be, for example, a chalcogenide compound, and the upper electrode 170 may be a Ti / TiN-based conductive layer. A second interlayer insulating layer 180 is formed on the resultant of the first interlayer insulating layer 150, and then a bit line 190 is formed to be electrically connected to the upper electrode 170. Here, reference numeral 185 denotes a via contact for connecting the upper electrode 170 and the bit line 190.

Such a diode of this embodiment is self-aligned on the sidewall of a MOS transistor having a recess gate structure. Accordingly, the diode can be formed in the memory cell region simultaneously with the fabrication of the MOS transistors in the peripheral region without the need for forming the diode individually. Furthermore, since the memory cell regions of the present embodiment are all formed by a mask for fabricating transistors in the peripheral region without an additional mask pattern, the memory cell region and the peripheral region can be simultaneously processed without any additional process.

10 is a circuit diagram of a PRAM device according to an embodiment of the present invention.

Referring to FIG. 10, a plurality of word lines WLn−1 to WLn + 2 and a plurality of bit lines BLn−2 to BLn + 2 are arranged crosswise to define a plurality of memory cells mc. In the intersecting regions of the word lines WLn-1 to WLn + 2 and the bit lines BLn-2 to BLn + 2, a resistance R, that is, a phase change material layer and a resistance R, varying in size depending on the penetration current. The diode 200 for controlling the current provided to is connected.

In this case, the diode 200 according to the present exemplary embodiment includes a polysilicon layer 125a and an N-type plug 160 doped with P-type impurities remaining at the bottom of the recess r as described above. The polysilicon layer 125a doped with the P-type impurity of the diode 200 is electrically connected to the word line structure 140, and the N-type plug 160 is in contact with the phase change material layer 165.

Compared with the diode sw structure of FIG. 1, the anode and the cathode are connected oppositely. That is, in the diode sw of FIG. 1, the phase change material layer R and the anode (P type portion) are connected, and the word line WL and the cathode (N type portion) are connected. The phase change material layer R and the cathode (N-type portion) are connected, and the word line WL and the anode (P-type portion) are connected. Even if the connection of the diode 200 is changed in this way, since it only needs to change the setting of the input voltage applied to the word line WL, it is possible to operate as a memory element.

In addition, as shown in FIG. 10, the word line structure 140 is formed of a polysilicon film 126 doped with N-type impurities, and is left at the bottom of the recess r. The plug 161 in contact with the bottom may be made of a P-type polysilicon film. In this case, it may have a diode connection structure as shown in FIG. Reference numeral 200 'denotes a PN junction.

According to this embodiment, a recess is formed in the unit memory cell region, and a plug connected to the word line structure and the word line structure is formed in the recess to form a diode. As a result, a diode in the memory cell region is formed on the sidewalls of the MOS transistor in the form of a recess gate. Therefore, since the MOS transistor and the diode can be simultaneously implemented, the peripheral region where the MOS transistor is mainly formed and the memory cell region where the diode is mainly formed can be simultaneously manufactured. As a result, ancillary processes can be reduced.

Although the present invention has been described in detail with reference to the above-described preferred embodiment, the present invention is not limited to the above embodiment, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is possible.

1 is a circuit diagram of a typical phase change memory device;

2 to 8 are cross-sectional views for each process for explaining a method of manufacturing a phase change memory device according to an embodiment of the present invention;

9 is a circuit diagram of a phase change memory device according to an embodiment of the present invention; and

10 is a cross-sectional view of a phase change memory device according to another exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

125a: polysilicon film doped with residual P-type impurities

140: word line structure 145: spacer

160: N-type plug 165: phase change material layer

170: upper electrode 190: bit line

200: diode

Claims (18)

A semiconductor substrate divided into a plurality of unit memory cell regions and including a recess having a predetermined depth formed in each of the unit memory cell regions; A wordline structure formed in a portion of the recess; A conductive layer electrically connected with the wordline structure, the conductive layer having a first conductivity type remaining at a bottom of the remaining portion of the recess; And And a plug comprising a conductive layer having a second conductive type which contacts the first conductive type conductive layer to form a diode. The method of claim 1, The wordline structure is A conductive layer having a first conductivity type formed so that a portion of the recess is buried; A hard mask film formed over the conductive layer having the first conductivity type; And A spacer formed on the sidewall surface of the hard mask layer and the conductive layer having the first conductivity type, And a conductive layer having the first conductive type constituting the word line structure extends without disconnection from the conductive layer having the first conductive type remaining in the recess bottom portion. The method of claim 2, And a conductive silicide layer further interposed between the conductive layer having the first conductivity type and the hard mask layer of the word line structure. The method of claim 1, And the plurality of unit memory cell regions are defined by device isolation layers. The method of claim 1, And a phase change film and an upper electrode are sequentially formed on the plug. The method of claim 1, The conductive layer having the first conductivity type is a polysilicon film doped with P-type impurities, And wherein the conductive layer having the second conductivity type is a polysilicon film doped with N type impurities. The method of claim 1, The conductive layer having the first conductivity type is a polysilicon film doped with N-type impurities, And wherein the conductive layer having the second conductivity type is a polysilicon film doped with P-type impurities. The method of claim 1, And the plug is formed to overlap the word line structure. The method of claim 1, And the plug is formed adjacent to the word line structure. Providing a semiconductor substrate in which a plurality of unit memory cell regions are defined; Forming a recess in each unit memory cell area; Forming a word line structure comprising a conductive layer having a first conductivity type in a portion of the recess, and leaving a conductive layer having the first conductivity type in the remaining portion of the recess; And Forming a plug with a conductive layer having a second conductivity type to be in contact with the conductive layer having the remaining first conductivity type. The method of claim 10, Forming the word line structure and at the same time leaving a conductive layer having the first conductivity type, Depositing a conductive layer having the first conductivity type on a semiconductor substrate such that the recess is sufficiently buried; Forming a hard mask layer on the conductive layer having the first conductivity type; And partially patterning the conductive layer having the hard mask layer and the first conductive type, and leaving the conductive layer having the first conductive type. The method of claim 11, Between depositing a conductive layer having the first conductivity type and forming the hard mask film, And forming a conductive silicide layer on the conductive layer having the first conductivity type. The method of claim 11, After leaving the conductive layer having the first conductivity type, Forming an insulating film for a spacer on the resultant material; Forming an interlayer insulating film on the spacer insulating film; Anisotropically etching the interlayer insulating film and the insulating film for spacers to expose the conductive layer having the first conductivity type remaining in the recess, thereby preparing a space for forming a plug. Way. The method of claim 10, After forming the plug, Forming a phase change film on the plug; And And forming an upper electrode on the phase change layer. The method of claim 10, The conductive layer having the first conductivity type is a polysilicon film doped with P-type impurities, And wherein the conductive layer having the second conductivity type is a polysilicon film doped with N-type impurities. The method of claim 10, The conductive layer having the first conductivity type is a polysilicon film doped with N-type impurities, And the second conductive type conductive layer is a polysilicon film doped with P-type impurities. A plurality of word lines; A plurality of bit lines crossing each of the plurality of word lines to define a plurality of unit memory cells; And A diode and a phase change material layer as switching elements respectively formed at intersections of the word line and the bit line, And a cathode of the diode is connected with the phase change material layer and an anode thereof is connected with a word line. A semiconductor substrate divided into a plurality of unit memory cell regions and including a recess having a predetermined depth formed in each of the unit memory cell regions; A conductive region having a first conductivity type formed in the recess; A word line structure formed to contact the first region of the conductive region; And a plug of a conductive layer having a second conductivity type forming a diode in contact with a second region of the conductive region adjacent to the first region of the conductive region.

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