KR20090048942A - Fuse of semiconductor device and forming method thereof - Google Patents

Fuse of semiconductor device and forming method thereof Download PDF

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Publication number
KR20090048942A
KR20090048942A KR1020070115060A KR20070115060A KR20090048942A KR 20090048942 A KR20090048942 A KR 20090048942A KR 1020070115060 A KR1020070115060 A KR 1020070115060A KR 20070115060 A KR20070115060 A KR 20070115060A KR 20090048942 A KR20090048942 A KR 20090048942A
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KR
South Korea
Prior art keywords
fuse
main
fuses
sub
semiconductor device
Prior art date
Application number
KR1020070115060A
Other languages
Korean (ko)
Inventor
김준동
이남일
최영현
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070115060A priority Critical patent/KR20090048942A/en
Publication of KR20090048942A publication Critical patent/KR20090048942A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam

Abstract

According to the present invention, by forming sub-fuses separated at regular intervals on both sides of the main fuse, the side of the main fuse is not inclined during the fuse patterning process so that no fuse residue is generated during the subsequent fuse cutting process, and thus the repair process It is made of a fuse of a semiconductor device and a method of forming the same that can improve the reliability of the.

Fuse, Repair, Slope, Slope, Trapezoidal, Main Fuse, Sub Fuse, Loading Effect

Description

Fuse of semiconductor device and forming method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse of a semiconductor device and a method of forming the same, and more particularly, to a fuse of a semiconductor device and a method of forming the fuse, which improves the fuse repair process by preventing residue of the fuse during the fuse cutting process.

The semiconductor device includes a plurality of fuses for a repair process after the manufacturing process of the semiconductor device is completed. The repair process will be described in detail as follows.

The repair process is a process of replacing defective unit cells with an extra normal unit cell among a plurality of unit cells included in the semiconductor device. Specifically, after the semiconductor device is manufactured in a wafer state, an electrical test is performed to confirm whether the semiconductor device operates normally. This is called a probe test. Probe tests can be used to select between normal and defective unit cells. In this case, a process of replacing the defective unit cells with an extra normal unit cell is called a repair process.

In general, the repair process is performed by cutting a fuse for a defective unit cell. There are many methods for cutting a fuse, but recently, a laser cutting method using a simple and accurate process has been used. However, the fuse may have a different sidewall slope of the fuse depending on the spacing (or density) of neighboring fuses, which may make the fuse cutting process difficult. This will be described in detail below.

1A and 1B are cross-sectional views illustrating a fuse and a fuse cutting process of a conventional semiconductor device.

Referring to FIG. 1A, a cross section of a cell region in which unit cells are formed at close intervals and a fuse box region in which a fuse is formed in the semiconductor substrate 10 is illustrated. Specifically, the first insulating film 11 for interlayer insulating film 11 is formed on the semiconductor substrate 10, and the conductive film for metal wiring or fuse is formed on the first insulating film 11. Subsequently, the conductive film is patterned to form the metal wiring 12a and the fuse 12b, and the second insulating film 13 for interlayer insulating film is formed. As such, the fuse 12b may be simultaneously formed during the metallization 12a forming process of the cell region. In addition, contact plugs are formed at both ends of the fuse 12b to be connected to the upper or lower metal wiring.

The metallization 12a formed in the cell region has a tight spacing W1 formed in the manufacturing process of the semiconductor device, but the fuse 12b formed in the fuse box region is formed between the metallization lines 12a formed in the cell region. It is formed at an interval W2 wider than the interval W1. For this reason, a loading effect may be applied during the patterning process so that the sidewall of the fuse 12b is inclined, so that the bottom may be wider than the top. As such, as the lower width is wider than the upper width of the fuse 12b, the subsequent fuse cutting process may become difficult. This will be described with reference to the following drawings.

Referring to FIG. 1B, a cross section of the fuse 12b formed in the fuse box area is illustrated. When the fuse 12b is formed in a trapezoidal shape having a wider bottom surface than the top surface, when the fuse is cut, fuse residues may occur on both sides or one side of the fuse.

As such, if the fuse remains after the fuse is cut, the above-described repair process may not be performed because a voltage may be transmitted through the residue.

Accordingly, by widening the width of the fuse and narrowing the distance between neighboring fuses, it is possible to minimize the loading effect to suppress the inclination of the side of the fuse, but this is the margin margin with the neighboring fuse in the subsequent fuse cutting process The reduction is not efficient as the neighboring fuses can be damaged.

The problem to be solved by the present invention is to form a sub-fuse isolated on both sides of the main fuse at regular intervals, thereby minimizing the loading effect on the main fuse to prevent the side of the main fuse inclined during the fuse patterning process Subsequent fuse cutting processes can be facilitated.

The fuse of the semiconductor device according to the exemplary embodiment of the present invention includes a main fuse. It is formed on both sides of the main fuse, each of the fuses of the semiconductor device including a sub-fuse which is not electrically connected to the main fuse, but any one of both ends in contact with the node. At this time, the width of the sub-fuse is formed to a width of 50% to 85% of the main fuse.

A fuse of a semiconductor device according to another embodiment of the present invention includes main fuses. It is formed on one side of the main fuses between the main fuses, and is made of a fuse of the semiconductor device including a sub-fuse which is not electrically connected to the main fuses, but any one of both ends contacting the node. At this time, the width of the sub-fuse is formed to a width of 50% to 85% of the main fuse.

In the method of forming a fuse of a semiconductor device according to an embodiment of the present invention, a semiconductor substrate having an insulating film is provided. A conductive film is formed on the insulating film. And a method of forming a fuse of the semiconductor device, the method including patterning a conductive film to form a main fuse and sub fuses separated from each other on both sides of the main fuse.

In a method of forming a fuse of a semiconductor device according to another embodiment of the present invention, a semiconductor substrate having an insulating film is provided. A conductive film is formed on the insulating film. Patterning the conductive layer to form sub-fuses isolated from each other between the metal line, the main fuses, and the main fuses.

The gap between the sub fuse and the main fuse is formed to be narrower than the gap between the main fuse and the main fuse and the neighboring main fuse.

The width of the sub-fuse is formed to be narrower than the width of the main fuse, the width of the sub-fuse to form a width of 50% to 85% of the main fuse.

The present invention provides a sub-fuse isolated at regular intervals on both sides of the main fuse, thereby minimizing the loading effect on the main fuse to prevent the side of the main fuse from inclining during the fuse patterning process. It does not generate fuse residues, thereby improving the reliability of the repair process.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided to inform you completely.

2 is a plan view illustrating a fuse of a semiconductor device according to the present invention. Referring to FIG. 2, one fuse structure may have a main fuse 200 and sub fuses 202a and 202b formed at predetermined intervals L1 on both sides or one side of the main fuse 200 so as to be isolated from the main fuse 200. It includes. First and second nodes 204a and 204b are formed at both ends of the main fuse 200, and contact plugs 206 are formed in the first and second nodes 204a and 204b. The sub fuses 202a and 202b may be isolated from the first and second nodes 204a and 204b, or either end of the sub fuses 202a and 202b may be the first node 204a or the second node. 204b. In the drawing, a case in which any one of both ends of the sub fuses 202a and 202b is in contact with the first node 204a or the second node 204b will be described as an example.

The sub-fuses 202a and 202b reduce the loading effect in the fuse patterning process, thereby suppressing the inclination of the side surface of the main fuse 200. The sub-fuses 202a and 202b are adjacent to the main fuse 200 but preferably formed at a constant interval L1. In this case, the interval L1 between the main fuse 200 and the sub fuses 202a or 202b may be formed to be narrower than the interval L2 between the main fuses 200. For this reason, the loading effect of the main fuse 200 may be reduced during the patterning process to suppress the inclination of the side surface of the main fuse 200. That is, the phenomenon that the width of the bottom surface is wider than the upper width of the main fuse 200 may be minimized.

Accordingly, it is preferable that the sub fuses 202a and 202b do not electrically connect the first node 204a and the second node 204b. In this case, contact plugs 206 for electrical connection are formed at the first node 204a and the second node 204b. If the sub fuses 202a and 202b electrically connect the first node 204a and the second node 204b, not only the main fuse 200 but also the sub fuses 202a and 202b during the fuse cutting process. The process is not easy because it must be cut. Therefore, both ends T1 and T2 of the sub fuses 202a and 202b do not contact both the first node 204a and the second node 204b, or only one of both ends (T1 or T2) of the first node. 204a or the second node 204b.

In addition, the sub-fuses 202a and 202b are preferably arranged on both sides of the main fuse 200 in order to suppress the occurrence of inclination of both sides of the main fuse 200, and according to the layout, any one of both sides of the main fuse 200 may be arranged. It may be formed by arranging only one side.

The sub fuses 202a and 202b may be formed to have a width of 50% to 85% of the width of the main fuse 200. In addition, the interval L1 between the sub fuses 202a and 202b and the main fuse 200 may be narrowed according to the resolution of the exposure process, but may not be electrically connected to the main fuse 200 during the patterning process.

Next, a description will be given of a method for manufacturing a fuse of a semiconductor device taking a cross-section in the A-A 'direction as an example.

3 is a cross-sectional view illustrating a fuse of a semiconductor device according to the present invention. The first insulating film 302 for the interlayer insulating film is formed on the semiconductor substrate 300. For example, when a plurality of unit cells or transistors are formed on the semiconductor substrate 300, the first insulating layer 302 may be formed to cover all of the unit cells and the transistors. In addition, a contact plug (not shown) may be formed on the first insulating layer 302 to electrically connect the upper and lower structures. Subsequently, after the fuse conductive film is formed on the first insulating film 302, a patterning process is performed to form the main fuse 200 and the sub fuses 202a and 202b. In this case, the gap L1 between the main fuse 200 and the sub fuses 202a and 202b may be narrowed as the sub fuses 202a and 202b are formed, thereby preventing the sidewall inclination angle of the main fuse 200 from being lowered. have. At this time, the side wall of the main fuse 200 is not inclined, or preferably formed so that the inclination angle θ is 0 ° to 5 °. Next, the second insulating film 304 for interlayer insulating film is filled between the main fuse 200 and the sub fuses 202a and 202b.

As a result, since the sidewalls may be formed to be close to vertical by suppressing an increase in the sidewall inclination angle θ of the main fuse 200, a subsequent fuse cutting process may be easily performed and generation of fuse residues may be prevented. Therefore, the reliability of the repair process can be improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A and 1B are cross-sectional views illustrating a fuse and a fuse cutting process of a conventional semiconductor device.

2 is a plan view illustrating a fuse of a semiconductor device according to the present invention.

3 is a cross-sectional view illustrating a fuse of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

200: main fuse 202a, 202b: sub fuse

204a: first node 204b: second node

206: contact plug 300: semiconductor substrate

302: first insulating film 304: second insulating film

Claims (8)

Main fuse; And And a sub fuse formed on both sides of the main fuse, the sub fuse being in electrical contact with the main fuse and having only one of both ends contacting the node. Main fuses; And A fuse formed between the main fuses on one side of the main fuses, the sub fuse being not connected to the main fuses and contacting a node only at one of both ends thereof. The method according to claim 1 or 2, The fuse of the semiconductor device is a width of 50% to 85% of the width of the main fuse. Providing a semiconductor substrate having an insulating film formed thereon; Forming a conductive film on the insulating film; And Patterning the conductive layer to form a main fuse and sub-fuses isolated from each other on both sides of the main fuse. Providing a semiconductor substrate having an insulating film formed thereon; Forming a conductive film on the insulating film; And Patterning the conductive layer to form metal fuses, main fuses, and sub-fuses isolated from each other between the main fuses. The method according to claim 4 or 5, And a gap between the sub fuse and the main fuse is smaller than a gap between the main fuse and the main fuse adjacent to the main fuse. The method according to claim 4 or 5, And a width of the sub-fuse is smaller than a width of the main fuse. The method according to claim 4 or 5, And a width of the sub fuse is 50% to 85% of the main fuse.
KR1020070115060A 2007-11-12 2007-11-12 Fuse of semiconductor device and forming method thereof KR20090048942A (en)

Priority Applications (1)

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KR1020070115060A KR20090048942A (en) 2007-11-12 2007-11-12 Fuse of semiconductor device and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070115060A KR20090048942A (en) 2007-11-12 2007-11-12 Fuse of semiconductor device and forming method thereof

Publications (1)

Publication Number Publication Date
KR20090048942A true KR20090048942A (en) 2009-05-15

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KR1020070115060A KR20090048942A (en) 2007-11-12 2007-11-12 Fuse of semiconductor device and forming method thereof

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