KR20090048879A - Method of forming wire rerouting pattern for semiconductor packages - Google Patents

Method of forming wire rerouting pattern for semiconductor packages Download PDF

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Publication number
KR20090048879A
KR20090048879A KR1020070114961A KR20070114961A KR20090048879A KR 20090048879 A KR20090048879 A KR 20090048879A KR 1020070114961 A KR1020070114961 A KR 1020070114961A KR 20070114961 A KR20070114961 A KR 20070114961A KR 20090048879 A KR20090048879 A KR 20090048879A
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KR
South Korea
Prior art keywords
forming
laser
interlayer insulating
redistribution
layer
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Application number
KR1020070114961A
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Korean (ko)
Inventor
박진우
안은철
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삼성전자주식회사
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Priority to KR1020070114961A priority Critical patent/KR20090048879A/en
Publication of KR20090048879A publication Critical patent/KR20090048879A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention provides a method for forming a redistribution pattern of a semiconductor package capable of forming a redistribution pattern by electroless plating using a laser without using a seed metal layer. The method for forming a redistribution pattern may include providing a semiconductor substrate on which electrode pads are formed, forming a first interlayer insulating layer including a first opening exposing a portion of the electrode pad, and forming an adhesive layer on the first interlayer insulating layer. Forming a second interlayer insulating layer comprising a forming step, activating a portion of the adhesive layer using a laser, forming a redistribution layer on the activated adhesive layer, and a second opening exposing a portion of the redistribution layer. The step of forming, and the step of forming the redistribution layer using an electroless plating.

Semiconductor Package, Rewiring, Relocation, Electroless Plating, Laser

Description

Method of forming wire rerouting pattern for semiconductor packages

The present invention relates to a method for forming a redistribution pattern of a semiconductor package, and more particularly, to a method for forming a redistribution pattern of a semiconductor device by electroless plating using a laser.

In general, higher integration of semiconductor devices results in thinner line widths of design rules in the wafer fabrication phase, and allows three-dimensional arrays of internal components such as transistors and capacitors to be used within a limited wafer area. There is a way to increase the degree of integration by inserting electronic circuitry. On the other hand, in the package manufacturing step, there is a method in which a plurality of semiconductor chips are mounted in one semiconductor package by vertically stacking semiconductor chips to increase the overall integration degree. As such, the method of increasing the density of semiconductor devices through semiconductor package manufacturing technology has many advantages in terms of overall cost, time required for research and development, and feasibility of the process compared to increasing the density at the wafer manufacturing stage. Currently, research on this is being actively conducted.

Also, in the semiconductor package field, a wafer level package (WLP) in which the size of the package is reduced to a chip level, or a system-in-package (SIP) including semiconductor chips performing various functions in a single semiconductor package The need for System In Package is increasing, and in order to implement this, a rerouting or redistribution technique is used.

Conventionally, solder balls are directly attached onto the aluminum pads of the wafer, but due to an increase in the density, the gap between the aluminum pads becomes dense and shorts between neighboring solder balls may occur. Also, as described above, for example, as chips are stacked, This is because the pad formed at the center of the chip needs to be extended to the edge. Therefore, it is necessary to rewire the connection terminal to the outside, that is, the position where the solder ball is attached by metal wiring. Briefly describing such a rewiring, a metal wiring is formed in a region where the pattern density is scarce while contacting the aluminum pad on the wafer on which the chip is formed to connect to the outside.

1A to 1C are cross-sectional views illustrating a conventional redistribution method in a process order.

Referring to FIG. 1A, a passivation layer 13 and a first interlayer insulating layer 20 are formed on a substrate 10. Partial regions of the passivation layer 13 and the first interlayer insulating layer 20 are patterned to expose the electrode pads 11 included in the substrate 10.

Referring to FIG. 1B, the seed metal layer 30 is formed on the first interlayer insulating layer 20. Next, a photoresist pattern (not shown) defining a redistribution metal layer is formed on the seed metal layer 30. The redistribution metal layer 40 is formed on the seed metal layer 30 using the photoresist pattern (not shown) as a mask. The redistribution metal layer 40 is generally formed by electroplating or sputtering.

Referring to FIG. 1C, the seed metal layer 30 in the region not covered by the redistribution metal layer 40 is removed using the redistribution metal layer 40 as a mask. Subsequently, the second interlayer insulating layer 50 is formed on the redistribution metal layer 40 and patterned so that the upper portion of the redistribution metal layer 40 is exposed at the portion where the connection electrode is to be formed to complete the redistribution pattern. Although not shown, an external connection terminal such as a solder ball (not shown) is attached to the opening 50 in which the redistribution metal layer 40 is exposed to complete the redistribution process.

Such a prior art has to go through an interlayer insulating layer forming process, a photo process, a seed metal layer forming process, and an electroplating process for forming redistribution, so that the process is complicated, and thus, a defective rate may be increased. In particular, since the seed metal layer generally includes copper, it is difficult to remove the seed metal layer.

An object of the present invention is to provide a method for forming a redistribution pattern of a semiconductor package which can form a redistribution pattern without using a seed metal layer.

According to another aspect of the present invention, there is provided a method for forming a redistribution pattern of a semiconductor package, the method including: providing a semiconductor substrate on which electrode pads are formed; Forming a first interlayer insulating layer including a first opening exposing a portion of the electrode pad; Forming an adhesive layer on the first interlayer insulating layer; Activating a portion of the adhesive layer using a laser; Forming a redistribution layer on the activated adhesive layer; And forming a second interlayer insulating layer including a second opening exposing a portion of the redistribution layer, wherein the forming of the redistribution layer uses electroless plating.

In some embodiments of the present disclosure, after forming the second interlayer insulating layer, the method may further include forming an external connection terminal in the second opening. After forming the external connection terminal, the method may further include forming a third interlayer insulating layer exposing an upper portion of the connection terminal on the external connection terminal.

In some embodiments of the present invention, the adhesive layer may include an insulator. The laser is helium-neon laser, argon ion laser, krypton ion laser, helium-cadmium ion laser, carbon dioxide laser, excimer laser, ND: YAG laser, ND: glass laser, ND: YLF laser, semiconductor laser, diode pump laser, One or more selected from the group consisting of organic dye lasers, chemical lasers, free electron lasers, X-ray lasers, and variable wavelength lasers.

In some embodiments of the present disclosure, forming the first interlayer insulating layer may further include forming a passivation layer exposing a portion of the electrode pad.

In some embodiments of the present invention, the redistribution layer is a group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti,) and gold (Au) It may include one or more selected from. In addition, the first to third interlayer insulating layers may include one or more selected from the group consisting of polyimide, polybenzooxazole, benzocyclobutene, and epoxy. have.

In the method of forming the redistribution pattern of the semiconductor package of the present invention, unlike the method of forming the redistribution pattern by using the conventional electroplating, the seed metal layer is not used, and thus, a process of increasing, exposing, etching and the like for forming the seed metal layer is performed. Since can be omitted, the process can be simplified. In addition, since the metal layer is formed by electroless plating on the activated region using a laser, it is possible to facilitate the formation of a uniform and fine pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art, and the following examples can be modified in various other forms, and the scope of the present invention is It is not limited to an Example. In the following description, when a layer is described as being on top of another layer, it may be directly on top of another layer, and a third layer may be interposed therebetween. In addition, the thickness or size of each layer in the drawings is exaggerated for convenience and clarity, the same reference numerals in the drawings refer to the same elements.

Although the terms first, second, etc. are used herein to describe various members, parts, regions, layers, and / or parts, these members, parts, regions, layers, and / or parts are defined by these terms. It is obvious that not. These terms are only used to distinguish one member, part, region, layer or portion from another region, layer or portion. Thus, the first member, part, region, layer or portion, which will be discussed below, may refer to the second member, component, region, layer or portion without departing from the teachings of the present invention.

2A to 2F are cross-sectional views illustrating a method of forming a redistribution method according to an embodiment of the present invention.

Referring to FIG. 2A, an electrode pad 102 electrically connected to the electric circuit is formed on a semiconductor substrate 100 on which an electric circuit (not shown) is formed. The electrode pad 102 may be an aluminum (Al) layer or a copper (Cu) layer. The semiconductor substrate 100 includes a plurality of unit chips separated from each other by a scribe lane, and the electrode pads 102 are formed on the respective unit chips. Subsequently, a passivation layer 110 is formed on the electrode pad 102, and a first interlayer insulating layer 120 is formed on the passivation layer 110. The passivation layer 110 may be a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or multiple layers thereof. The first interlayer insulating layer 120 is photosensitive and may include one or more selected from the group consisting of polyimide, polybenzooxazole, benzocyclobutene, and epoxy. Can be. However, this is exemplary and is not necessarily limited thereto. In addition, the formation of the passivation layer 110 may be omitted, and the first interlayer insulating layer 120 may be directly formed on the substrate. The first interlayer insulating layer 120 and the passivation layer 110 are patterned to form a first opening 125 that exposes the electrode pad 102. Formation of the first opening 125 may use a conventional photo process.

Referring to FIG. 2B, an adhesive layer 130 is formed on the first interlayer insulating layer 120. The adhesive layer 130 may be formed by a printing method or may be formed by a spin coating method. However, this is exemplary and is not necessarily limited thereto. The adhesive layer 130 may include an insulator, and in this case, the adhesive layer 130 should not be formed on the electrode pad 102 for electrical connection with the redistribution layer 140 formed later.

Referring to FIG. 2C, some regions of the adhesive layer 130 are turned into activated adhesive layers 132 activated by laser irradiation in a subsequent process. In particular, the adhesive layer 130 formed on the side of the first opening 125 should also be activated. Arrows shown in FIG. 2C indicate laser irradiation. These laser irradiations include helium-neon lasers, argon ion lasers, krypton ion lasers, helium-cadmium ion lasers, carbon dioxide lasers, excimer lasers, ND: YAG lasers, ND: glass lasers, ND: YLF lasers, semiconductor lasers, and diode pump lasers. And an organic dye laser, a chemical laser, a free electron laser, an X-ray laser, and a laser including one or more selected from the group consisting of a variable wavelength laser. However, this is exemplary and is not necessarily limited thereto. Regarding the laser device and method used in the above step, methods known in the art can be used.

Referring to FIG. 2D, the redistribution layer 140 is formed on the activated adhesive layer 132 by using electroless plating. The redistribution layer 140 is connected to the electrode pad 102 to electrically extend the electrode pad 102 along the redistribution layer 140. The redistribution layer 140 is also formed on the activated adhesive layer 132 formed on the side of the first opening 120.

The electroless plating is a kind of chemical plating, and is a plating method that does not use electric energy, such as electroplating. The electroless plating is a method of chemically reducing metal ions in an aqueous metal salt solution to precipitate on the surface of the plated body. Electroless plating can be performed by: 1) catalyzing a non-conductive object such as plastic or ceramics other than metal, and 2) uniformly thickening of an object having a complex shape. Uniform plating is possible inside the openings and the like. In addition, 3) it is possible to reduce the formation of pinholes that are not plated, 4) to form a unique functional plating film such as magnetic or amorphous, 5) the plating equipment is simple and easy to control the plating conditions There is an advantage. Therefore, the adhesive layer 132 activated by the laser is plated with a conductive material, for example a metal, whereas the metal layer is not plated with the non-activated adhesive layer 131, and as a result, a redistribution layer having a redistribution pattern ( 140 is formed. The material of the redistribution layer 140 varies depending on the type of metal in the metal salt aqueous solution used when performing the electroless plating of this step. The redistribution layer 140 is one or more selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti,) and gold (Au) It may include. In addition, the redistribution layer 140 may be formed of multiple layers of the above materials. In general, metals commonly used in electroless plating are copper or nickel, and they have low cost and good adhesion and corrosion resistance. However, the conductive materials forming the redistribution layer 140 described above are exemplary, but are not necessarily limited thereto.

Referring to FIG. 2E, a second interlayer insulating layer 150 is formed on the substrate 100 including the unactivated adhesive layer 131 and the redistribution layer 140. The second interlayer insulating layer 150 may include one or more selected from the group consisting of polyimide, polybenzoxazole, benzocyclobutene, and epoxy. However, this is exemplary and is not necessarily limited thereto. Subsequently, the second interlayer insulating layer 140 is patterned to form a second opening 155 to which a portion of the redistribution layer 140, that is, the external connection terminal 160 is attached, in a later process. The second opening 155 may be formed using a conventional photo process.

Referring to FIG. 2F, an external connection terminal 160 electrically connected to the redistribution layer 140 in the second opening 155 is formed. The external connection terminal 160 may be, for example, a bump, a solder ball, or a bonding wire, and the external connection terminal 160 may include gold, silver, copper, tin, or nickel. Can be. In addition, a normal reflow process may be performed to improve electrical connection between the redistribution layer 140 and the external connection terminal 160.

Referring to FIG. 2G, a third interlayer insulating layer 170 is formed on the external connection terminal 160 to selectively expose an upper portion of the external connection terminal 160. The third interlayer insulating layer 170 may include one or more selected from the group consisting of polyimide, polybenzoxazole, benzocyclobutene, and epoxy. However, this is exemplary and is not necessarily limited thereto. The third interlayer insulating layer 170 may serve as a buffer for supporting the external connection terminal 160 and protecting it from external shock.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope not departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1A to 1C are cross-sectional views illustrating a conventional redistribution method in a process order.

2A to 2G are cross-sectional views illustrating a method of forming a redistribution method according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: substrate 102: electrode pad

110: passivation layer 120: first interlayer insulating layer

130, 132: adhesive layer 140: redistribution layer

150: second interlayer insulating layer 160: external connection terminal

170: third interlayer insulating layer

Claims (10)

Providing a semiconductor substrate having electrode pads formed thereon; Forming a first interlayer insulating layer including a first opening exposing a portion of the electrode pad; Forming an adhesive layer on the first interlayer insulating layer; Activating a portion of the adhesive layer using a laser; Forming a redistribution layer on the activated adhesive layer; And Forming a second interlayer insulating layer including a second opening that exposes a portion of the redistribution layer, Forming the redistribution layer is a method for forming a redistribution pattern of a semiconductor package, characterized in that using electroless plating. The method of claim 1, wherein after forming the second interlayer insulating layer, And forming an external connection terminal in the second opening. The method of claim 2, wherein after forming the external connection terminal, And forming a third interlayer insulating layer exposing an upper portion of the connection terminal on the external connection terminal. The method of claim 1, wherein the adhesive layer comprises an insulator. The laser of claim 1, wherein the laser is a helium-neon laser, an argon ion laser, a krypton ion laser, a helium-cadmium ion laser, a carbon dioxide laser, an excimer laser, an ND: YAG laser, an ND: glass laser, an ND: YLF laser, or a semiconductor. Method for forming a redistribution pattern of a semiconductor package comprising one or more selected from the group consisting of a laser, a diode pump laser, an organic dye laser, a chemical laser, a free electron laser, an X-ray laser, and a variable wavelength laser. . The method of claim 1, wherein the forming of the first interlayer insulating layer comprises: And forming a passivation layer exposing a portion of the electrode pads. According to claim 1, wherein the redistribution layer is selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti,) and gold (Au) Method for forming a redistribution pattern of a semiconductor package comprising one or more. The method of claim 1, wherein the first interlayer insulating layer comprises one or more selected from the group consisting of polyimide, polybenzooxazole, benzocyclobutene and epoxy. Method for forming a redistribution pattern of a semiconductor package, characterized in that. 2. The redistribution pattern formation of claim 1, wherein the second interlayer insulating layer comprises one or more selected from the group consisting of polyimide, polybenzoxazole, or benzocyclobutene and epoxy. Way. 4. The redistribution pattern formation of claim 3, wherein the third interlayer insulating layer comprises one or more selected from the group consisting of polyimide, polybenzoxazole, or benzocyclobutene and epoxy. Way.
KR1020070114961A 2007-11-12 2007-11-12 Method of forming wire rerouting pattern for semiconductor packages KR20090048879A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101930958A (en) * 2010-07-08 2010-12-29 日月光半导体制造股份有限公司 Semiconductor packaging element and production method thereof
CN110323130A (en) * 2019-07-12 2019-10-11 吉林大学 A kind of chromium doped black silicon material and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101930958A (en) * 2010-07-08 2010-12-29 日月光半导体制造股份有限公司 Semiconductor packaging element and production method thereof
CN110323130A (en) * 2019-07-12 2019-10-11 吉林大学 A kind of chromium doped black silicon material and preparation method thereof

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