KR20090047155A - Loop filter, phase locked loop and method of operating loop filter determining an amplitude of controlled voltage randomly - Google Patents

Abstract

A loop filter, a phase locked loop, and a method of operating a loop filter for randomly determining the amplitude of a control voltage are disclosed. The loop filter according to the present invention includes a timing adjustment clock generator and a variable capacitor unit. The timing adjustment clock generator generates a timing adjustment clock that is randomly determined whether the first logic state appears. The variable capacitor unit is charged by the input current, and the capacitance changes according to the logic state of the timing adjustment clock.

Description

Loop filter, phase locked loop and method of operating loop filter determining an amplitude of controlled voltage randomly}

The present invention relates to a loop filter, and more particularly, to a loop filter for randomly determining the amplitude of a control voltage.

When generating a clock in a phase locked loop or the like, ripple may occur. This ripple has the problem of causing a reference spur. In addition, the frequency peak of the generated clock may be high. In this case, there is a problem that the bandwidth limitation is reduced.

An object of the present invention is to provide a loop filter for randomly determining the amplitude of a control voltage.

A loop filter according to the present invention for achieving the above technical problem includes a timing adjusting clock generator and a variable capacitor unit. The timing adjustment clock generator generates a timing adjustment clock that is randomly determined whether the first logic state appears. The variable capacitor unit is charged by the input current, and the capacitance changes according to the logic state of the timing adjustment clock.

The timing adjustment clock generation unit may randomly determine whether the first logic state of the timing adjustment clock is to appear at every cycle of the timing adjustment clock.

The timing adjustment clock generator may further include a random number generator for generating a random value, and may randomly determine whether the timing adjustment clock has a first logical state according to the random value. The random number generator may be a pseudo random bit sequence (PRBS) generator.

The variable capacitor unit may include a switch controlled in response to a logic state of the timing adjustment clock; A first capacitor connected in series with the switch and charged by an input current when the switch is turned on; And a second capacitor connected in parallel to the switch and the first capacitor and charged by the input current.

A phase locked loop according to the present invention comprises: a phase-frequency detector for comparing a phase or frequency of a reference clock and a feedback clock; A charge pump generating a charge pump current corresponding to the comparison result; A loop filter for changing a control voltage according to the charge pump current; And a voltage-controlled oscillator (VCO) for generating the feedback clock corresponding to the control voltage. The loop filter may include a timing adjustment clock generator configured to generate a timing adjustment clock that is randomly determined whether a logic state is to be transitioned; And a variable capacitor unit which is charged by an input current and whose capacitance changes according to the logic state of the timing adjustment clock.

A method of operating a loop filter according to the present invention is a method of operating a loop filter including a first capacitor and a second capacitor. In a method of operating a loop filter according to the present invention, at every cycle of a timing adjusting clock, randomly determining whether the timing adjusting clock has only a first logical state or both a first logical state and a second logical state. ; Charging only the second capacitor with charge supplied by an input current in a period in which the timing adjustment clock has a first logic state; And charging the charge supplied by the input current to the first capacitor and the second capacitor together in a period in which the timing adjustment clock has a second logic state.

The loop filter according to the present invention according to the present invention can randomly determine the amplitude of the control voltage. Accordingly, there is an advantage that can reduce the reference spur (frequency spur) and the frequency peak.

In addition, the loop filter according to the present invention has an advantage that the reference spur and the frequency peak can be effectively lowered with only a simple circuit configuration without having a complicated circuit configuration.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram of a phase locked loop (PLL).

Referring to FIG. 1, the phase locked loop includes a phase-frequency detector 110, a charge pump 130, a loop filter 200, and a voltage-controlled oscillator 190.

The phase-frequency detector 110 compares the phase or frequency of the reference clock RCLK and the feedback clock FCLK and outputs a comparison result. For example, when the phase of the reference clock RCLK is faster than the phase of the feedback clock FCLK, the up signal UP is output, and when the phase of the reference clock RCLK is slower than the phase of the feedback clock FCLK, the signal is down. Signal DN can be output. Further, when the phase of the reference clock RCLK is faster than the phase of the feedback clock FCLK, the down signal DN is output, and when the phase of the reference clock RCLK is slower than the phase of the feedback clock FCLK, the up signal ( UP) can also be output. The charge pump 130 outputs a charge pump current ICP corresponding to the comparison results UP and DN. For example, the charge pump CP supplies the charge pump current ICP to the loop filter 200 when the up signal UP is received, and the loop filter 200 when the down signal DN is received. ), The charge pump current ICP can flow out. The loop filter 200 changes the control voltage V CTRL according to the charge pump current ICP. The voltage-controlled oscillator 190 generates a feedback clock FCLK corresponding to the control voltage VCTRL. The generated feedback clock FCLK is fed back to the phase-frequency detector 110. Through this operation, the phase locked loop matches the phase or frequency of the feedback clock FCLK and the reference clock RCLK.

2 (a) is a diagram illustrating a loop filter according to the present invention.

Hereinafter, although the loop filter according to the present invention has been described as being included in the phase locked loop of FIG. 1, the loop filter according to the present invention may not only be used as the loop filter of the phase locked loop of FIG. 1 but also included in another circuit. It can also be used as a loop filter.

Referring to FIG. 2A, a loop filter according to the present invention includes a timing adjusting clock generator 250 and a variable capacitor unit 270. For convenience of description, the phase-frequency detector 110 and the charge pump 130 are shown together in FIG.

The variable capacitor unit 270 is charged or discharged by the charge pump current ICP. If the charge pump current ICP flows from the charge pump 130 to the variable capacitor unit 270 while the up signal UP is being received, the variable capacitor unit 270 is charged and thus the amount of charge of the variable capacitor unit 270. Increases. On the contrary, when the charge pump current ICP flows from the variable capacitor unit 270 to the charge pump 130 while the down signal DN is received, the charges charged in the variable capacitor unit 270 are discharged and thus the variable capacitor unit is discharged. The amount of charge at 270 is reduced.

According to the magnitude of the charge pump current ICP, the amount of charge and the amount of charge discharged to the variable capacitor unit 270 during the unit time are determined. When the size of the charge pump current ICP increases, the charge amount and the discharge amount of the variable capacitor unit 270 increase during the unit time, and when the size of the charge pump current ICP decreases, the charge amount of the variable capacitor unit 270 during the unit time increases. The amount of over discharge becomes small. In addition, the amount of charge charged and the amount of charge discharged to the variable capacitor unit 270 is determined according to the time when the charge pump current ICP flows into or out of the variable capacitor unit 270. As the inflow time or outflow time of the charge pump current ICP increases, the charge amount and discharge amount of the variable capacitor unit 270 increase, and as the inflow time or outflow time of the charge pump current ICP shortens, the variable capacitor unit 270 ) The amount of charge and discharge decreases.

In the present specification, the loop filter according to the present invention has been described as being included in the phase locked loop, and the variable capacitor unit 270 has been described as exchanging the charge pump 130 with the charge pump current ICP. In addition, however, the loop filter according to the present invention may not be included only in the phase locked loop. In this case, the variable capacitor unit 270 may exchange current with other components other than the charge pump 130.

The control voltage VCTRL is determined according to the charge amount of the variable capacitor unit 270. As the amount of charge of the variable capacitor unit 270 increases, the control voltage VCTRL increases, and when the amount of charge of the variable capacitor unit 270 decreases, the control voltage VCTRL decreases. As described above, the charge amount of the variable capacitor unit 270 depends on whether the charge pump current ICP is inflow / outflow, the magnitude of the charge pump current ICP, and the inflow or outflow time of the charge pump current ICP. Different. Therefore, the control voltage V CTRL also varies with the above conditions. For example, when the up signal UP is received and the charge pump current ICP flows into the variable capacitor unit 270, the control voltage VCTRL becomes high, and the down signal DN is received to charge the charge pump current ICP. Is discharged from the variable capacitor unit 270, the control voltage (VCTRL) is lowered. In this manner, the loop filter may adjust the magnitude of the control voltage VCTRL by adjusting the amount of charge of the variable capacitor unit 270.

In the loop filter according to the present invention, the capacitance of the variable capacitor unit 270 may vary. When the capacitance of the variable capacitor unit 270 is changed, the magnitude of the voltage across the variable capacitor unit 270 is varied without the inflow / outflow of the charge pump current ICP (no change in the amount of charge). Here, since the voltage applied to the variable capacitor unit 270 is the control voltage VCTRL, when the capacitance of the variable capacitor unit 270 is changed, the magnitude of the control voltage VCTRL also changes. For example, in a situation where there is no inflow / outflow of the charge pump current ICP, when the capacitance of the variable capacitor unit 270 transitions from a low state to a high state, the control voltage VCTRL is low and the variable capacitor unit 270 is ), The control voltage (VCTRL) is high when the capacitance of the transition from the high state to the low state. In addition, when the capacitance of the variable capacitor unit 270 remains low for a predetermined time and then transitions to a high state, the control voltage VCTRL becomes high during the time that the capacitance of the variable capacitor unit 270 remains low. Keep your level. When the capacitance of the variable capacitor unit 270 transitions to a high state, the level of the control voltage VCTRL is lowered. Of course, it is also possible that the capacitance of the variable capacitor unit 270 is kept high and then transitioned to a low state. In this case, the control voltage VCTRL maintains a low level and then transitions to a high level.

In the loop filter according to the present invention, whether the capacitance of the variable capacitor unit 270 has a high value or a low value is randomly determined. For example, it is possible to randomly determine whether to keep the capacitance of the variable capacitor unit 270 high or to transition from high to low. That is, a section in which the capacitance of the capacitor unit 270 is kept high and a section in which the capacitance of the capacitor unit 270 is kept low may be randomly displayed.

On the other hand, the control voltage VTRL rises slowly in the period where the capacitance of the capacitor unit 270 is high, and the control voltage VCTRL rises rapidly in the period where the capacitance of the capacitor unit 270 is low. Therefore, when the section with the high capacitance and the section with the low capacitance of the capacitor unit 270 are randomly selected, whether the control voltage VCTRL rises quickly or slowly rises is randomly determined. In the sections P1 and P4 of FIG. 3, the control voltage VCTRL rises quickly (A1 and A2), and in the sections P2 and P3, the control voltage VCTRL rises slowly (B1 and B2). It is randomly determined whether the control voltage VCTRL has a form such as A1 or A2 or a form like B1 or B2. That is, in the situation where the same charge pump current ICP is inflow / outflow, it is randomly determined whether the amplitude of the control voltage VCTRL is high or low. Accordingly, the reference spurs can be distributed to various frequency bands in the frequency domain. Accordingly, the reference spur level can be lowered.

On the other hand, assuming that the capacitance of the variable capacitor unit 270 is constant, the amplitude of the control voltage V CTRL is also constant, so that the reference spur level is not lowered.

The timing adjustment clock generator 250 generates a timing adjustment clock DCCLK that is randomly determined whether a first logical state (eg, a logic low state) is to appear. 3 shows a logic low state of the timing adjustment clock DCCLK in the sections P1 and P4 and a logic low state of the timing adjustment clock DCCLK in the sections P2 and P3. The timing adjustment clock DCCLK may be used to vary the capacitance of the variable capacitor unit 270.

The timing adjustment clock generator 250 may randomly determine whether the first logic state of the timing adjustment clock DCCLK is to appear at every cycle of the timing adjustment clock DCCLK. For example, the timing adjustment clock generator 250 may randomly determine whether or not the logic low state of the timing adjustment clock DCCLK is to appear at every cycle of the timing adjustment clock DCCLK. 3 illustrates an example in which the sections P1 and P4 having the logic low state and the sections P2 and P3 having the logic high state are randomly shown.

The timing adjustment clock generator 250 may generate the timing adjustment clock DCCLK using the feedback clock FCLK or the reference clock RCLK. For example, referring to FIG. 3, the timing adjustment clock generator 250 inverts the feedback clock FCLK in the P1 and P4 sections to generate the timing adjustment clock DCCLK, and generates the feedback clock FCFC in the P2 and P3 sections. Generates a timing adjustment clock DCCLK. That is, while the logic high period of the feedback clock FCLK appears every cycle, the timing adjustment clock DCCLK corresponding to the logic high period of the feedback clock FCLK has two periods P1 and P4. Appears only on

In this case, the period of the timing adjustment clock DCCLK may be the same as the period of the feedback clock FCLK (or the period of the reference clock RCLK). That is, the timing adjustment clock is maintained by randomly changing the logic state of the feedback clock FCLK (or the reference clock RCLK) while maintaining the period of the feedback clock FCLK (or the cycle of the reference clock RCLK) as it is. (DCCLK) can be generated.

The capacitance of the variable capacitor unit 270 may vary according to the logic state of the timing adjustment clock DCCLK. In the second logical state section of the timing adjustment clock DCCLK (eg, the logic high period), the capacitance of the variable capacitor unit 270 may be increased, and the first logical state section of the timing adjustment clock DCCLK (eg For example, the capacitance of the variable capacitor unit 270 may be reduced in a logic low period. In this case, the control voltage VCTRL may be slowly increased in the second logical state section of the timing adjustment clock DCCLK (eg, the logic high period), and the first logical state section of the timing adjustment clock DCCLK may be increased. For example, the control voltage VCTRL may be quickly increased in the logic low period.

In addition, by randomly determining a section in which the first logic state and the second logic state of the timing adjustment clock DCCLK appear, a section with a high capacitance and a section with a low capacitance of the variable capacitor unit 270 may appear at random. Accordingly, the reference spur can be lowered.

However, although the capacitance of the variable capacitor unit 270 increases in the logic high period of the timing adjustment clock DCCLK, the capacitance of the variable capacitor unit 270 increases in the logic low period of the timing adjustment clock DCCLK. Could be In the above description, the capacitance of the variable capacitor unit 270 is changed by using the transition of the logic state of the timing adjustment clock DCCLK. However, the capacitance of the variable capacitor unit 270 may be changed using other means. For example, a section having a high capacitance and a section having a low capacitance of the variable capacitor unit 270 may be randomly displayed according to a control signal received from the outside. Therefore, the present invention does not necessarily have to include the timing adjustment clock generator 250.

The variable capacitor unit 270 may include a switch SW, a first capacitor CI, and a second capacitor CP.

The switch SW is turned on or off by the timing adjustment clock DCCLK. For example, the switch SW may be turned on in an activation period of the timing adjustment clock DCCLK and may be turned off in an inactivation period of the timing adjustment clock DCCLK. Of course, the switch SW is turned off in the activation period of the timing adjustment clock DCCLK and may be turned on in the inactivation period of the timing adjustment clock DCCLK.

Depending on whether the switch SW is on or off, the total capacitance of the variable capacitor unit 270 varies. Specifically, when the switch SW is turned on, the first capacitor CI and the second capacitor CP are connected in parallel. Accordingly, the capacitance of the variable capacitor unit 270 is the sum of the capacitance of the first capacitor CI and the capacitance of the second capacitor CP. On the contrary, when the switch SW is turned off, the first capacitor CI is not connected to the node where the charge pump 130 and the control voltage V CTRL are generated. That is, when the switch SW is turned off, the variable capacitor unit 270 has the same effect as having only the second capacitor CP. Accordingly, the total capacitance of the variable capacitor unit 270 becomes equal to the capacitance of the second capacitor CP. That is, when the switch SW is turned on, the total capacitance of the variable capacitor unit 270 is increased, and when the switch SW is turned off, the total capacitance of the variable capacitor unit 270 is decreased.

FIG. 3 is a timing diagram for describing an operation of the loop filter of FIG. 2.

Hereinafter, the operation of the loop filter according to the present invention will be described with reference to FIGS. 2A and 3.

The down signal DN is received after the up signal UP is received in the P1 section of FIG. 3. The charge pump current ICP flows from the charge pump 130 to the loop filter while the up signal UP is received, and the charge pump current from the loop filter to the charge pump 130 while the down signal DN is received. (ICP) leaks. On the other hand, when the timing adjustment clock DCCLK transitions to the logic low level (first logic level) in the P1 section, the switch SW is turned off. Therefore, the second capacitor CP is charged by the charge pump current ICP while the up signal UP is received, and then the second capacitor CP is discharged while the down signal DN is received thereafter. . On the other hand, since the switch SW is turned off in the P1 section, the first capacitor CI is not charged / discharged.

Since the first capacitor CI is not charged while the second capacitor CP is charged by the charge pump current ICP introduced according to the up signal UP, the first capacitor CI and the second capacitor are not charged. The level of the control voltage V CTRL rises faster than when all the CPs are charged. In addition, since the second capacitor CP is discharged by the charge pump current ICP flowing out according to the down signal DN, while the first capacitor CI is not charged, the first capacitor CI and the first capacitor CI are discharged. The level of the control voltage V CTRL drops faster than when both the capacitors CP are discharged. Accordingly, the control voltage V CTRL has the form of A1 in FIG. 3.

Next, in the P2 section in FIG. 3, the timing adjustment clock DCCLK has a logic high level (second logical level). Accordingly, the switch SW is turned on. Therefore, the first capacitor CI and the second capacitor CP are charged by the charge pump current ICP while the up signal UP is received, and thereafter the first capacitor CI is received while the down signal DN is received. The capacitor CI and the second capacitor CP are discharged.

Since both the first capacitor CI and the second capacitor CP are charged by the charge pump current ICP flowing in according to the up signal UP, the second capacitor CP is controlled more than the case where only the second capacitor CP is charged. The level of the voltage VCTRL rises slowly. In addition, since both the first capacitor CI and the second capacitor CP are discharged by the charge pump current ICP that flows out according to the down signal DN, the control of the second capacitor CP is less than the case where only the second capacitor CP is discharged. The level of the voltage VCTRL decreases slowly. Accordingly, the control voltage V CTRL has the form of B1 in FIG. 3.

3, the amplitude of the up signal UP is shown to be the same as the amplitude of the down signal DN. Accordingly, the amount of charge charged in the second capacitor CP in response to the up signal UP is discharged in response to the down signal DN. However, this operation may vary according to the change of the amplitude of the up signal UP and the down signal DN, and further, may vary according to the time when the up signal UP and the down signal DN are applied. In the above description, the case in which the loop filter receives both the up signal UP and the down signal DN has been described, but the loop filter receives only the up signal UP without receiving the down signal DN. The same may be applied to the case where only the down signal DN is received without receiving the signal UP.

The loop filter according to the present invention randomly determines a section in which the first logic state and the second logic state of the timing adjustment clock DCCLK appear, so that a section having a high capacitance and a section having a low capacitance are randomly selected. You can make it appear. Accordingly, the reference spur can be lowered. On the other hand, the loop filter according to the present invention need only be provided with a variable capacitor unit to perform the above process. Therefore, the loop filter according to the present invention can effectively reduce the reference spurs without having a complicated circuit configuration.

In the above description, an example in which the variable capacitor unit 270 is implemented by a switch SW, a first capacitor CI, and a second capacitor CP has been described, but the variable capacitor unit 270 of the loop filter 200 according to the present invention is described. ) May not be implemented as described above. That is, those skilled in the art will be able to implement the variable capacitor unit according to the present invention in another manner so that the capacitance of the variable capacitor unit 270 can be changed according to the logic state of the timing adjustment clock DCCLK with reference to the above description. .

In this case, the variable capacitor unit 270 is charged in the section where the up signal UP is received, and accordingly, the control voltage V CTR is increased. Next, the charging of the variable capacitor unit 270 is stopped in the period in which the up signal UP is not received, and thus the control voltage VCTRL is maintained as it is. Next, when the timing adjustment clock DCCLK transitions to logic high, the capacitance of the variable capacitor unit 270 has a value larger than the capacitance in the section where the timing adjustment clock DCCLK is logic low. Thus, even if the charge pump current ICP does not flow in, i.e., even if the charge amount does not change, the control voltage VCTRL is lowered.

2B is a diagram illustrating an example of the timing adjustment clock generator 250 of the loop filter.

The timing adjustment clock generator 250 of FIG. 2B may include a random number generator 252 and a logic operator 254. The random number generator 260 generates a random value RNUM that is randomly generated. The random number generator 260 may be a pseudo random bit sequence (PRBS) generator 260.

The logic calculator 254 logically operates the logic state of the random value RNUM and the reference clock RCLK to generate the timing adjustment clock DCCLK. For example, the logic operator 254 may NAND the random value RNUM and the reference clock RCLK to generate the timing adjustment clock DCCLK illustrated in FIG. 3. Of course, those skilled in the art will appreciate that the NAND logic operation is merely an example, and the timing adjustment clock DCCLK shown in FIG. 3 may be generated through other types of logic operations.

Meanwhile, although an example of generating the timing adjustment clock DCCLK using the reference clock RCLK is illustrated in FIG. 2B, the timing adjustment clock DCCLK may be generated using the feedback clock RCLK.

In FIG. 2B, the random number generator 252 is illustrated as being included in the timing adjustment clock generator 250. However, the random number generator 252 may be separately provided outside the timing adjustment clock generator 250. have.

4 is a view showing a loop filter according to a first comparative example for comparison with the present invention. In FIG. 4, the charge pump 130 is shown together for convenience of description.

The loop filter 400 of FIG. 4 includes a resistor R and two capacitors CI and CSHUNT. Compared to the loop filter according to the present invention illustrated in FIG. 2, the loop filter 400 according to the first comparative example illustrated in FIG. 4 includes a resistor R instead of the switch SW. In addition, in FIG. 4, the capacitance is not varied.

FIG. 5A is a timing diagram for describing an operation of the loop filter of FIG. 4.

Referring to FIG. 5A, the charge pump current ICP flows into the loop filter 400 while the up signal UP is received. The charge pump current ICP applies a voltage VPROP to the resistor R and charges the capacitor CI. Accordingly, while the up signal UP is received, the control voltage VCTRL becomes a voltage obtained by adding the voltage VPROP applied to the resistor R and the voltage VINT of the capacitor CI. Here, while the up signal UP is received, the voltage of the capacitor CI is increased in proportion to the capacitance of the capacitor CI. Next, when the reception of the up signal UP is stopped, the voltage of the resistor R is no longer applied, and the amount of charge charged in the capacitor CI is maintained. As a result, the control voltage VCTRL becomes the voltage VINT of the capacitor CI.

As described above, in the loop filter of FIG. 4, there is a problem that the high voltage VPROP is applied to the resistor R while the up signal UP is received. This phenomenon is called a reference spur. On the other hand, referring to FIG. 3, in the loop filter according to the present invention, the charge amount of the charge pump current ICP is spread in a section in which the timing adjustment clock DCCLK is inactivated. Therefore, the voltage applied to the loop filter according to the present invention is lower than the voltage applied to the loop filter of FIG. Therefore, the loop filter according to the present invention can reduce the reference spurs.

FIG. 5B is another timing diagram for describing an operation of the loop filter of FIG. 4.

Referring to FIG. 5B, when the loop filter of FIG. 4 receives both the up signal UP and the down signal DN, the process of increasing and decreasing the control voltage VCTRL is repeated. The straight line shown in the second timing diagram of FIG. 5 (b) shows the change of control voltage when the loop filter of FIG. 4 includes only the first capacitor CI, and the curve shows that the loop filter of FIG. The change in the control voltage when both the CI) and the second capacitor CSHUNT are provided is shown. In the case where the loop filter of FIG. 4 includes the second capacitor CSHUNT, the ripple of the control voltage is reduced. However, even in this case, there is still a reference spur phenomenon in which the resistor R has a relatively high voltage.

6 (a) to 6 (c) are diagrams illustrating a loop filter according to a second comparative example for comparison with the present invention. 6 shows a phase-frequency detector PFD and charge pumps CP1 and CP2 together for convenience of description.

FIG. 7 is a timing diagram for describing an operation of the loop filter of FIG. 6.

Referring to FIG. 7, in the loop filter of FIG. 6, the charge amount of the charge pump current ICP flowing in according to the up signal UP is divided and charged in a section in which the up signal UP is not received. Therefore, like the loop filter according to the present invention, the loop filter of FIG. 6 can also reduce the reference spurs. However, as shown in FIGS. 6A-6C, the loop filter of FIG. 6 must have complex circuits. On the other hand, the loop filter according to the present invention only needs to include the variable capacitor unit in order to reduce the reference spurs. Therefore, compared to the loop filter of FIG. 6, the loop filter according to the present invention can effectively reduce a reference spur without having a complicated circuit configuration.

8 is a view showing a loop filter according to a third comparative example for comparison with the present invention. 8 illustrates a phase-frequency detector 110 and a charge pump 130 for convenience of description.

Referring to FIG. 8, the loop filter according to the third comparative example inverts the feedback clock FCLK to generate a delay clock FCLK2 for adjusting the on-off timing of the switch SW. Therefore, the duty ratio of the delay clock FCLK2 is equal to the duty ratio of the feedback clock FCLK.

FIG. 9A is a timing diagram for describing an operation of the loop filter of FIG. 8.

Referring to FIG. 9A, the deactivation period and the activation period of the delay clock FCLK2 are half of the period of the delay clock FCLK2. That is, the deactivation period and the activation period of the delay clock FCLK2 are the same. Accordingly, in the loop filter of FIG. 8, the charge amount of the charge pump current flowing in accordance with the up signal UP is divided and charged during half of the period of the delay clock FCLK2. On the other hand, in the loop filter according to the present invention, the charge amount of the charge pump current is charged while being divided in the deactivation period of the timing adjustment clock. Here, the deactivation interval of the timing adjustment clock is adjusted to be longer than the activation interval.

Therefore, the divided charge time supplied by the current of the charge pump in the loop filter according to the present invention is longer than the charge time supplied by the charge pump current in the loop filter in FIG. 8. Therefore, the loop filter according to the present invention can reduce the reference spur than the loop filter of FIG. 8.

FIG. 9B is another timing diagram for describing an operation of the loop filter of FIG. 8.

FIG. 9B illustrates a situation in which the up signal UP is supplied for a longer time than the half period of the feedback clock FCLK. In this case, the up signal UP is continuously supplied even after the feedback clock FCLK is inactivated. In such a section (t1 and t2), the charge of the charge pump current is divided into the first capacitor CI and the second capacitor CP to be charged, so that the rate of increase of the control voltage VCTRL is lowered. 9 (b) shows a case where the charge of the charge pump current is charged only to the second capacitor CP, and the graph shown by the solid line in FIG. 9 (b) shows that the charge of the charge pump current is the first capacitor. The case where the charge is divided into (CI) and the second capacitor (CP) is shown. As indicated by the dotted line in FIG. 9B, when the rising rate of the control voltage VCTRL is low, the control voltage VCTRL is not proportional to the time when the up signal UP is supplied, and thus the control voltage VCTRL is increased. The UP signal is not properly represented. On the other hand, the loop filter according to the present invention may delay the timing at which the timing adjustment clock DCCLK is activated after the supply of the up signal UP is stopped. Meanwhile, in the loop filter according to the present invention, the charges are charged only to the second capacitor CP before the timing adjustment clock DCCLK is activated, and after the timing adjustment clock DCCLK is activated, the second capacitor CP is charged. Charges that have been charged are shared by the first capacitor CI and the second capacitor CP. Therefore, the loop filter according to the present invention raises the control voltage VCTRL in proportion to the time when the up signal UP is supplied while the up signal UP is supplied, and when the supply of the up signal UP is stopped, the timing is increased. Activate control clock DCCLK to reduce control voltage VCTRL.

10 is a graph illustrating reference spur levels in a loop filter according to the present invention and a loop filter according to a comparative example.

Referring to FIG. 10, it can be seen that the reference spur level of the loop filter according to the present invention is lower than the reference spur level of the loop filters according to the first and third comparative examples.

A method of operating a loop filter according to the present invention relates to a method of operating a loop filter including a first capacitor and a second capacitor. Referring to Figure 2 (b), the operation method of the loop filter according to the present invention will be described.

A method of operating a loop filter according to the present invention includes: randomly determining whether a timing adjusting clock DCCLK has only a first logical state or a second logical state every period of the timing adjusting clock DCCLK; Charging the charge supplied by the input current ICP only to the second capacitor CP in a period in which the timing adjustment clock DCCLK has a first logic state; And charging the first capacitor CI and the second capacitor CP together with the charge supplied by the input current ICP in the period in which the timing adjustment clock DCCLK has the second logical state.

Since the timing adjustment clock DCCLK has only a first logical state or a second logical state is randomly determined, it is determined whether the control voltage VCTRL rises quickly or slowly. That is, in the situation where the same charge pump current ICP is inflow / outflow, it is randomly determined whether the amplitude of the control voltage VCTRL is high or low. Accordingly, the reference spurs can be distributed to various frequency bands in the frequency domain. Accordingly, the reference spur level can be lowered.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a phase locked loop (PLL).

2 (a) is a diagram illustrating a loop filter according to the present invention.

FIG. 2B is a diagram illustrating an example of the timing adjustment clock generator of FIG. 2A.

FIG. 3 is a timing diagram for describing the operation of the loop filter of FIGS. 2A and 2B.

4 is a view showing a loop filter according to a first comparative example for comparison with the present invention.

FIG. 5A is a timing diagram for describing an operation of the loop filter of FIG. 4.

FIG. 5B is another timing diagram for describing an operation of the loop filter of FIG. 4.

6 (a) to 6 (c) are diagrams illustrating a loop filter according to a second comparative example for comparison with the present invention.

FIG. 7 is a timing diagram for describing an operation of the loop filter of FIG. 6.

8 is a view showing a loop filter according to a third comparative example for comparison with the present invention.

FIG. 9A is a timing diagram for describing an operation of the loop filter of FIG. 8.

FIG. 9B is another timing diagram for describing an operation of the loop filter of FIG. 8.

10 is a graph showing reference spur levels in a loop filter according to the present invention and a loop filter according to a comparative example.

Claims (18)

A timing adjustment clock generator for generating a timing adjustment clock that is randomly determined whether a first logical state will appear; And And a variable capacitor unit which is charged by an input current and whose capacitance changes according to the logic state of the timing adjustment clock. The clock generator of claim 1, wherein the timing adjustment clock generator comprises: And at every cycle of the timing adjustment clock, randomly determines whether the first logic state of the timing adjustment clock will appear. The clock generator of claim 2, wherein the timing adjustment clock generator comprises: And at every cycle of the timing adjustment clock, randomly determines whether the timing adjustment clock has only a first logic state or both a first logic state and a second logic state. The method of claim 3, The first logical state is an active state, And the second logic state is in an inactive state. The clock generator of claim 1, wherein the timing adjustment clock generator comprises: It further comprises a random number generator for generating a random value, And randomly determining whether the timing adjustment clock has a first logic state according to the random value. The method of claim 5, wherein the random number generator, And a pseudo random bit sequence (PRBS) generator for generating random values. The method of claim 5, wherein the timing adjustment clock generator, Receive the input clock, In an interval in which the random value has a first logical value, the input clock is inverted and output as the timing adjusting clock. And outputting the timing adjustment clock having a first logic state value in a section in which the random value has a second logic value. The method of claim 7, wherein the timing adjustment clock generator, And a logic calculator configured to logically operate a logic state of the input clock and the random value to generate the timing adjustment clock. The method of claim 7, wherein The loop filter is included in a phase locked loop, And the input clock is a reference clock or a feedback clock of the phase locked loop. The method of claim 1, In the period in which the timing adjustment clock maintains an active state, the capacitance of the variable capacitor unit is low, And a loop transition of the variable capacitor unit from a low state to a high state in a period where the timing adjustment clock transitions to an inactive state. The method of claim 1, wherein the variable capacitor unit, A switch controlled in response to a logic state of the timing adjustment clock; A first capacitor connected in series with the switch and charged by an input current when the switch is turned on; And And a second capacitor connected in parallel to the switch and the first capacitor and charged by the input current. The method of claim 11, wherein the switch, And a loop filter which is turned on in the activation period of the timing adjustment clock and off in the deactivation period of the timing adjustment clock. A phase-frequency detector for comparing the phase or frequency of the reference clock and the feedback clock; A charge pump generating a charge pump current corresponding to the comparison result; A loop filter for changing a control voltage according to the charge pump current; And A voltage-controlled oscillator (VCO) generating the feedback clock corresponding to the control voltage; The loop filter, A timing adjustment clock generator for generating a timing adjustment clock that is randomly determined whether the logic state will transition; And And a variable capacitor unit which is charged by an input current and whose capacitance changes according to the logic state of the timing adjustment clock. The method of claim 13, wherein the variable capacitor unit, A switch controlled by the timing adjustment clock; A first capacitor connected in series with the switch and charged by the charge pump current when the switch is turned on; And And a second capacitor connected in parallel to the switch and the first capacitor and charged by the charge pump current. The method of claim 13, wherein the timing adjustment clock generation unit, And at every cycle of the timing adjustment clock, randomly determines whether the timing adjustment clock has only a first logic state or both a first logic state and a second logic state. In the method of operating a loop filter comprising a first capacitor and a second capacitor, Randomly determining, at every period of the timing adjustment clock, whether the timing adjustment clock has only a first logical state or has both a first logical state and a second logical state; Charging only the second capacitor with charge supplied by an input current in a period in which the timing adjustment clock has a first logic state; And And charging the first capacitor and the second capacitor together with the charge supplied by the input current in a section in which the timing adjustment clock has a second logic state. The method of claim 16, The loop filter is included in a phase locked loop, And inverting the reference clock or feedback clock of the phase locked loop to output the timing adjusting clock or outputting the timing adjusting clock having the first logic state value. The method of claim 17, wherein the input current, And a current generated by a charge pump included in the phase locked loop.

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