KR20090046545A

KR20090046545A - High voltage generator

Info

Publication number: KR20090046545A
Application number: KR1020070112761A
Authority: KR
Inventors: 정상화
Original assignee: 주식회사 하이닉스반도체
Priority date: 2007-11-06
Filing date: 2007-11-06
Publication date: 2009-05-11

Abstract

The high voltage generator of the present invention includes a clock driver for delaying an external clock to generate first and second clock signals having opposite levels, and a charge pump for pumping external power voltages according to the first and second clock signals. In the high voltage generator, when the pumping voltage rises and stabilizes at a predetermined level, the clock voltage is supplied to the clock driver in which the external voltage is reduced.

High Voltage Generator, Clock Driver, External Supply Voltage

Description

High voltage generator

The present invention relates to a high voltage generator for supplying a high voltage used in a semiconductor device.

In a conventional memory, IC chip, etc., there are circuits requiring a voltage higher than the supply voltage. High voltage generators that supply voltages above the supply voltage are in most cases produced using a charge pump, which is driven in accordance with the clock signal generated by the oscillator.

The high voltage generator also requires a regulator to keep the output voltage of the charge pump constant. As a general regulation method, the output voltage of the charge pump is compared with the reference voltage. When the output voltage is lower than the reference voltage, the clock signal is generated by the oscillator to drive the charge pump. I'm using a way to block creation.

However, a high voltage generator using only one regulator may cause ripple in the output voltage. In order to eliminate such ripple, a configuration in which a second regulator for regulating the output voltage of the regulator is added again is widely used.

However, the configuration using two regulators has the problem of increasing the current consumption in the high voltage generator.

In order to solve the various problems of the high voltage generator described above, an object of the present invention is to provide a high voltage generator capable of reducing the external power supply voltage supplied to the clock driver in accordance with the degree of increase in the pumping voltage of the charge pump.

The high voltage generator of the present invention for achieving the above object is a clock driver for delaying an external clock to generate first and second clock signals of opposite levels, and an external power supply voltage according to the first and second clock signals. In the high voltage generator including a charge pump for pumping, when the pumping voltage rises and stabilizes to a predetermined level, it is characterized in that for supplying the converted voltage to reduce the external power supply voltage to the clock driver.

In addition, the high voltage generator of the present invention is a high voltage generator for pumping the external power supply voltage in accordance with the first and second clock signals of mutually opposite levels, when the pumping voltage is stabilized to a predetermined level converted voltage that reduced the external power supply voltage It is characterized in that it comprises a voltage converter for supplying a clock driver to reduce the amplitude of the first and second clock signal.

According to the configuration of the present invention described above it is possible to lower the level of the external power supply voltage supplied to the clock driver according to the degree of rise of the pumping voltage. As the voltage supplied to the clock driver is lowered, the levels of the first and second clock signals output from the clock driver are also lowered, which reduces the ripple of the pumping voltage.

Therefore, it is possible to reduce the ripple of the pumping voltage without adopting a configuration for regulating the output voltage of the first regulator again. As a result, there is an effect of replacing a high voltage generator including two regulation with high current consumption.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and fully scope the scope of the invention to those skilled in the art. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a circuit diagram illustrating a high voltage generator that is commonly used.

The high voltage generator 100 includes an oscillator 110, a clock driver 120, a charge pump 130, a first regulator 140, and a second regulator 150.

The oscillator 110 generates a clock signal CLK1 having a specific frequency and transmits the generated clock signal CLK1 to the clock driver 120.

The clock driver 120 delays the clock signal CLK1 according to the output signal of the first comparator 142 included in the first regulator to output two clock signals CLK2 and CLK2b having opposite levels. To this end, it includes a first inverter group in which n inverters are connected in series, and a second inverter group in which n + 1 inverters are connected in series (not shown). At this time, each inverter group is supplied with a VDD voltage.

The charge pump 130 performs a pumping operation according to two clock signals CLK2 and CLK2b having different levels output from the clock driver 120 to output a predetermined pumping voltage VPP.

The first regulator 140 stabilizes the pumping voltage to a voltage of a predetermined level to supply a first regulation voltage.

The first regulator 140 divides the pumping voltage to output a first divided voltage Vf1, a first voltage divider 144, a first divided voltage Vf1, and a first reference voltage VREF1. Compared to the first control unit includes a first comparator 142 for controlling the operation of the clock driver 120.

The first voltage divider 144 includes a plurality of passive elements R0 and R1 connected in series. The first voltage divider 144 receives the first divided voltage Vf1 input to the first comparator 142 according to a ratio thereof. Output Preferably, the plurality of first and second resistors R0 and R1 are connected in series between the pumping voltage output terminal VPP and ground, and are input to the first comparator 142 according to the ratio of these resistors. The first divided voltage Vf1 is outputted.

The first comparator 142 compares the first reference voltage VREF1 with the first divided voltage Vf1 and outputs a high level signal to the clock driver 120 when the first reference voltage is larger. To this end, the first reference voltage VREF1 is input to the non-inverting terminal (+), and the first divided voltage includes an OP amplifier receiving the inverting terminal (−).

According to this configuration, the value of the final pumping voltage VPP has the following equation, and this voltage becomes the first regulation voltage.

In the case of the first regulator, since the first regulation voltage is output by controlling only the operation of the charge pump, the ripple of the output is severe. In order to eliminate this, a second regulator of a method using a current control method is further configured.

On the other hand, the second regulator 150 converts the first regulation voltage into a voltage of a predetermined level to output the second regulation voltage.

The second regulator 150 includes a second comparator 152, a second voltage divider 154, a current breaker 156, and a voltage supply 158.

The second voltage divider 154 includes a plurality of passive elements R3 and R4 connected in series. The second voltage divider 154 divides the second regulation voltage according to a ratio thereof and outputs a second divided voltage Vf2. Preferably, the plurality of third and fourth resistors R3 and R4 are connected in series between the output terminal VREG and ground, and are input to the second comparator 152 according to the ratio of the resistors. 2 Output the divided voltage Vf2. At this time, the output voltage VREG is controlled by adjusting the resistance value of the third resistor R3.

The second comparator 152 controls the operation of the current blocking unit 156 by comparing the second divided voltage and the second reference voltage VREF2.

To this end, it includes an OP amplifier that receives the second reference voltage VREF2 as the inverting terminal (−) and receives the second divided voltage as the non-inverting terminal (+).

At this time, by applying the same voltage as the second division voltage Vf2 as the second reference voltage VREF2, the magnitude of the second division voltage and the second reference voltage actually input are compared. Therefore, according to the comparison result, a high level voltage is output when the second division voltage is greater than the second reference voltage, and a low level voltage is output when the second division voltage is less than the second reference voltage.

On the other hand, the current blocking unit 156 forms a current path between the output terminal and the ground terminal of the first regulator. To this end, it includes an NMOS transistor (N156) is turned on in response to the output voltage of the second comparator. The NMOS transistor N156 is connected between the voltage supply unit 158 and ground, and is turned on in response to a high level signal to form a current path from the charge pump output terminal to ground. A diode D156 may be further included between the NMOS transistor N156 and the ground to prevent reverse current flow.

Therefore, according to the comparison result of the comparison unit 152, when the second division voltage is greater than the second reference voltage, the high level voltage is output, so that a current path is formed through the current blocking unit 156. At this time, the magnitude of the current flowing through the formed current path becomes larger as the second divided voltage is greater than the second reference voltage. In addition, as the current path is formed, the level of the first regulation voltage VPP is lowered.

On the other hand, when the second division voltage is smaller than the second reference voltage, the low level voltage is output, so that the NMOS transistor N156 is turned off to cut off the current path.

The voltage supply unit 158 supplies or blocks the first regulation voltage VPP to the output terminal VREG of the second regulator depending on whether the current path is formed.

To this end, the voltage supply unit 158 is connected between the resistor R2 connected between the charge pump output terminal VPP and the current interrupting unit 156, the charge pump output terminal and the output terminal VREG of the regulator and the resistor ( And an NMOS transistor N158 to which a voltage of the connection node of R2) and the current interrupting unit 156 is applied as a gate.

When the current path is not formed, the voltage supply unit 158 applies a first regulation voltage directly to the gate of the NMOS transistor N158 to turn on the transistor so that the first regulation voltage is applied to the output terminal VREG of the second regulator. To be supplied).

However, when the current path is formed, the voltage level applied to the gate of the NMOS transistor N158 is low so that the transistor cannot be turned on, so that the first regulation voltage is not supplied to the output terminal VREG of the second regulator.

The voltage VREG output by the configuration of the regulator 150 is as follows.

However, when using the second regulator using the current control method as described above, there is a problem in that the current consumed is increased as compared with the configuration using only the first regulator.

First, as the difference between the pumping voltage VPP output from the first regulator and the voltage VREG output from the second regulator increases, the current value consumed becomes larger.

The first regulation voltage greater than the second regulation voltage must be output for the output of the second regulation voltage. For example, in order to output a second regulation voltage of about 26V, a first regulation voltage of 30V, which is approximately 4V or more, needs to be generated. The current value consumed by the above voltage difference is increased.

As described above, the configuration of outputting a high level pumping voltage increases the number of pump stages included in the charge pump, which increases the overall size.

In addition, the second regulator uses a method of extracting the current through the current blocking unit to produce a final output, which is a factor of increasing the current.

In view of the fact that the current used by the charge pump accounts for more than 50% of the entire chip, solving these problems can significantly reduce the current consumed in the operation of the entire chip.

2 is a circuit diagram illustrating a high voltage generator according to an embodiment of the present invention.

The high voltage generator 200 outputs two clock signals CLK2 and CLK2b of opposite levels by delaying the oscillator 210 generating the clock signal CLK1 having a specific frequency and the clock signal CLK1. ), A charge pump 230 for outputting a predetermined pumping voltage VPP by performing a pumping operation according to two clock signals CLK2 and CLK2b of opposite levels, and a distribution voltage and a reference voltage Vref of the pumping voltage VPP. ) And a pumping voltage regulator 240 for stabilizing the pumping voltage to a voltage of a predetermined level, and when the pumping voltage is stabilized, a voltage converter 250 for reducing and supplying a power voltage VDD applied to the clock driver. And a voltage conversion controller 260 for supplying first and second control signals having levels opposite to those of the voltage converter according to a comparison result of the pumping voltage regulator.

The oscillator 210 generates a clock signal CLK1 of a specific frequency and transmits the generated clock signal CLK1 to the clock driver 220.

The clock driver 220 is controlled according to the comparison result of the pumping voltage regulator 240. That is, the clock driver is driven when the divided voltage Vf1 and the reference voltage Vref of the pumping voltage are compared and the reference voltage is larger. The clock signal CLK1 is delayed according to the driving of the clock driver to output two clock signals CLK2 and CLK2b having opposite levels. The clock signals CLK2 and CLK2b are applied to the charge pump to increase the pumping voltage through the pumping operation.

An internal configuration of the clock driver will be described in more detail.

3 is a circuit diagram showing a detailed configuration of the clock driver 220 used in the present invention.

The clock driver 220 includes a first inverter group 310 in which n inverters are connected in series, and a second inverter group 320 in which n + 1 inverters are connected in series. Therefore, the clock CLK2 output through the first inverter group and the clock CLK2b output through the second inverter group have opposite levels.

At this time, the voltage supplied to each inverter in the present invention is to be applied differently according to the pumping degree of the charge pump.

In the conventional invention, the external power supply voltage VDD is fixedly applied regardless of the level of the pumping voltage, thereby causing ripple in the pumping voltage. Adding a regulator to remove the ripple is the circuit of FIG. 1 described above, and the problem is as described above.

In the present invention, it is to control to apply a voltage (VDC) of a level lower than the external power supply voltage (VDD) according to the pumping degree of the charge pump.

When the low level voltage is supplied to each inverter, the output level of the inverter is also lowered. In the case of a commonly used CMOS inverter, since the supply voltage supplied to the inverter is output as an output signal according to an input signal applied to the inverter, when the external supply voltage level is changed, the output level of the inverter is also changed.

Therefore, as the level of the supply voltage supplied to the clock driver 220 is lowered, the level of the output signal of the inverter is lowered, and as a result, the level of the clock signal CLK2 or CLK2b is lowered. Accordingly, there is an effect of lowering the level of ripple generated in the pumping voltage of the charge pump.

The components of FIG. 2 will be described again.

The charge pump 230 performs a pumping operation according to two clock signals CLK2 and CLK2b having different levels output from the clock driver 220 to output a predetermined pumping voltage VPP.

When the pumping voltage rises to a target voltage, a certain amount of ripple occurs. In the present invention, as described above, the voltage level of the clock output from the clock driver 220 is reduced to reduce the ripple.

The pumping voltage regulator 240 stabilizes the pumping voltage to a voltage of a predetermined level and supplies a regulation voltage Vreg.

The pumping voltage regulator 240 divides the pumping voltage to output a first divided voltage Vf1, a first voltage divider 244, a first divided voltage Vf1, and a first reference voltage VREF1. Compared to the first control unit includes a first comparison unit 242 for controlling the operation of the clock driver 220.

The first voltage divider 244 includes a plurality of passive elements R1 and R2 connected in series. The first voltage divider 244 receives the first divided voltage Vf1 input to the first comparator 242 according to a ratio thereof. Output Preferably, a plurality of first and second resistors R1 and R2 are connected in series between the pumping voltage output terminal VPP and ground, and are input to the first comparator 242 according to the ratio of these resistors. The first divided voltage Vf1 is outputted.

The first comparator 242 compares the first reference voltage VREF1 with the first divided voltage Vf1 and outputs a high level clock driving signal CKEN when the first reference voltage is larger than that of the clock driver 220. ) However, when the first reference voltage is smaller, the clock drive signal CKEN having a low level is output to the clock driver 220.

To this end, the first reference voltage VREF1 is input to the non-inverting terminal (+), and the first divided voltage includes an OP amplifier receiving the inverting terminal (−).

According to an exemplary embodiment, a differential amplifier may receive a first reference voltage VREF1 as a non-inverting terminal (+) and a first split voltage as an inverting terminal (−) as the comparison unit.

According to such a configuration, the value of the final pumping voltage VPP has the following equation.

The voltage converter 250 converts the magnitude of the supply voltage Va supplied to the clock driver according to the level of the pumping voltage.

In the present invention, the external power supply voltage VDD is supplied as it is during the period in which the pumping voltage increases. However, when the pumping voltage reaches the target voltage and stabilizes, a voltage lower than the external power supply voltage is supplied to the clock driver 220.

The voltage converter 250 divides the supply voltage Va to output a second divided voltage Vf2, and an external power supply voltage VDD or higher with respect to the clock driver. The voltage supply unit 256 for supplying the conversion voltage VDC having a low level, and the voltage supply unit 256 during the rising period of the pumping voltage (that is, the period in which the divided voltage of the pumping voltage is smaller than the first reference voltage) An external power supply voltage supply control unit 258 for supplying an external power supply voltage VDD, and the voltage supply unit 256 during a period in which the pumping voltage is stabilized (that is, a period in which the divided voltage of the pumping voltage is greater than a first reference voltage). ) Includes a second comparator 252 for supplying the conversion voltage VDC.

The voltage supply unit 256 has an output terminal of the second comparator 252 and an external power supply voltage supply control unit 258 connected in parallel to a gate, and one terminal thereof is connected with an external power supply voltage terminal VDD, and the other terminal is connected to the gate terminal. A PMOS transistor P256 connected to the second voltage divider 254 is included. At this time, the voltage Va applied to the connection node with the second voltage divider 254 is supplied to the clock driver 220 as a supply voltage.

Therefore, when the pumping voltage rises and the external power supply voltage supply controller 258 applies a low level signal, the PMOS transistor P256 is turned on so that the external power supply voltage VDD becomes the supply voltage Va. 220).

In addition, when the pumping voltage is stabilized and the second comparator 252 supplies the high level signal or the external power voltage supply controller 258 stops supplying the low level signal, the PMOS transistor P256 is turned off. The voltage applied to the connection node is supplied to the clock driver 220 as it is.

The external power supply voltage supply control unit 258 is an NMOS transistor N258 connected between the gate and the ground terminal of the PMOS transistor P256 of the voltage supply unit 256, and a control signal DETECT of the voltage conversion control unit 260. Inverter IV258 is inverted and supplied to the gate of the NMOS transistor N258.

A detailed configuration of the voltage conversion controller 260 will be described later. When the control signal DETECT is briefly described, this is a signal whose level varies depending on the level of the pumping voltage. That is, the control signal DETECT is a signal having a low level value in a section where the pumping voltage increases and a high level value in a section where the pumping voltage is stabilized.

Accordingly, the external power supply voltage supply controller 258 turns on the NMOS transistor N258 by inverting the low level control signal DETECT in the period in which the pumping voltage rises, thereby turning the ground voltage of the voltage supply part 256 into the external supply voltage supply control unit 258. The PMOS transistor P256 is supplied. Accordingly, an external power supply voltage VDD is supplied to the clock driver 220.

However, since the high level control signal DETECT is applied in the period where the pumping voltage is stabilized, the NMOS transistor N258 is not turned on, and thus the PMOS transistor P256 is not turned on.

In this manner, the voltage supply unit 256 is controlled to supply the external power voltage VDD.

The second voltage divider 254 includes a plurality of passive elements R3 and R4 connected in series with the external power voltage supply controller 256, and distributes the supply voltage Va according to their ratio. The second divided voltage Vf2 is output. The output second divided voltage Vf2 is applied to one terminal of the second comparator 252.

In an embodiment of the present invention, the values of the passive elements are the same so that a value corresponding to 1/2 of the supply voltage Va is applied to the second comparator 252.

The second comparator 252 compares the second reference voltage VREF2 with the second divided voltage Vf2 and outputs a high level signal to the voltage supply unit 256 when the second reference voltage is larger. To this end, it includes an OP amplifier receiving the second reference voltage VREF2 as the non-inverting terminal (+) and receiving the second divided voltage as the inverting terminal (−).

According to an exemplary embodiment, a differential amplifier may receive a second reference voltage VREF2 as a non-inverting terminal (+) and a second divider voltage as an inverting terminal (−) as the comparison unit.

The second comparator 252 is driven in response to the control signal DETECT of the voltage conversion controller 260 described above. That is, the operation is performed only when a high level DETECT control signal is applied. Therefore, the pump operates only in a section where the pumping voltage is stabilized.

Meanwhile, the second comparator 252, the second voltage divider 254, and the voltage supply unit 256 operate as another regulator. That is, the value of the supply voltage is stabilized constantly. The value of the supply voltage has the following formula.

If the values of the resistors are the same, the relationship is Va = 2 * Vref2. Therefore, the level of the conversion voltage VDC varies depending on how the second reference voltage is set.

In the present invention, the second reference voltage is applied so that a voltage of 1.8 to 2.0 V is output as the conversion voltage. This is a voltage lower than the external power supply voltage (2.7 to 3.6V). Preferably, the difference between the external power supply voltage and the conversion voltage is characterized in that 0.7 ~ 1.8V.

On the other hand, the second reference voltage is generated using a bandgap reference voltage generation circuit having a constant voltage value without being affected by temperature changes.

In summary, the voltage supply unit 250 applies a supply voltage having a different level according to the level of the pumping voltage.

The voltage conversion controller 260 supplies first and second control signals having levels opposite to those of the voltage converter according to the level of the pumping voltage.

To this end, the first control signal supply unit 262 generates a first control signal having a high level during the stabilization period of the pumping voltage, and the second control signal supply unit generates a second control signal having a low level during the rising period of the pumping voltage. 268, a control signal buffer unit 264 for temporarily storing the control signals and outputting the control signals to the voltage converter 250.

The first control signal supply unit 262 may include a first inverter IV264 for inverting the enable signal EN and a clock driving signal CKEN output from the first comparator of the pumping voltage regulator 240. A negative OR gate NOR262 that receives the inverted enable signal EN as an input, a second inverter IV262 that inverts and outputs an output of the negative OR gate 262, and a high voltage according to an output of the second inverter. The PMOS transistor P262 transfers a level voltage to the control signal buffer unit 264.

In operation of the first control signal supply unit, a high level enable signal EN is supplied. In addition, the clock driving signal CKEN of the high level is output in the rising period of the pumping voltage. Thus, the NOR gate outputs a low level signal, which becomes a high level signal via the second inverter. Thus, the PMOS transistor P262 is maintained in the turn off state.

On the other hand, when the pumping voltage is stabilized and the low level clock driving signal CKEN is output, the negative logic sum gate outputs a high level signal. This becomes a low level signal through a second inverter, and the PMOS transistor P262 is turned on so that an external power supply voltage having a high level is stored in the control signal buffer unit 264.

The second control signal supply unit 268 transmits a ground voltage to the control signal buffer unit 264 in response to a power-up reset signal POR, and the ground voltage in response to a reset signal. And an NMOS transistor N269 transmitted to the control signal buffer unit 264.

When the external power supply voltage VDD is applied to the nonvolatile memory device, it rises from 0V to a predetermined voltage. At this time, while monitoring the rise of the external power supply voltage, when a voltage higher than a predetermined level is applied, the power-up reset signal POR of a low level is output.

Accordingly, a power-up reset signal POR is applied at the initial stage of operation of the nonvolatile memory device to store a low level voltage in the control signal buffer unit 264.

The control signal buffer unit 264 includes latches IV265 and IV266 and an inverter IV264 connected to connection nodes of the first control signal supply unit 262 and the second control signal supply unit 268. Therefore, the first control signal or the second control signal is stored and output as a control signal DETECT to the voltage converter 250.

In view of the operation of the nonvolatile memory device, since a power-up reset signal is initially applied, a second low level control signal is stored in the latch and output as the control signal DETECT.

Thereafter, when the pumping voltage rises and stabilizes, and the low level clock driving signal CKEN is output, the high level first control signal is stored in the latch and output as the control signal DETECT.

Now, the operation of the high voltage generator will be summarized.

4 is a waveform diagram illustrating various waveforms applied during the operation of the high voltage generator according to an exemplary embodiment of the present invention.

First, when the pumping voltage is increased to apply the high level clock driving signal CKEN, the voltage conversion controller 260 outputs the low level control signal DETECT.

The low level control signal DETECT operates the external power supply control unit 258 of the voltage converter 250, and accordingly, the external power supply voltage VDD is supplied as a supply power.

Thereafter, when the pumping voltage reaches the target constant voltage level and stabilizes, the clock driving signal CKEN having a low level is output. However, the high level voltage may be output in the form of an impulse according to the operation of the first comparator of the pumping voltage regulator.

In response to the low level clock driving signal CKEN input, the voltage conversion controller 260 outputs a high level control signal DETECT.

In response to the control signal being applied, the second comparator 252 starts driving, and the supply voltage transitions to the conversion voltage VDC at a level lower than the external power supply voltage.

As such, since the magnitude of the supply voltage supplied to the clock driver 220 varies according to the level of the pumping voltage, the level of the clock output from the clock driver also changes.

In particular, as the magnitude of the supply voltage is lowered, the level of the clock is also lowered, which has the effect of reducing the ripple of the pumping voltage.

Description of the main parts of the drawing

200: high voltage generator

210: oscillator

220: clock driver

230: charge pump

240: pumped voltage regulator

242: first comparator 244: first voltage divider

250: voltage conversion unit

252: second comparator 254: second voltage divider

256: voltage supply unit 258: external power voltage supply control unit

260: voltage conversion control unit

262: first control signal supply unit 264: control signal buffer unit

268: second control signal supply unit

Claims

A clock driver for delaying an external clock to generate first and second clock signals having opposite levels;

In the high voltage generator comprising a charge pump for pumping an external power supply voltage in accordance with the first and second clock signal,

And when the pumping voltage rises and stabilizes at a predetermined level, a high voltage generator which supplies a converted voltage having the external power supply voltage reduced to the clock driver.

2. The high voltage generator of claim 1, wherein the clock driver generates first and second clock signals having a lower amplitude than when the external voltage is supplied.

The method of claim 1, wherein the high voltage generator further comprises a pumping voltage regulator for stabilizing the output voltage of the charge pump to a predetermined level,

The pumping voltage regulator outputs a first clock driving signal for operating the clock driver while the pumping voltage is rising,

And outputting a second clock driving signal to stop the operation of the clock driver when the pumping voltage is stabilized to a predetermined level.

The pumping voltage regulator of claim 3, further comprising: a first voltage divider configured to divide the pumping voltage and output a first divided voltage;

And a first comparator for comparing the first divided voltage and the first reference voltage to output the clock driving signal.

4. The voltage converter of claim 3, further comprising: a voltage converter configured to supply an external power supply voltage to the clock driver while the pumping voltage is increased, and to supply the converted voltage to the clock driver when the pumping voltage is stabilized to a predetermined level;

And a voltage conversion controller configured to control the voltage converter to supply the external power voltage or the conversion voltage according to the level of the clock driving signal output from the pumping voltage regulator.

The apparatus of claim 5, wherein the voltage conversion controller comprises: a first control signal supply unit configured to generate a first control signal when the pumping voltage is stabilized at a predetermined level;

A second control signal supply unit which generates a second control signal while the pumping voltage is increased;

And a control signal buffer unit for temporarily storing the control signals and outputting the control signals to the voltage converter.

The apparatus of claim 6, wherein the voltage converter divides an output voltage and outputs a second divided voltage.

A voltage supply unit supplying the external power supply voltage or the conversion voltage to the clock driver;

An external power supply voltage supply controller configured to supply the external power supply voltage to the voltage supply unit in response to the second control signal;

And a second comparator for causing the voltage supply unit to supply the converted voltage in response to the first control signal.

The high voltage generator of claim 7, wherein the second comparator is driven by the first control signal and compares a magnitude of a second reference voltage and the second divided voltage.

The high voltage generator of claim 1, wherein the conversion voltage is 0.7 to 1.8V lower than the external power supply voltage.

In the high voltage generator for pumping the external power supply voltage in accordance with the first and second clock signals of mutually opposite levels,

And a voltage converter configured to reduce a amplitude of the first and second clock signals by supplying a converted voltage to the clock driver when the pumping voltage is stabilized to a predetermined level.

The high voltage generator of claim 10, wherein the voltage converter supplies the external power supply voltage to a clock driver while a pumping voltage is increased.

The method of claim 10, wherein the high voltage generator further comprises a pumping voltage regulator for stabilizing the output voltage of the charge pump to a predetermined level,

The pumping voltage regulator outputs a first clock driving signal for operating a clock driver to output the first and second clock signals while the pumping voltage is increased,

And a second clock driving signal for stopping an operation of a clock driver so that output of the first and second clock signals is stopped when the pumping voltage is stabilized to a predetermined level.

The apparatus of claim 12, wherein the high voltage generator further comprises a voltage conversion controller configured to control the voltage converter to supply the external power voltage or the conversion voltage according to a level of a clock driving signal output from the pumping voltage regulator. High voltage generator.

The apparatus of claim 13, wherein the voltage conversion controller comprises: a first control signal supply unit configured to generate a first control signal when the pumping voltage is stabilized at a predetermined level;

15. The apparatus of claim 14, wherein the voltage converter divides an output voltage to output a second divided voltage;

16. The high voltage generator of claim 15, wherein the second voltage divider comprises first and second passive elements connected in series to distribute the output voltage.

The high voltage generator of claim 15, wherein the second comparator is driven by the first control signal and compares a magnitude of a second reference voltage and the second divided voltage.

18. The high voltage generator of claim 17, wherein the second reference voltage is applied such that the converted voltage is 0.7 to 1.8 V lower than an external power supply voltage.