KR20090044845A - Method for fabricating semiconductor device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device, the method comprising: forming a first interlayer insulating film on a substrate, forming a plurality of bit lines on the first interlayer insulating film, an upper portion of the bit line, and Forming a second interlayer insulating film exposing a portion of the sidewalls, forming a protective film covering upper and sidewalls of the exposed bit line, and a second interlayer insulating film and a first interlayer insulating film below the protective film as an etch barrier. By forming a contact hole by etching, it is possible to prevent the loss of the thin films to protect the bit line, it is possible to prevent a short with the subsequent plug.

Contact hole, bit line, interlayer insulating film, short, plug

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device for preventing the loss of a thin film protecting a bit line.

A DRAM (Dynamic Random Access Memory) device representing a semiconductor device, particularly a DRAM device of 60 nm or less, has a plurality of unit memory cells including one transistor and one capacitor.

The capacitor is in contact with a storage node contact plug to transmit an electrical signal.

The storage node contact plug further includes a second plug 13 as shown in FIG. 1 to improve an overlay margin with the first electrode of the capacitor, which means the storage node or the lower electrode. This second plug 13 is referred to as 'SNC2'. Here, '12' is the first plug 12 and '11' is the interlayer insulating film 11. The first plug 12 and the second plug 13 are referred to as storage node contact plugs.

In order to form the storage node contact plug having the above structure, a hole type storage node contact hole must be formed. The storage node contact hole is formed by using a photoresist pattern formed by an argon fluoride (ArF) exposure process. This increases the manufacturing cost. In addition, a higher cost is consumed because the process for forming the second plug 13 must be further performed.

In order to solve this problem, a method of forming a storage node contact hole with a line type mask has been proposed.

2 is a process cross-sectional view showing a method for manufacturing a line-type storage node contact hole according to the prior art.

Referring to FIG. 2, an insulating film is formed on a substrate 23 including a plurality of bit lines 22, and a line mask pattern 21 is formed on the insulating film.

Subsequently, the insulating layer is etched using the mask pattern 21 as an etch barrier to form the storage node contact hole 24 exposing the substrate 23. Here, the etching of the insulating layer corresponds to the self aligned contact (SAC) etching.

Self-aligned contact etching is an etching process using an etching selectivity between the nitride film and the oxide film. The nitride film corresponds to the bit line hard mask film 27 and the bit line spacer 28 included in the bit line 22, and the oxide film is an insulating film. Corresponds to

When using such a linear mask pattern 21, it can be formed by a Krypton argon (KrF) exposure process can reduce the cost.

However, when the storage node contact hole 24 is formed using the line mask pattern 21, the bit line 22 is exposed to the outside, which is why the bit line hard mask layer 27 and the bit liner 28 are exposed. An excessive loss occurs in the SAC etching process. Hereinafter, the above problem is abbreviated as 'SAC fail (fail)'.

Accordingly, there is a need for a technology capable of preventing SAC fail in the process of forming the storage node contact hole 24 using the line mask pattern 21.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device which prevents the loss of thin films protecting a bit line in a SAC process using a line mask pattern. .

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a first interlayer insulating film on a substrate, forming a plurality of bit lines on the first interlayer insulating film, the top and sidewalls of the bit line Forming a second interlayer insulating film exposing a portion, forming a protective film covering upper and sidewalls of the exposed bit line, and forming a second interlayer insulating film and a first interlayer insulating film under the protective film as an etch barrier. And etching to form contact holes.

The present invention based on the above-described problem solving means can prevent the loss of the thin film to protect the bit line in the SAC etching process using a line-type mask pattern, it is possible to prevent a short with the subsequent plug.

In addition, since the present invention forms a line-type mask pattern by a krypton argon (KrF) exposure process instead of an argon fluoride (ArF) exposure process, the cost reduction effect can be seen. In addition, the SNC2 forming process can be omitted, thereby simplifying the process and reducing the cost.

Therefore, the present invention not only can improve the stability and reliability of the semiconductor device, but also has the effect of improving the yield.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 3A, an interlayer insulating film 31 is formed on the substrate 30 on which a predetermined lower layer is formed. The first interlayer insulating film 31 is formed of an oxide film.

Subsequently, the barrier metal 32, the metal film 33, and the dual hard mask film 34 are sequentially formed on the first interlayer insulating film 31, and then patterned to form a plurality of bit line patterns. Form.

The barrier metal 32 is formed of a structure in which a titanium film Ti and a titanium nitride film TiN are sequentially stacked, and the metal film 33 is formed of a tungsten film.

The dual hard mask film 34 has a structure in which at least two or more thin films are stacked. In an embodiment, the dual hard mask film 34 has a structure in which the first hard mask film 34A and the second hard mask film 34B are stacked. The first hard mask film 34A is formed of an insulating film, especially a silicon nitride film (Si ₃ N ₄ ), and the second hard mask film 34B is a tungsten film (W), a tungsten nitride film (WN), and a titanium nitride film (TiN). , At least one thin film selected from the group consisting of an aluminum film Al and a poly-silicon film. For example, it may have a stacked structure of tungsten film W and tungsten nitride film WN.

Subsequently, a bit liner 35 is formed on sidewalls of the bit line pattern.

The bit liner 35 protects the sidewalls of the bit line pattern and prevents the metal film 33 from being oxidized in a subsequent heat treatment process.

In order to form the bit liner 35, an insulating film is formed on the entire surface of the substrate 30 and anisotropically etched. The insulating film is formed of a nitride film, particularly a silicon nitride film. The bit liner 35 is formed to a thickness of at least several tens of micrometers or less in order to prevent the line margin of the bit line pattern from being excessively increased and the open margin thereof becomes poor.

As shown in FIG. 3B, the second interlayer insulating layer 36 is formed to fill the bit line patterns.

Subsequently, after forming the line-type mask pattern 37 on the second interlayer insulating film 36, the second interlayer insulating film 36 is partially etched so that a portion of the bit line pattern is embedded. .

The etching of the second interlayer insulating layer 36A is performed by an etching gas having an etching selectivity with the dual hard mask layer 34 and the bit line spacer 35 of the bit line pattern. For example, oxygen (O ₂ ) is added to the stock corner gas of C _x F _y (where x and y are natural numbers except 0). Here, the gas of the C _x F _y system may be CF ₄ or C ₄ F ₈ gas.

The linear mask pattern 37 is a photoresist pattern formed by argon fluoride (ArF) or krypton argon (KrF) exposure process.

Subsequently, a wet etching process is performed. Referring to the right drawing, it can be seen that part of the second interlayer insulating film 36A under the line-type mask pattern 37 is etched by the isotropic etching characteristic of the wet etching. That is, the portion represented by the dotted line shows that the second interlayer insulating film 36A under the line mask pattern 37 is etched.

More specifically, referring to FIG. 4, which shows a cut plane of II ′ of FIG. 3B, it can be seen that the second interlayer insulating film 36A under the line mask pattern 37 is expanded by wet etching. This is to increase the contact area by securing an overlay margin between the first electrode of the capacitor to be formed later-the storage node or the lower electrode-and the storage node contact plug.

The wet etching process uses a dip out wet station, but can also be performed in a spin or spray wet station to improve wet etch uniformity. Can be. And, the chemical (chemical) proceeds to the chemical containing fluorine (fluorine), for example, may be a BOE (Buffered Oxide Etchant) or hydrogen fluoride (HF) solution.

After the wet etching process, the height of the remaining second interlayer insulating film 36A is preferably higher than the metal film 33 in the bit line pattern. This is to increase the stability of the device and to further reduce the possibility of the metal film 33 being exposed.

As shown in FIG. 3C, the passivation layer 38 is formed on the top and sidewalls of the exposed bit line pattern.

The passivation layer 38 is formed of a carbon-based polymer, and the thickness D1 of the passivation layer 38 formed on the bit line pattern is the thickness of the passivation layer pattern 38 formed on the sidewall of the bit line pattern. Thicker than D2). Proportionally, D1: D2 has a 3: 1 ratio. To this end, the formation of the carbon-based polymer proceeds at a high pressure, such as a chamber pressure of 100 ~ 200mTorr.

As a method of forming the protective film 38, the carbon-based polymer forming and etching process may be sequentially and repeatedly performed. Referring to FIG. 5 as a diagram illustrating this, first, a carbon-based polymer 38A is formed. In this process, the carbon-based polymer 38A formed on the plurality of bit line patterns may be connected to each other because of the characteristics of the thin film having poor step coverage.

Thus, the etching process for the carbon-based polymer 38A is performed to form the protective film 38.

The formation and etching of the carbon-based polymer 38A are repeated until the protective film 38 having a desired thickness is formed.

Formation of the carbon-based polymer uses a plasma generated with at least one gas selected from the group consisting of C ₂ H ₄ , CH ₃ F and CH ₄ gas at a chamber pressure of 100 ~ 200mTorr. For example, it may be a mixed gas of C ₂ H ₄ , CH ₃ F. In addition, at least one selected from the group consisting of C ₂ H ₄ , CH ₃ F and CH ₄ gas, and Ar and N ₂ gas may be mixed.

Etching of the carbon-based polymer proceeds to etch back, using plasma generated from CF ₄ and CHF ₃ gas.

The carbon-based polymer is formed and etched in-situ in an etch chamber in which the second interlayer insulating film 36A is partially etched.

In addition, in order to form the passivation layer 38 only on the top and sidewalls of the bit line pattern, the carbon-based polymer formed on the second interlayer insulating layer 36 must be etched.

The etching process may be performed in the formation and etching process of the carbon-based polymer described above, and may be performed in a separate etching process after the deposition of the carbon-based polymer is completed.

As shown in FIG. 3D, the first interlayer insulating layer 31 is etched using the protective layer 38 as an etch barrier to form the contact hole 39.

The first interlayer insulating layer 31 is etched using a fluorine-based etching gas, and the fluorine-based etching gas may be C ₄ F ₆ and C ₄ F ₈ gases.

As shown in FIG. 3E, the contact hole 39 is expanded after the protective film 38 is removed.

Removal of the protective film 38 uses a plasma generated by O ₂ gas, and the expansion of the contact hole 39 proceeds by wet etching.

In this wet etching process, the second interlayer insulating layer 36A remaining due to the passivation layer 38 formed on the sidewalls of the bit line pattern may be removed, and the first interlayer insulating layer 31A may be etched to etch the bottom of the contact hole 39. You can increase the line width of the face. As a result, the contact hole 39 is expanded.

Subsequently, a conductive plug is embedded in the contact hole 39 to form a contact plug. This contact plug corresponds to a storage node contact plug. In addition, before forming the contact plug, a spacer may be formed on the sidewall of the contact hole 39 to prevent short between the bit line and the storage node contact plug.

The storage node contact plug formed through the above process does not generate a short between the bit line patterns due to the stably formed contact hole 39.

In the embodiment of the present invention as described above, the contact hole 39 is formed by using the mask pattern 39 of the linear shape.

In this case, the bit line pattern may be exposed on the entire surface to generate a SAC fail. In order to prevent this, the passivation layer 38 is formed on the bit line pattern in an overhang structure. The overhang structure refers to a form that covers the upper and sidewall portions of the vertical structure, such as the sulfur shape of the match. Therefore, SAC fail does not occur.

In addition, the second interlayer insulating layer 36A under the linear mask pattern 39 is expanded by wet etching to increase the contact area between the first electrode of the capacitor and the storage node contact plug.

In addition, the contact hole 39 is formed and expanded to increase the line width of the contact hole 39, in particular, the line width of the bottom of the contact hole 39.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1 is a structural cross-sectional view showing a storage node contact plug according to the prior art.

Figure 2 is a process cross-sectional view showing a manufacturing method of a line-type storage node contact hole according to the prior art.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4 is a cross-sectional view illustrating a cutting plane taken along line II ′ of FIG. 3B.

5 is a cross-sectional view showing a method of forming a protective film.

Explanation of symbols on the main parts of the drawings

30 substrate 31A first interlayer insulating film

32: barrier metal 33: metal film

34: dual hard mask film 34A: first hard mask film

34B: Second Hard Mask Layer 35: Beat Liner Facer

39: contact hole

Claims (15)

Forming a first interlayer insulating film on the substrate; Forming a plurality of bit lines on the first interlayer insulating film; Forming a second interlayer insulating film exposing a portion of an upper sidewall and a sidewall of the bit line; Forming a protective film covering upper and sidewalls of the exposed bit line; And Forming a contact hole by etching the second interlayer insulating layer having the protective layer as an etch barrier and the first interlayer insulating layer below the protective layer; Semiconductor device manufacturing method comprising a. The method of claim 1, The passivation layer may be formed in an overhang structure on the bit line. The method of claim 1, The protective film is a semiconductor device manufacturing method formed of a carbon-based polymer. The method of claim 1, Forming the protective film, Forming a carbon-based polymer in an overhang structure along the steps of the plurality of bit lines; And Etching the carbon-based polymer by an etch back process Semiconductor device manufacturing method comprising a. The method according to claim 3 or 4, The carbon-based polymer is a semiconductor device manufacturing method using at least one gas selected from the group consisting of C ₂ H ₄ , CH ₃ F and CH ₄ gas. The method according to claim 3 or 4, The carbon-based polymer is a semiconductor device manufacturing method using a gas mixed with at least one gas selected from the group consisting of C ₂ H ₄ , CH ₃ F and CH ₄ gas and Ar and N ₂ gas. The method according to claim 3 or 4, The carbon-based polymer is a semiconductor device manufacturing method that proceeds at a chamber pressure of 100 ~ 200mTorr. The method of claim 4, wherein A method of manufacturing a semiconductor device, wherein the protective film is formed by repeatedly forming and etching the carbon-based polymer. The method of claim 4, wherein Etching of the carbon-based polymer is a semiconductor device manufacturing method that proceeds to the plasma generated by the CF ₄ and CHF ₃ gas. The method of claim 4, wherein The forming and etching process of the carbon-based polymer is in-situ in the chamber for forming the second interlayer insulating film. The method of claim 1, The forming of the second interlayer insulating layer may include performing partial etching and wet etching sequentially using a line mask pattern. The method of claim 1, The bit line includes a barrier metal, a metal film, and a dual hard mask film. The method of claim 12, The dual hard mask layer includes at least two or more thin films. The method of claim 12, The dual hard mask layer may include at least one thin film selected from the group consisting of an insulating film, a tungsten film (W), a tungsten nitride film (WN), a titanium nitride film (TiN), an aluminum film (Al), and a polysilicon film (poly-silicon). Method of manufacturing a semiconductor device formed by laminating. The method of claim 1, After forming the contact hole, expanding the contact hole; Forming a spacer on the sidewall surface of the extended contact hole; And Forming a plug in the contact hole A semiconductor device manufacturing method further comprising.

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