KR20090044643A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20090044643A
KR20090044643A KR1020070110825A KR20070110825A KR20090044643A KR 20090044643 A KR20090044643 A KR 20090044643A KR 1020070110825 A KR1020070110825 A KR 1020070110825A KR 20070110825 A KR20070110825 A KR 20070110825A KR 20090044643 A KR20090044643 A KR 20090044643A
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KR
South Korea
Prior art keywords
film
fuse
pad
forming
trench
Prior art date
Application number
KR1020070110825A
Other languages
Korean (ko)
Inventor
김덕수
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070110825A priority Critical patent/KR20090044643A/en
Publication of KR20090044643A publication Critical patent/KR20090044643A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive

Abstract

The present invention relates to a method of manufacturing a semiconductor device, the method of manufacturing a semiconductor device of the present invention, forming a fuse in the fuse region on the substrate having a fuse region and a pad region; Forming an insulating film on the resultant including the fuse; Forming a pad in which a metal film, an antireflection film, and a hard mask are stacked in the pad area on the insulating film; Forming a protective film on the resultant including the pad; Performing a repair / pad etching to stop the etching in the anti-reflection film to form a first trench for exposing the anti-reflection film in the pad area, while leaving the insulating film on the fuse at a predetermined thickness Forming a trench; Forming a material layer on the passivation layer to cover sidewalls of the second trench while opening the first trench and the second trench; And removing the anti-reflection film using the material layer as an etching barrier, wherein the method of manufacturing a semiconductor device according to the present invention includes forming a hard mask on the anti-reflection film of the pad area to fix / fuse the fuse area during etching. By increasing the degree of etching of the polyimide film deposited on the sidewalls of the polyimide film, the cracks can be prevented, and an etch stop film can be formed in the fuse region to maintain the desired thickness of the insulating film on the fuse.

Repair / Pad Etch, Fuse, Pad, Polyimide, Anti-reflective, Etch Stop

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacturing technology of semiconductor devices, and more particularly, to repair / pad etching of semiconductor devices.

In the manufacture of a semiconductor memory device, if any one of a number of fine cells is defective, it cannot be performed as a memory and thus is treated as a defective product. However, even though only a few cells in the memory have failed, disposing of the entire device as defective is inefficient in terms of yield.

Therefore, the current yield is improved by replacing the defective cells by using redundancy cells pre-installed in the memory, thereby restoring the entire memory. In more detail, a test is performed to determine whether cells formed on a substrate are defective, and as a result, the cells determined to be defective are removed by fuse cutting by a laser beam through a repair process and replaced with redundancy cells in a chip. . Here, the fuse is not formed using a separate wiring, but is formed in the fuse area by selecting one of a conventional circuit wiring (for example, a word line, a bit line, a plate line, or a metal wiring).

Meanwhile, an etching process for forming a fuse box and an etching process for forming a pad for inputting and outputting signals of a semiconductor device are performed in one etching process, which is called a repair / pad etching process.

1A and 1B are cross-sectional views illustrating a repair / pad etching process according to the prior art.

As shown in Fig. 1A, a fuse 11 is formed in a fuse area on the substrate 10 having a fuse area and a pad area. In this case, the fuse 11 may be formed using, for example, a plate line of a capacitor.

Next, the insulating film 12 covering the fuse 11 is formed. In this case, an oxide-based thin film (eg, a spin on glass (SOG) film) is generally used as the insulating film 12.

Subsequently, a pad 13 in which the metal film 13a and the antireflection film 13b are stacked is formed in the pad region on the insulating film 12. At this time, Al film is generally used as the metal film 13a, and TiN film is used as the antireflection film 13b.

Next, the protective film 14 which covers the pad 13 is formed. The protective film 14 is generally formed by stacking an HDP oxide film and a nitride film.

Subsequently, after forming a mask (not shown) for repair / pad etching on the passivation layer 14, the passivation layer 14 and / or the insulating layer 12 are etched using the mask as an etching barrier, but the anti-reflection layer 13b is used. To stop the etching. This is called repair / pad etching. As a result of performing the repair / pad etching, an initial first trench 15 exposing the anti-reflection film 13b is formed in the pad area, and an initial second in which the insulating film 12 on the fuse 11 is left in a predetermined thickness in the fuse area. Trench 16 is formed.

As shown in FIG. 1B, a polyimide film 17 is deposited on the protective film 14 to open the initial first trench 15 and the initial second trench 16. In this case, a polyimide layer 17 is deposited to cover the sidewalls of the initial second trench 16 of the fuse region. This is to prevent cracks due to moisture infiltration in the subsequent packaging process since the insulating layer 12 generally includes a material vulnerable to moisture such as SOG.

Subsequently, the final anti-reflection film 13b of the pad region is etched using the polyimide film 17 as an etch barrier to form the final first trench 15 ′ exposing the metal film 13a, thereby forming a fuse in the fuse region. 11, the insulating film 12 is etched until the insulating film 12 remains at a desired thickness to form a final second trench 16 ′. This is called SWP (Sidewall Polyimide) etching.

However, such conventional repair / pad etching and SWP etching have the following problems.

First, since the etching is stopped in the anti-reflection film 13b during the repair / pad etching, the etching degree in the fuse area, that is, the depth of the initial second trench 16 is relatively small. Therefore, even if the polyimide film 17 for preventing cracks is deposited on the sidewalls, the insulating film 12 is exposed during subsequent SWP etching, and still has a problem of being vulnerable to moisture penetration (see dotted line in FIG. 1B).

In addition, it is required to completely remove the anti-reflection film 13b and to maintain the insulating film 12 on the fuse 11 at a desired thickness during SWP etching.

The present invention has been proposed to solve the above problems of the prior art, by forming a hard mask on the anti-reflection film of the pad region to increase the degree of etching of the fuse region during repair / pad etching, the degree of polyimide film deposition on the sidewalls The present invention provides a method for manufacturing a semiconductor device capable of increasing cracks to prevent cracks and forming an etch stop layer in the fuse region to maintain the desired thickness of the insulating film on the fuse.

The semiconductor device manufacturing method of the present invention for solving the above problems comprises the steps of forming a fuse in the fuse region on the substrate having a fuse region and a pad region; Forming an insulating film on the resultant including the fuse; Forming a pad in which a metal film, an antireflection film, and a hard mask are stacked in the pad area on the insulating film; Forming a protective film on the resultant including the pad; Performing a repair / pad etching to stop the etching in the anti-reflection film to form a first trench for exposing the anti-reflection film in the pad area, while leaving the insulating film on the fuse at a predetermined thickness Forming a trench; Forming a material layer on the passivation layer to cover sidewalls of the second trench while opening the first trench and the second trench; And removing the anti-reflection film using the material film as an etching barrier.

In addition, another method of manufacturing a semiconductor device of the present invention for solving the above problems comprises the steps of forming a fuse in the fuse region on the substrate having a fuse region and a pad region; Forming a first insulating film, an etch stop film, and a second insulating film on a resultant including the fuse; Forming a pad in which a metal film, an anti-reflection film, and a hard mask are stacked in the pad area on the second insulating film; Forming a protective film on the resultant including the pad; Performing repair / pad etching to stop the etching in the anti-reflection film, thereby forming a first trench in which the anti-reflection film is exposed in the pad area, and forming a second trench in which the etch stop film is left in the fuse area. step; Forming a material layer on the passivation layer to cover sidewalls of the second trench while opening the first trench and the second trench; And removing the anti-reflection film and at least an etch stop film as an etching barrier.

In the method of manufacturing a semiconductor device according to the present invention described above, a hard mask is formed on an anti-reflection film in a pad region to increase the degree of etching of the fuse region during repair / pad etching, thereby increasing the degree of polyimide film deposition on the sidewalls of the pad region. Generation can be prevented, and an etch stop film can be formed in the fuse region to maintain the thickness of the insulating film over the fuse to a desired degree.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in Fig. 2A, a fuse 21 is formed in the fuse area on the substrate 20 having the fuse area and the pad area. In this case, the fuse 21 may be formed using, for example, a plate line of a capacitor.

Subsequently, an insulating film 22 covering the fuse 21 is formed on the resultant product including the fuse 21. As the insulating film 22, an oxide-based thin film (for example, a SOG (Spin On Glass) film) is used. In this case, the etch stop layer 23 may be interposed in the insulating layer 22, and the insulating layer 22 may be formed on the lower first insulating layer 22a and the upper second insulating layer based on the etch stop layer 23. 22b). The etch stop layer 23 is for easily adjusting the thickness of the insulating layer remaining on the fuse 21 during the subsequent repair / pad etching. Therefore, when the thickness of the insulating film which is desired to remain on the fuse 21 is referred to as a target thickness (for example, 1500Å), the etch stop film 23 is formed by the thickness of the first insulating film 22a on the fuse 21. Preferably, T) is interposed at a position equal to the target thickness. It is preferable that such an etch stop film 23 is made of a nitride film.

Subsequently, a pad 24 in which the metal film 24a, the antireflection film 24b, and the hard mask 24c are stacked is formed in the pad region on the insulating film 22. An Al film is used as the metal film 24a, and a TiN film is used as the antireflection film 24b. In this case, the hard mask 24c is to increase the etching degree of the fuse area in the subsequent repair / pad etching. Therefore, it is preferable to use a material (for example, amorphous carbon) having a high etching selectivity with the oxide-based thin film constituting the insulating film 22 as the hard mask 24c.

Subsequently, a protective film 25 covering the pad 24 is formed on the resultant product including the pad 24. It is preferable that the protective film 25 has a laminated structure of an oxide film and a nitride film.

As shown in FIG. 2B, after forming a mask (not shown) for repair / pad etching on the protective film 25, the mask is used as an etching barrier to repair or stop the etching on the anti-reflection film 24b. Perform etching.

In this case, the passivation layer 25 and the hard mask 24c are etched in the pad region to form an initial first trench 26 exposing the antireflection layer 24b.

At the same time, the protective film 25 and the insulating film 22 are etched in the fuse region to form the initial second trench 27. At this time, the degree of etching of the insulating layer 22 in the fuse region, that is, the depth of the initial second trench 27 increases with the interposition of the hard mask 24c, which is the material and the thickness of the hard mask 24c. Can be adjusted accordingly. Preferably, all of the second insulating layers 22b may be etched and the etching may be stopped at the etch stop layer 23. However, the present invention is not limited thereto, and the initial second trench 27 may be formed so that the second insulating film 22b remains a predetermined thickness on the etch stop film 23 (see dotted line).

As shown in FIG. 2C, a polyimide film 28 is deposited on the passivation layer 25 so as to open the initial first trench 26 and the initial second trench 27, but the initial second trench of the fuse region ( 27) A polyimide film 28 is deposited to cover the sidewalls. As described above, since the depth of the initial second trench 27 is increased through the hard mask 24c, the degree of deposition of the polyimide film 28 on the sidewall is also increased to increase the degree of protection of the insulating film 22. Can be. Thus, cracks in subsequent packaging processes and the like can be prevented.

Subsequently, SWP etching is performed using the polyimide film 28 as an etching barrier. That is, by removing the exposed anti-reflection film 24b in the pad region, the final first trench 26 ′ exposing the metal film 24a is formed, and at the same time, the etch stop film 23 (second insulating film) in the fuse region is formed. If 22b remains, the second insulating film 22b and the etch stop film 23 are removed to form an insulating film of a target thickness on the fuse 21 (in this specification, the first insulating film on the fuse 21). A final second trench 27 'is formed, which leaves the thickness T) of 22a).

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A and 1B are cross-sectional views illustrating a repair / pad etching process according to the prior art.

2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20: substrate 21: fuse

22: insulating film 23: etch stop film

24: pad 25: protective film

26, 27: trench 28: polyimide film

Claims (13)

Forming a fuse in a fuse region on the substrate having a fuse region and a pad region; Forming an insulating film on the resultant including the fuse; Forming a pad in which a metal film, an antireflection film, and a hard mask are stacked in the pad area on the insulating film; Forming a protective film on the resultant including the pad; Performing a repair / pad etching to stop the etching in the anti-reflection film to form a first trench for exposing the anti-reflection film in the pad area, while leaving the insulating film on the fuse at a predetermined thickness Forming a trench; Forming a material layer on the passivation layer to cover sidewalls of the second trench while opening the first trench and the second trench; And Removing the anti-reflection film using the material film as an etching barrier Method for manufacturing a semiconductor device comprising a. The method of claim 1, The insulating film is formed of an oxide-based thin film Method of manufacturing a semiconductor device. The method of claim 1, The second trench forming step, The thickness of the insulating film remaining on the fuse becomes a predetermined target thickness. Method of manufacturing a semiconductor device. The method according to claim 1 or 3, The thickness of the insulating film remaining on the fuse is, Adjusted according to the material of the hard mask or the thickness of the hard mask Method of manufacturing a semiconductor device. The method of claim 1, The material film is made of a polyimide film Method of manufacturing a semiconductor device. The method of claim 1, In the anti-reflection film removing step, The insulating film of the fuse region is further etched until the thickness of the insulating film remaining on the fuse reaches a predetermined target thickness. Method of manufacturing a semiconductor device. Forming a fuse in a fuse region on the substrate having a fuse region and a pad region; Forming a first insulating film, an etch stop film, and a second insulating film on a resultant including the fuse; Forming a pad in which a metal film, an anti-reflection film, and a hard mask are stacked in the pad area on the second insulating film; Forming a protective film on the resultant including the pad; Performing repair / pad etching to stop the etching in the anti-reflection film, thereby forming a first trench in which the anti-reflection film is exposed in the pad area, and forming a second trench in which the etch stop film is left in the fuse area. step; Forming a material layer on the passivation layer to cover sidewalls of the second trench while opening the first trench and the second trench; And Removing the anti-reflection film and at least an etch stop film by using the material film as an etching barrier. Method for manufacturing a semiconductor device comprising a. The method of claim 7, wherein The first insulating film or the second insulating film is formed of an oxide-based thin film Method of manufacturing a semiconductor device. The method of claim 7, wherein The thickness of the first insulating film on the fuse is equal to a predetermined target thickness. Method of manufacturing a semiconductor device. The method according to claim 7 or 9, The etch stop layer is formed of a nitride series thin film Method of manufacturing a semiconductor device. The method according to claim 7 or 9, The second trench forming step, The etching may be stopped at the etch stop layer. Method of manufacturing a semiconductor device. The method according to claim 7 or 9, The second trench depth is adjusted according to the material of the hard mask or the thickness of the hard mask. Method of manufacturing a semiconductor device. The method of claim 7, wherein The material film is made of a polyimide film Method of manufacturing a semiconductor device.
KR1020070110825A 2007-11-01 2007-11-01 Method for manufacturing semiconductor device KR20090044643A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109346453A (en) * 2018-10-08 2019-02-15 长江存储科技有限责任公司 Semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109346453A (en) * 2018-10-08 2019-02-15 长江存储科技有限责任公司 Semiconductor devices

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