KR20090044135A

KR20090044135A - Apparatus for address counting and counting method thereof

Info

Publication number: KR20090044135A
Application number: KR1020070110074A
Authority: KR
Inventors: 강태규
Original assignee: 주식회사 하이닉스반도체
Priority date: 2007-10-31
Filing date: 2007-10-31
Publication date: 2009-05-07

Abstract

An address counting apparatus of the present invention includes a counter including a counter for increasing different external addresses by a predetermined amount and outputting different main addresses, and a plurality of latches for storing the main addresses output from the counter when the external address is changed. It is characterized by including.

In addition, the address counting method of the present invention includes generating and outputting main addresses by increasing the external address by a predetermined amount, and storing the main address generated at the point of change of the external address in the latch unit when the external address is changed; Generating main addresses by increasing the changed address by a predetermined amount, outputting a specific address among the addresses stored in the latch unit and the main addresses generated based on the changed address as an output address, and It characterized in that it comprises the step of repeating the above steps until the output of the.

Address counting

Description

Apparatus for address counting and counting method

The present invention relates to an address counting device used in the operation of a nonvolatile memory device and a counting method thereof.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

Representative operations of the nonvolatile memory device include basic operations such as a program operation, a read operation, an erase operation, and the like, and other application operations include a copyback program operation, a copy2 operation, and a multiplane operation. It is used.

In the case of the basic operation, there is no need to use a plurality of counter values for the calculation of the input address. However, in the case of the melting operation, two or more counter values are required because the address values required for each operation are large.

To meet this need, a multi-counter circuit is in use by copying the same counters used to calculate multiple counter values. However, as several counters that occupy a large area inside the chip are used in the same manner, the size of the chip is relatively increased, and the power consumption increases accordingly.

In order to solve the above problems, an object of the present invention is to provide an improved address counting device that outputs a plurality of addresses required for application operation of a nonvolatile memory device with only one counter.

Another object of the present invention is to provide an address counting method using an improved address counting device.

The address counting apparatus of the present invention for achieving the above object of the present invention is a counter for outputting different main addresses by increasing the external address by a predetermined amount, and the main address output from the counter when the external address is changed, respectively. And a latch unit including a plurality of latches for storing.

In addition, the address counting apparatus of the present invention includes a counter for outputting different main addresses by increasing the external address by a predetermined amount, a latch unit including a plurality of latches for storing the main addresses output from the counter, and the counter And a mux for selectively outputting a specific address among a main address to be output and a plurality of latch addresses output from the latch unit.

In addition, the address counting method of the present invention includes generating and outputting a first group of main addresses by increasing a first external address by a predetermined amount, and when the first external address is changed to a second external address, the second external address. Storing a main address generated at an input point of time in a first latch, generating a second group of main addresses by increasing the second external address by a predetermined amount, and storing an address and a second stored in the first latch And outputting a specific address among the main addresses of the group as an output address.

In addition, the address counting method of the present invention comprises the steps of generating and outputting first main addresses of which the first external address is increased by a predetermined amount, storing the generated first main addresses in a latch unit, and a second external address. Generating second main addresses increased by a predetermined amount, outputting a specific address of the address stored in the latch unit and the second main addresses as an output address, and outputting the output address until completion. And repeating the above steps.

According to the configuration of the present invention described above, when a plurality of addresses are required during various operations of the nonvolatile memory device, a plurality of addresses can be supplied by only one counter. Therefore, the area of the chip can be reduced as compared with the conventional nonvolatile memory device in which a plurality of identical counters are designed and thus, power consumption can be reduced.

On the other hand, the present invention can be applied to other types of semiconductor chip through a design change as well as a nonvolatile memory device, it is possible to supply a variety of addresses at the same time.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and fully scope the scope of the invention to those skilled in the art. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a diagram illustrating an addressing counter device according to an exemplary embodiment of the present invention.

The counter device 100 includes a counter 110 for increasing different external addresses by a predetermined amount and outputting different main addresses, and a plurality of latches for storing the main addresses output by the counter at a change point of the external address, respectively. The latch unit 120 includes a mux 130 for selectively outputting a specific address among a main address output from the counter and a plurality of latch addresses output from the latch unit.

The counter 110 generates various addresses necessary for a basic operation or an application operation of the nonvolatile memory device.

As the counter, various types of counters commonly used may be used. For example, the use of a synchronous counter in which the counting number increases by a certain amount in response to the application of the clock pulse may be used.

In a program operation or a read operation, a column address of a memory cell to be programmed or read is input as a start address, and the value is increased by one. As a result, the memory cells to be programmed or read are sequentially addressed.

However, in the above-described application operations such as copyback program operation, copy2 operation, and multi-plane operation, two or more different addresses are required for each operation, and such addresses need to be output. .

The latch unit 120 includes first to Nth latches 122 to 126, and temporarily stores various addresses output from the counter.

That is, since two or more addresses are required during the application operation, the addresses are temporarily stored. For example, in the case of a copyback operation or a copyto operation, an address of a destination to be copied and an address of a point to be copied are required. In addition, the copyback operation or the copy-to operation is a continuous operation of a read operation and a program operation, and it is necessary to temporarily stop the operation of the counter for a new operation from the outside during the read operation, so that space for temporarily storing an address is required. Done.

As such, the address generated by the counter is stored by designating a specific latch among the plurality of latches.

The latch may be a D latch, an SR latch, a JK latch, or the like.

The counter and each latch are connected via a data bus, and the address generated by the counter is stored in a specific latch.

Each latch is driven by the enable signals enable1 to enableN, and is initialized by the reset signal.

The mux 150 selectively outputs a specific address signal among a main address signal output from the counter or first to Nth address signals stored in the latch.

According to the operation of the nonvolatile memory device, an address signal required is output in response to a selection control signal.

Now, the operation sequence of the counter according to the present invention will be described.

2 is a flowchart illustrating a counting method according to an embodiment of the present invention.

First, a necessary address is input to the counter according to the operation of the nonvolatile memory device (step 210).

The start address required for basic operations such as program operation, read operation, and other application operations is input.

Next, the counter increases the external address by a predetermined amount to generate a main address (step 220).

At this time, the main address generated by increasing the first external address first applied by a predetermined amount is defined as the main address of the first group.

If there is no special change, the main address is output as an output address (steps 230 and 240).

Thereafter, the address output may be completed without any change according to the operation of the nonvolatile memory device (step 242).

However, when the external address is changed, the main address generated by the counter at the time of change is stored in the latch unit (steps 230 and 250).

At this time, the changed external address is called a second external address, and the main address generated at the time of application of the second external address is stored in the first latch of the latch unit.

Generalizing this, the main address generated upon application of the N + 1th external address is stored in the Nth latch of the latch portion.

The address stored in the Nth latch is called an Nth latch address.

The change of the external address is determined by the operation of the nonvolatile memory device. In the basic operation mentioned above, the address incremented by the counter can be output without changing the external address.

However, in the case of the application operation or the like, since a new address is inputted to the counter, it is necessary to store the address calculated by the counter before inputting a new address.

Next, the changed address is incremented by a predetermined amount to generate a main address (step 260).

At this time, the main address generated by increasing the second external address by a predetermined amount is defined as a main address of the second group.

If there is no special change, a specific address is selectively output from the latch address stored in the latch unit and the main address generated by incrementing the changed address (second external address) (steps 270 and 280).

This is controlled by the selection control signal applied to the mux 130.

Thereafter, the address output may be completed without any change according to the operation of the nonvolatile memory device (step 282).

However, when the external address is changed, the address output from the counter at the time of change is stored in the latch unit (steps 270 and 250).

The steps 250 to 282 are continuously repeated depending on whether or not the external address is changed. In general, when N external address changes occur, that is, when N + 1 external addresses are input, N main address latching operations occur.

The N + 1 group main addresses generated by increasing the last applied N + 1 external address and a specific address among the first to Nth latch addresses are selectively output.

Description of the main parts of the drawing

100: address counting device

110: counter

120: latch portion

130: mux

Claims

A counter for outputting different main addresses by increasing the external address by a predetermined amount;

And a latch unit including a plurality of latches, each of which stores a main address output from the counter when a change of the external address occurs.

The address counting apparatus of claim 1, further comprising a mux for selectively outputting a specific address among a main address output from the counter and a plurality of latch addresses output from the latch unit.

The address counting apparatus of claim 1, wherein the latch unit comprises N latches respectively storing main addresses output from the counter at input points of different N + 1 external addresses.

The address counting device of claim 1, wherein the latch unit outputs N different latch addresses.

Generating and outputting a first group of main addresses by increasing the first external address by a predetermined amount;

When the first external address is changed to a second external address, storing a main address generated at the time of input of the second external address in a first latch;

Generating a second group of main addresses by increasing the second external address by a predetermined amount;

And outputting a specific address of an address stored in the first latch and a main group of a second group as an output address.

The method of claim 5, further comprising: storing the main address generated at the time of input of the third external address in the second latch when the second external address is changed to the third external address;

Generating a third group of main addresses by increasing the third external address by a predetermined amount;

And outputting a specific address of an address stored in the first latch, an address stored in the second latch, and a third group of main addresses as an output address.

Generating and outputting first main addresses in which the first external address is increased by a predetermined amount;

Storing the generated first main addresses in a latch unit;

Generating second main addresses of which the second external address is incremented by a predetermined amount;

Outputting a specific address of an address stored in the latch unit and the second main addresses as an output address;

And repeating the steps until the output of the output address is completed.

A latch unit including a plurality of latches respectively storing a main address output from the counter;

And a mux for selectively outputting a specific address among a main address output from the counter and a plurality of latch addresses output from the latch unit.