KR20090044004A - Array substrate for liquid crystal display device - Google Patents

Abstract

According to an aspect of the present invention, there is provided a semiconductor device comprising: a first gate wiring extending in one direction on a substrate; a data wiring defining a first pixel region crossing the first gate wiring; A source electrode connected to the first gate line and the data line and having a gate electrode in the pixel region, a source electrode having a concave portion overlapping with the gate electrode and symmetrical with each other, and a symmetrical structure inserted into the concave portion A first thin film transistor comprising a first and a second drain electrode having a first thin film transistor; An array substrate including a pixel electrode formed in the pixel area while simultaneously contacting the first and second drain electrodes of the first thin film transistor.

Array board, liquid crystal, data wiring, sharing, parasitic capacitance

Description

Array substrate for liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device having a data line sharing structure for driving two pixels with one data line to reduce a driving IC. .

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Among the liquid crystal display devices, an active matrix liquid crystal display device having a thin film transistor, which is a switching element that can control voltage on and off for each pixel, has the best resolution and video performance. I am getting it.

In general, an LCD device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming a thin film transistor and a pixel electrode, and a color filter substrate manufacturing process for forming a color filter and a common electrode, and between the two substrates. It completes through the cell process through liquid crystal in the process.

In more detail, referring to FIG. 1, which is an exploded perspective view of a general liquid crystal display device, as illustrated, the array substrate 10 and the color filter substrate 20 face each other with the liquid crystal layer 30 interposed therebetween. The array substrate 10 of the lower part includes a plurality of gate lines 14 and data lines 16 arranged vertically and horizontally on the upper surface of the transparent substrate 12 to define a plurality of pixel regions P. Thin film transistors T are provided at the intersections of the two wires 14 and 16 so as to correspond one-to-one with the pixel electrodes 18 provided in the pixel regions P. FIG.

In addition, the upper color filter substrate 20 facing the array substrate 10 is a rear surface of the transparent substrate 22, and the non-display of the gate wiring 14, the data wiring 16, the thin film transistor T, and the like. A grid-like black matrix 25 is formed around the pixel region P so as to cover the region, and red (R) and green are sequentially arranged in order to correspond to the pixel region (P) in the grid. A color filter layer 26 including (G) and blue (B) color filter patterns 26a, 26b, and 26c is formed, and is transparent over the entire surface of the black matrix 25 and the color filter layer 26. The common electrode 28 is provided.

Although not shown in the drawings, each of the two substrates 10 and 20 is sealed with a sealant or the like along the edge to prevent leakage of the liquid crystal layer 30 interposed therebetween. 10 and 20 are interposed between upper and lower alignment layers that provide reliability in the molecular alignment direction of the liquid crystal at a boundary portion of the liquid crystal layer 30, and at least one outer surface of each substrate 10 and 20 is provided with a polarizing plate. have.

In addition, a back-light is provided on the outer surface of the array substrate 10 to supply light, and the on / off signal of the thin film transistor T is transmitted to the gate wiring 14. When the image signal of the data wiring 16 is transferred to the pixel electrode 18 of the selected pixel region P by being sequentially scanned and applied, the liquid crystal molecules are driven by the vertical electric field therebetween, and thus the transmittance of light Various images can be displayed by a change.

On the other hand, in the liquid crystal display device configured as described above, the number of gates and data lines increases as the area and the resolution become larger, and the number of driving circuits increases accordingly. In particular, in recent years, digital broadcasting has been activated, and an image display device having an area ratio (horizontal: vertical) of 16: 9 is mainly used. As a result, an increase in data wiring is increasing more rapidly than an increase in gate wiring. And a method for reducing the number of driving circuits related thereto have been sought, and a technique for driving two pixel areas with one data line has been proposed.

This technique is a method of flickering a thin film transistor to generate a signal application time deviation to a pixel electrode in a pixel region connected to the data line at the same time so that a sequential data signal is comprehensively applied.

FIG. 2 is a schematic diagram illustrating a part of a display area of a general array substrate in which data lines drive two pixel regions, and FIG. 3 illustrates sharing of data lines in a general array substrate in which data lines drive two pixel regions. A plan view of two pixel areas.

As shown in the drawing, the first and second gate lines 43a and 43b adjacent to each other are separated by one group n-1 and n, and extend in one direction. , a common wiring 47 is formed between n). In addition, the data line 60 defining the pixel areas P1 and P2 is extended to intersect the group gate lines n-1 and n. In this case, the data line 60 is adjacent to the data line 60. The left and right pixel areas P1 and P2 share the data line 60 to receive a signal voltage. Further, thin film transistors Tr1 and Tr2 each having a gate electrode 45, a gate insulating film (not shown), a semiconductor layer (not shown), and source and drain electrodes 62 and 65 are formed in each pixel region P1 and P2. And a drain electrode 65 of the thin film transistors Tr1 and Tr2 and a pixel electrode 70.

In this case, in the case of two neighboring pixel regions P1 and P2 sharing one data line 60, the thin film transistors Tr1 and Tr2 driving the pixel electrodes 70 in the pixel regions P1 and P2, respectively. It can be seen that the formation position of the) is different. That is, the thin film transistor (hereinafter referred to as the first thin film transistor Tr1) in the pixel area (hereinafter referred to as the first pixel area P1) positioned on the left side of the data line 60 is referred to as the n-1 group ( is connected to the first gate line 43a of n-1 and formed on the upper right side in the first pixel region P1 and is located in the pixel region (hereinafter referred to as the second pixel region P2) located on the right side. The thin film transistor (hereinafter referred to as a second thin film transistor Tr2) is connected to the second gate wire 43b of the nth group n and is formed on the lower left side of the second pixel region P2.

However, in the case of the array substrate 41 having the structure described above, the gate layer and the data line 60 for forming the gate lines 43a and 43b and the gate electrode 45 during the manufacturing process thereof. ) And a thin film transistor Tr between the two pixel areas P1 and P2 when the source layer is formed in the vertical direction or the left or right direction due to the deviation in forming the source layer for forming the source and drain electrodes 62 and 65. , Cgs (parasitic capacitance due to overlapping of the gate electrode and the drain electrode), which is a parasitic capacitance of Tr2, is generated by a difference of twice as much as the degree of twisting between the adjacent first and second pixel regions P1 and P2. . That is, referring to FIG. 2, when the source layer is formed to be biased upward with respect to the gate layer due to the patterning deviation, the first thin film transistor Tr1 is positioned on the upper right side in the first pixel region P1. Whereas the region where the drain electrode 65 overlaps with the gate electrode 45 increases, in the second pixel region P2, the bar drain electrode 65 in which the second thin film transistor Tr2 is positioned on the lower left side is gated. As the area overlapping with the electrode 45 is reduced, a difference occurs between Cgs in the first pixel area P1 and the second pixel area P2. In this case, ΔVp (feed through voltage) magnitude difference occurs for each pixel region due to the parasitic capacitance difference, which causes a difference in the data signal voltage applied between the two pixel regions P1 and P2 and thus the luminance difference. Occurs and finally the image quality is deteriorated.

SUMMARY OF THE INVENTION The present invention has been proposed for the purpose of solving the above-described problem, and in the data wiring sharing structure array substrate according to the present invention, even if a distortion occurs due to a patterning error when the gate layer and the data layer are formed, the data wiring is mutually separated. Providing an array substrate capable of preventing the display quality caused by the parasitic capacitance from deteriorating due to the difference in parasitic capacitance caused by the difference in the overlapping region between the gate electrode and the drain electrode between the shared pixel regions. The purpose.

An array substrate according to the present invention comprises: a first gate wiring extending in one direction on a substrate; A data line crossing the first gate line and defining a first pixel area; A source electrode connected to the first gate line and the data line, the source electrode having a gate electrode in the pixel region, first and second concave portions overlapping with the gate electrode and symmetrical with each other; A first thin film transistor inserted into the second recessed portion and including first and second drain electrodes having symmetrical structures; And a pixel electrode in contact with the first and second drain electrodes of the first thin film transistor and formed in the pixel region.

The first thin film transistor includes a gate insulating film sequentially stacked between the gate electrode, the source, and the first and second drain electrodes, an active layer, and first, second and third ohmic contact layers spaced apart from each other. The source electrode is formed on the second ohmic contact layer, and the first and second drain electrodes are formed on the first and third ohmic contact layers, respectively.

The first and second recesses have a symmetrical structure with respect to the longitudinal direction of the data line with respect to the center of the gate electrode.

A second gate wiring extending in parallel with the first gate wiring and defining a second pixel region by crossing with the data wiring, and connected to the second gate wiring and the data wiring; A second thin film transistor having a same structure as that of the first thin film transistor and connected to the second gate line and the data line is further configured in an area, wherein the first and second pixel areas share the data line. Is characteristic.

A protective layer having first and second drain contact holes exposing the first and second drain electrodes, respectively, is further formed on the first thin film transistor.

The first pixel region has a shape that surrounds three surfaces inwardly, and common wiring connected to each other between adjacent pixel regions is further formed. The pixel electrode is formed by overlapping with the common wiring, so that the overlapped portions are stored. It is characterized by forming a capacitor.

The data wiring sharing structure array substrate according to the present invention comprises a source electrode having concave portions which are symmetrical with respect to one gate electrode in each pixel region, and is inserted into the concave portions. By constructing a thin film transistor having a structure in which the structure is configured to be effective, it is possible to fundamentally prevent the change of the parasitic capacitance caused by the distortion of the gate layer and the source layer, and furthermore, the display quality due to the parasitic capacitance change in each pixel region. It is effective in preventing a decrease.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a plan view of two pixel regions in which data lines share data lines in an array substrate in which data lines drive two pixel regions according to an exemplary embodiment of the present invention.

As illustrated, the array substrate 101 according to the present invention has a plurality of gate wiring groups n and n + 1 having one group of adjacent first and second gate wirings 105a and 105b as one group. A plurality of data lines 138 intersect with the plurality of gate line groups n and n + 1 to define pixel regions P1 and P2. In this case, for convenience of description, the first pixel area P1 positioned on the left side of the data line 138 and the second pixel region P2 positioned on the right side are defined.

The common wiring 109 surrounds three surfaces of the pixel areas P1 and P2 and is connected to each other between the adjacent pixel areas P1 and P2 in the pixel areas P1 and P2. .

In addition, thin film transistors Tr1 and Tr2, which are switching elements connected to the first or second gate wires 105a and 105b and simultaneously connected to the data wires 138, are formed in each pixel area P1 and P2. It is becoming. In this case, the most characteristic configuration of the present invention is that the thin film transistors Tr1 and Tr2 formed in each of the pixel areas P1 and P2 are positioned at an upper center part or a lower center part in the pixel areas P1 and P2. In particular, among the components constituting the thin film transistors Tr1 and Tr2, the drain electrode 142 is symmetrically with respect to the center of the thin film transistors Tr1 and Tr2 to the first and second drain electrodes 142a and 142b. It is characterized by being divided. In addition, each of the pixel regions P1 and P2 having such a configuration is connected to the two drain electrodes 142a and 142b, respectively, and a pixel electrode 155 is formed.

In more detail, the structures of the first and second pixel regions P1 and P2, which are located on the left and right sides of the data line 138 and are jointly applied with a signal voltage by the data line 138. In the drawings, the first gate wiring 105a is positioned above the second gate wiring 105b and the first gate wiring 105b defines the pixel regions P1 and P2. It can be seen that 105a belongs to the n + 1th group n + 1 and the second gate line 105b belongs to the nth group n.

Through this configuration, the first pixel region P1 is associated with the first gate wiring 105a and the second pixel region P2 only with the second gate wiring 105b, and the respective pixel regions P1 and P2. Also in the thin film transistors Tr1 and Tr2 in the first and second thin film transistors Tr1 and Tr2, the first thin film transistor Tr1 formed in the first pixel region P1 is connected to the first gate line 105a and the second pixel region P2. The second thin film transistor Tr2 formed therein is connected to the second gate line 105b. Therefore, due to this structural feature, the first thin film transistor Tr1 in the first pixel region P1 is positioned below and the second thin film transistor Tr2 in the second pixel region P2 is positioned above.

Meanwhile, the structure of the thin film transistors Tr1 and Tr2 formed in the pixel areas P1 and P2 will be described. The first and second pixel areas P1 may be formed from the first and second gate lines 105a and 105b, respectively. The source electrode 140 having the first and second concave portions A1 and A2 formed in a symmetrical structure overlapping with the gate electrode 107 is formed by branching the gate electrode 107 into the P2. It is connected to the data connection pattern 139 branched from the data line 138 and is formed to be inserted into the first concave portion and the second concave portion (A1, A2), respectively, symmetrically the first and the first It is a feature that two drain electrodes 142a and 142b are formed.

Due to this structural feature, the common wiring 109 formed in each of the pixel regions P1 and P2 may be formed on the surface on which the first or second gate wirings 105a and 105b are formed. The common wiring 109 having such a structure is not formed but is formed only on the other three surfaces, and the first and second drain electrodes 142a and 142b divided into two in each of the pixel regions P1 and P2. ) And the pixel electrode 155 formed while simultaneously contacting through the first and second drain contact holes 152a and 152b to form the storage capacitor StgC.

In the case of the array substrate 101 having the above-described structure, the gate layer including the gate lines 105a and 105b, the gate electrode 107, and the common line 109, the data line 138, the source and drain electrodes The first and second drain electrodes 142a and 142b in the pixel areas P1 and P2 may be formed even if they are formed upside down or left / right in the process of forming the source layer including the 140 and 142. Since the overlapping regions of the gate electrode 107 are compensated with each other, the parasitic capacitance Cgs becomes the same size in each of the pixel regions P1 and P2. The display quality degradation caused by changing the size of the parasitic capacitance Cgs for each of the regions P1 and P2 does not occur.

For example, when the source layer is formed to be biased upward or downward with respect to the gate layer, there is no change in the parasitic capacitance Cgs, and when formed to the left, the pixel regions P1 and P2 are formed. The portion where the first drain electrode 142a positioned on the left side overlaps with the gate electrode 107 becomes smaller, whereas the region where the second drain electrode 142b formed on the right side overlaps with the gate electrode 107 As it extends, the area of the first and second drain electrodes 142a and 142b substantially overlapping with the gate electrode 107 is not changed. The gate electrodes 107 and the first and second drain electrodes 142a are not changed. , 142b) can be seen that there is no change in the size of the parasitic capacitance (Cgs) generated by overlapping.

Therefore, in the case of the array substrate 101 according to the present invention, the gate layer generated by the patterning error in the data line 138 and the first and second pixel regions P1 and P2 to which the signal voltage is applied. And display quality deterioration due to a change in the parasitic capacitance (Cgs) size due to the distortion between the data layers.

Hereinafter, the cross-sectional structure of the array substrate according to the present invention having the planar structure described above will be described.

5 is a cross-sectional view of a portion taken along the cutting line V-V of FIG. 4. In this case, since the cross-sectional structure is the same in the first pixel area and the second pixel area, only the first pixel area will be described. For convenience of description, an area in which a thin film transistor is formed in each pixel area is defined as a switching area.

As illustrated, a first gate wiring (not shown) extends in one direction on the transparent insulating substrate 101, and a gate electrode 107 is formed by branching from the first gate wiring (not shown). The common wiring (not shown) is connected to the adjacent pixel region P1 on the same layer, and is formed to surround three surfaces at the inner edge of each pixel region P1.

In addition, a gate insulating layer 112 is formed on the entire surface of the first gate wiring (not shown), the common wiring (not shown), and the gate electrode 107, and the switching region TrA is disposed on the gate insulating layer 112. The active layer 120 of pure amorphous silicon is formed in correspondence with the gate electrode 107, and the ohmic contact layers 123a, 123b, and 123c of impurity amorphous silicon are spaced apart from each other on the active layer 120. It is. In this case, the ohmic contact layers 123a, 123b, and 123c may be divided into three parts in the switching region TrA and include first, second, and third ohmic contact layers 123a, 123b, and 123c. It is characteristic.

In addition, the first and the second portions of the ohmic contact layers 123a, 123b, and 123c divided into three parts are symmetrical with each other on the second ohmic contact layer 123b formed corresponding to the central portion of the gate electrode 107. Source electrodes 140 having two recesses A1 and A2 are formed, and the first and second ohmic contact layers 123a and 123c are formed on both sides of the source electrode 140, respectively. The first drain electrode 142a and the second drain electrode 142b are formed to correspond to the entrances A1 and A2.

In addition, first and second drain contact holes 152a and 152b exposing the first and second drain electrodes 142a and 142b over the source electrode 140 and the first and second drain electrodes 142a and 142b. Is formed on the passivation layer 150 and simultaneously contacts the first and second drain electrodes 142a and 142b through the first and second drain contact holes 152a and 152b. In this case, the pixel electrode 155 is formed to overlap the common wiring (not shown) formed to surround three surfaces inside the pixel region P1, so that the overlapped portion is a storage capacitor (not shown). The array substrate 101 according to the embodiment of the present invention is completed.

1 is an exploded perspective view schematically illustrating a configuration of a general liquid crystal display device.

2 is a schematic diagram schematically showing a part of a display area of a general array substrate in which data wirings drive two pixel areas;

3 is a plan view of two pixel regions in which a data line shares two data lines in a general array substrate driving two pixel regions.

4 is a plan view of two pixel regions in which data wirings share data wirings in an array substrate in which data wirings drive two pixel regions according to an embodiment of the present invention;

FIG. 5 is a cross-sectional view of a portion taken along the line V-V of FIG. 4. FIG.

<Description of Symbols for Main Parts of Drawings>

105a, 105b: first and second gate wiring

107: gate electrode

140: source electrode

142a, 142b: first and second drain electrodes

152a, 152b: first and second drain contact holes

155 pixel electrode

A1, A2: first and second recesses

P1, P2: first and second pixel areas

Tr1, Tr2: first and second thin film transistors

n, n + 1: gate wiring group

Claims (9)

A first gate wiring extending in one direction on the substrate; A data line crossing the first gate line and defining a first pixel area; A source electrode connected to the first gate line and the data line, the source electrode having a gate electrode in the pixel region, first and second concave portions overlapping with the gate electrode and symmetrical with each other; A first thin film transistor having a first drain and a second drain electrode respectively inserted in the second recess and having a symmetrical structure; A pixel electrode formed in the pixel region in contact with the first and second drain electrodes of the first thin film transistor Array substrate comprising a. The method of claim 1, The first thin film transistor may further include a gate insulating layer sequentially stacked between the gate electrode, the source, and the first and second drain electrodes, an active layer, and first, second, and third ohmic contact layers spaced apart from each other. . The method of claim 2, And the source electrode is formed on the second ohmic contact layer, and the first and second drain electrodes are formed on the first and third ohmic contact layer, respectively. The method of claim 1, And the first and second recessed portions have a symmetrical structure with respect to the longitudinal direction of the data line with respect to the center of the gate electrode. The method of claim 2, A second gate wiring extending in parallel with the first gate wiring and defining a second pixel region by crossing with the data wiring; A second thin film transistor connected to the second gate line and the data line and further connected to the second gate line and the data line and having the same structure as the first thin film transistor in the second pixel area. In-array substrate. The method of claim 5, wherein And the first and second pixel regions share the data line. The method of claim 1, And a passivation layer on the first thin film transistor, the passivation layer having first and second drain contact holes that expose the first and second drain electrodes, respectively. The method of claim 1, And a common wiring connected to each other between adjacent pixel areas, wherein the first pixel area surrounds three surfaces. The method of claim 8, And the pixel electrode is formed to overlap the common wiring so that the overlapped portion forms a storage capacitor.

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