KR20090043940A - Method for forming de-coupling capacitor of a semiconductor memory device - Google Patents

Abstract

The present invention discloses a method of forming a decoupling capacitor of a semiconductor memory device that applies a decoupling capacitor to a leaf cell formed in a peripheral circuit region, wherein the disclosed semiconductor memory device is formed on an adjacent N-type well region and a P-type well region, respectively. A first electrode formed in at least one of the transistor elements and the N-type well region and the P-type well region, and including a first electrode and a source and a drain connected in common; and a second electrode formed as a gate; The first electrode is connected to the source of the transistor element in its well region, and the second electrode comprises decoupling capacitors formed connected to the source of the transistor element in another neighboring well region.

Description

A method of forming a decoupling capacitor of a semiconductor memory device {METHOD FOR FORMING DE-COUPLING CAPACITOR OF A SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a semiconductor memory device in which a decoupling capacitor is applied to a leaf cell formed in a peripheral circuit region.

Semiconductor memory devices, such as DRAMs, employ capacitors not only for memory cell arrays, but also for stable power supply or stabilization of transmitted signals, and in particular for the purpose of stabilizing voltages from factors such as noise. It has a decoupling capacitor disposed in the free space of the region.

The decoupling capacitor removes high frequency noise on the power supply or provides auxiliary power to the device, and excludes inductance components generated when the device is connected to the external power supply. It plays a role in improving impedance.

In the case of a semiconductor memory device, a MOS capacitor having a large capacitor capacity in a small area is generally formed as a decoupling capacitor.

1 illustrates an example in which the above-described decoupling capacitor is formed. Referring to FIG. 1, a decoupling capacitor 10 is formed in the peripheral circuit region 5, and the decoupling capacitor 10 is a distributed leaf cell ( It is formed between the leaf cells (12). Here, the leaf cell 12 refers to a circuit block composed of predetermined elements capable of performing a minimum logic function.

The decoupling capacitor 10 should be formed in a large space in order to secure sufficient capacity, but as the semiconductor device becomes more integrated, the space for forming the decoupling capacitor 10 in the peripheral circuit region 5 gradually decreases. Therefore, there is a problem that it becomes increasingly difficult to form the decoupling capacitor 10 in the semiconductor memory device to have a sufficient capacity.

In addition, as shown in FIG. 1, when the distance between the leaf cell 12 and the decoupling capacitor 10 is far from each other, the decoupling capacitor 10 is difficult to play a sufficient role due to a problem such as delay with respect to the leaf cell 12. There is this.

In addition, the level of power supplied to the leaf cell 12 is temporarily lowered by the temporary unstable power supply, so that the performance of the device provided in the leaf cell 12 may be degraded.

In addition, as the size of the semiconductor memory device becomes smaller and smaller, the size of the leaf cell 12 is required to be smaller. Accordingly, the leaf cell 12 uses unit cell frames having an optimized standard layout. To be configured.

Referring to FIG. 2, one leaf cell 20 is conventionally defined as a standardized unit cell frame including an N type well region 22 and a P type well region 24, and each well region 22, Elements 24 such as MOS transistors NM and PM are disposed in 24.

As shown in FIG. 2, when the MOS transistors PM and NM having different widths are disposed in the leaf cell 20, the regions indicated by dotted lines in the region except for the region where the MOS transistors PM and NM are disposed ( 26, 28) such as free space occurs.

Since the free spaces 26 and 28 cause the uniformity of the pattern (gate or power wiring, etc.), the patterns of the elements may be deformed or processed in a subsequent process such as chemical mechanical polish (CMP). It acts to reduce margins.

The present invention provides a semiconductor device having a decoupling capacitor, and in particular, provides a capacitance required for the device by forming the decoupling capacitor in the leaf cell.

In addition, the present invention provides a method of forming a semiconductor memory device capable of ensuring the uniformity of the pattern in the leaf cell by the decoupling capacitor.

 A semiconductor memory device of the present invention includes transistor elements formed on adjacent N-type well regions and P-type well regions, respectively; And a first electrode formed in at least one of the N-type well region and the P-type well region, the first electrode having a source and a drain connected in common, and a second electrode formed of a gate. And decoupling capacitors connected to a source of the transistor element in its well region and the second electrode is connected to a source of the transistor element in another neighboring well region.

The second electrode of the decoupling capacitor is preferably connected to a source node of an adjacent well region through at least one contact connected to one common gate line.

In addition, the source of the transistor elements is preferably connected to a common wiring.

The second electrode of the decoupling capacitor on the N-type well region is preferably supplied with a power supply voltage level from a source node of a neighboring P-type well region.

Similarly, the second electrode of the decoupling capacitor on the P-type well region is preferably supplied with a ground voltage level from a source node of a neighboring N-type well region.

In addition, the wiring making contact with the source of the transistor element is preferably extended to overlap the gate of the decoupling capacitor of the neighboring well region.

A method of forming a decoupling capacitor of a semiconductor memory device of the present invention comprises: arranging transistor elements on an N-type well region and a P-type well region adjacent to each other; Disposing a decoupling capacitor having a first electrode and a second electrode in at least one of the N-type well region and the P-type well region; A first electrode of the decoupling capacitor makes an electrical connection with a source of a transistor in its well region; The second electrode is characterized by making an electrical connection with a source of a transistor in another neighboring well region.

Among these, the decoupling capacitor is laid out as a MOS transistor type capacitor, the source and the drain in common to form the first electrode, the gate is preferably the second electrode.

The second electrode may be in contact with a wiring contacting the source of the transistor element in another neighboring well region extending to its own region.

In addition, the wiring may be in contact with the common wiring.

The present invention increases the total capacity of the decoupling capacitors disposed in the semiconductor memory device by arranging the decoupling capacitors in the free space in the leaf cells, thereby reducing the distance between the devices provided and the decoupling capacitors, thereby reducing power from factors such as noise. It can be stabilized to improve the performance of the device.

In addition, the decoupling capacitor increases the density in the leaf cell and makes the pattern uniform to ensure physical stability corresponding to the process.

The present invention forms a decoupling capacitor in the remaining region after the transistor elements are disposed in the N-type and P-type well regions of the leaf cell mainly formed in the peripheral circuit region. Therefore, power is supplied to the transistor elements in an auxiliary manner, the stability of the power source is prevented from such factors as noise, and the density inside the leaf cell is increased to secure physical stability corresponding to the process.

Specifically, referring to FIG. 3, the leaf cell of the semiconductor memory device of the present invention includes an N type well region N_WELL and a P type well region P_WELL, and the N type well region N_WELL has various widths. PMOS transistors PM are formed in a finger structure, and NMOS transistors NM having various widths are formed in a finger structure in the P-type well region P_WELL.

3 illustrates only a portion of the N-type well region N_WELL and the P-type well region P_WELL constituting one leaf cell, and the PMOS transistors PM and the NMOS transistors NM form logic. Transistor elements are referred to as 'S', a drain node 'D' and a gate node 'G' of each MOS transistor.

Each of the PMOS and NMOS transistors PM and NM is electrically connected to a metal line (not shown) through a contact C1 and is supplied with a power supply (or ground) voltage.

PMOS transistors PM having different channel sizes are disposed in the N-type well region N_WELL of the leaf cell, and at least one decoupling capacitor PM_DC is formed in the region 26 except for this.

Similarly, NMOS transistors NM having different channel sizes are disposed in the P-type well region P_WELL, and at least one decoupling capacitor NM_DC is formed in the region 28 except for this.

In detail, the decoupling capacitor PM_DC of the N-type well region N_WELL extends the source node of the PMOS transistor PM located on its extension line in the same N-type well region N_WELL so as to extend the first of the decoupling capacitor PM_DC. Form an electrode.

The drain node of the decoupling capacitor PM_DC is electrically connected to the first electrode of the decoupling capacitor PM_DC by the contact C4 through the common source node CS1, and the gate of the decoupling capacitor PM-DC is one. A plurality of pads are integrally coupled to the common gate wiring of the decoupling capacitor (PM-DC) and are formed of a second electrode (poly layer).

Similarly, the decoupling capacitor NM_DC of the P-type well region P_WELL extends the source node of the NMOS transistor NM located on its extension line in the same P-type well region P_WELL to extend the first electrode of the decoupling capacitor NM_DC. To form.

The drain node of the decoupling capacitor NM_DC is electrically connected to the first electrode of the decoupling capacitor NM_DC by the contact C5 through the common source node CS2, and the gate of the decoupling capacitor NM-DC is one. A plurality of pads are integrally coupled to a common gate wiring of the second coupling electrode (NM-DC) to form a second electrode (poly layer, bold line).

In addition, the second electrode of the decoupling capacitor PM_DC of the N-type well region N_WELL has a decoupling capacitor having a source node of an NMOS transistor NM of the P-type well region P_WELL adjacent to each other via a contact C2. By being electrically connected to the first electrode of NM_DC to receive the power supply voltage, the voltage of the power supply voltage level can be charged and supplied to the transistor elements in the leaf cell.

Similarly, the second electrode of the decoupling capacitor NM_DC of the P-type well region P_WELL is a decoupling capacitor of which the source node of the PMOS transistor PM of the adjacent N-type well region N_WELL is extended through the contact C3. By being electrically connected to the first electrode of the PM_DC to receive the ground voltage, the voltage of the ground voltage level can be charged and supplied to the transistor elements in the leaf cell.

Here, it is preferable that the wirings (first and second electrodes) coupled with the source node of the transistor element extend so as to overlap with the gate of the decoupling capacitor in the well region.

In addition, the plurality of transistor elements NM and PM and the decoupling capacitors NM_DC and PM_DC of the leaf cell 30 of the present invention may be configured as shown in FIG. 4. Compared with FIG. 2, it can be seen that the transistor devices NM and PM are disposed in the leaf cell and the remaining free space is filled with the decoupling capacitors NM_DC and PM_DC of the present invention.

In addition, the decoupling capacitors NM_DC and PM_DC may know that a plurality of pads may be integrally coupled to one common gate area.

As described above, the leaf cell of the semiconductor memory device of the present invention supplies a power supply (or ground) voltage from an extended source node of a MOS transistor in a well region adjacent to decoupling capacitors PM-DC and NM-DC. As a receiving structure, there is no need to further provide a wiring for supplying a power (or ground) voltage from the outside.

The semiconductor memory device of the present invention has a structure in which a decoupling capacitor is disposed in a free space in a leaf cell, thereby increasing the total capacity of the decoupling capacitor included in the semiconductor device.

In addition, since the interval between the transistor elements and the decoupling capacitors that make up the logic is narrowed, the auxiliary power may be sufficiently supplied from the decoupling capacitor to the transistor elements within an early time, thereby improving performance of the transistor elements.

In addition, the high frequency noise on the power supply is removed by the decoupling capacitor, and the inductance component generated when the external power supply is connected to the device is excluded, thereby improving the impedance viewed from the external power supply.

Then, as the unnecessary free space in the leaf cell is filled with the poly gate and the active region constituting the decoupling capacitor, the gate threshold line width becomes regular, so that a margin of a subsequent process such as CMP can be sufficiently secured.

1 is a diagram showing an arrangement of decoupling capacitors in a conventional semiconductor memory device.

2 shows a leaf cell of a conventional semiconductor memory device.

3 is a layout diagram showing a preferred embodiment of a leaf cell of a semiconductor memory device according to the present invention;

4 is an exemplary layout diagram of one leaf cell implemented by applying an embodiment of the present invention.

Claims (10)

Transistor elements formed on adjacent N-type well regions and P-type well regions, respectively; And Is formed in at least one of the N-type well region and the P-type well region, A first electrode formed by connecting a source and a drain in common; A second electrode formed of a gate; The first electrode is connected to a source of the transistor element in its well region, The second electrode may include decoupling capacitors connected to a source of the transistor element in another neighboring well region; Semiconductor memory device comprising a. The method of claim 1, And the second electrode of the decoupling capacitor is connected to a source node in an adjacent well region through at least one contact connected to one common gate wiring. The method of claim 1, And a source of the transistor elements is connected to a common wiring. The method of claim 1, The second electrode of the decoupling capacitor on the N-type well region A semiconductor memory device receiving power of a power supply voltage level from source nodes in neighboring P-type well regions. The method of claim 1, The second electrode of the decoupling capacitor on the P-type well region A semiconductor memory device receiving ground voltage level power from a source node in a neighboring N-type well region. The method of claim 3, wherein And a wiring contacting the source of the transistor element extends overlapping with a gate of the decoupling capacitor in a neighboring well region. Disposing transistor elements on the N type well region and the P type well region adjacent to each other; Disposing a decoupling capacitor having a first electrode and a second electrode in at least one of the N-type well region and the P-type well region; A first electrode of the decoupling capacitor makes an electrical connection with a source of a transistor in its well region; And a second electrode is in electrical connection with a source of a transistor in another neighboring well region. The method of claim 7, wherein And the decoupling capacitor is laid out as a MOS transistor type capacitor, the source and the drain form the first electrode in common, and the gate forms the second electrode. The method of claim 7, wherein And a second electrode of the decoupling capacitor makes contact with a wiring contacting a source of the transistor element in another neighboring well region extending to its region. The method of claim 9, And a wiring line crossing the common line to make a contact.

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