KR100958801B1 - Semiconductor device including reservoir capacitor and layout method for the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a reserve capacitor and a layout method thereof, wherein a leaf cell is defined including an N type well region and a P type well region, and formed in the N type well region and the P type well region, respectively. And devices receiving a voltage through the first voltage line; And at least one reservoir capacitor formed in at least one of the N-type well region and the P-type well region, and configured to charge and supply the voltage supplied through the second voltage line to the devices. .

Reserve, Capacitor, Semiconductor, Layout

Description

A semiconductor device having a reserve capacitor and a layout method therefor {SEMICONDUCTOR DEVICE INCLUDING RESERVOIR CAPACITOR AND LAYOUT METHOD FOR THE SAME}

1 is a view showing the arrangement of a reserve capacitor in a conventional semiconductor device.

2 is a diagram showing a layout structure of a leaf cell of a conventional semiconductor device.

3 is a view showing a layout structure of a leaf cell of a semiconductor device according to the present invention.

4A is a view showing an example of a layout structure of a reserve capacitor provided in a leaf cell of a semiconductor device according to the present invention.

4B is a view showing another example of a layout structure of a reserve capacitor provided in a leaf cell of a semiconductor device according to the present invention.

5 is a view showing a layout structure of a leaf cell including a reserve capacitor having a power supply therein in a semiconductor device according to the present invention;

FIG. 6 illustrates a partial layout structure of a leaf cell including a reserve capacitor having an external power supply connection in the semiconductor device according to the present invention; FIG.

FIG. 7 illustrates a partial layout structure of a leaf cell including a reserve capacitor formed at a position of an input (or output) terminal 70 in the semiconductor device according to the present invention. FIG.

The present invention relates to a semiconductor device of the present invention, and more particularly, to a semiconductor device having a reserve capacitor and a layout method thereof.

Generally, in a semiconductor device such as DRAM, reservoir capacitors are disposed in a free space in a peripheral area of a memory cell to stabilize voltage from noise.

That is, the conventional semiconductor device has a structure in which a reserve capacitor 14 is disposed between two adjacent leaf cell groups 10 and 12, as shown in FIG. Here, the leaf cell refers to a circuit block composed of predetermined elements capable of performing a minimum logic function.

However, as the semiconductor device becomes more integrated, the free space between two adjacent leaf cell groups 10 and 12 may be reduced, thereby reducing the space in which the reserved capacitor 14 may be disposed.

In addition, as shown in FIG. 1, when the reserve capacitor 14 is disposed in an area between two adjacent leaf cell groups 10 and 12 or another empty area, the distance between the reserve capacitor 14 and the leaf cell 10 is far from each other. In this case, a supply delay of a current required for the leaf cell may occur.

In this case, there is a problem that a temporary power supply failure occurs or the level of the power supplied to the leaf cell is lowered, thereby degrading the performance of the device provided in the leaf cell.

In addition, in order to reduce the size of the leaf cell as the size of the semiconductor device is gradually miniaturized, it is determined and used as a standardized unit cell frame so that the leaf cell can have an optimized layout.

For example, as shown in FIG. 2, a leaf cell is conventionally defined as a standardized unit cell including a P type well region 20 and an N type well region 22, and a MOS is formed in each well region 20 and 22. Elements such as transistors are formed.

However, when MOS transistors having different widths are disposed in the leaf cell as shown in FIG. 2, unnecessary free space may occur around the relatively small MOS transistors such as the region 24 indicated by the dotted line.

This extra space causes irregular gate critical dimensions and degrades the uniformity of the active, which can reduce the margin of subsequent processes such as chemical mechanical polish (CMP). have.

It is an object of the invention to place a reserve capacitor of sufficient capacity in a highly integrated semiconductor device.

It is another object of the present invention to reduce noise and level stabilization of power supplied to the device by reducing the arrangement interval between the device and the reserve capacitor provided in the leaf cell.

Another object of the present invention is to improve the gate threshold line width and the uniformity of active of the transistor provided in the leaf cell.

In the semiconductor device according to the embodiment of the present invention for achieving the above object, a leaf cell including an N-type well region and a P-type well region is defined, and the N-type well region and the P-type well region Elements respectively formed and receiving voltage through a first voltage line; And at least one reservoir capacitor formed in at least one of the N-type well region and the P-type well region, and configured to charge and supply the voltage supplied through the second voltage line to the devices. .

Preferably, the reserve capacitor is a MOS transistor type capacitor, and in particular, the reserve capacitor formed in the N type well region of the reserve capacitor is a PMOS transistor type capacitor, and the reserve capacitor formed in the P type well region is an NMOS transistor type capacitor. Is preferred. Here, the gate of the PMOS transistor type capacitor is supplied with a ground voltage through a ground voltage line, the gate of the NMOS transistor type capacitor is preferably supplied with a power supply voltage through a power supply voltage line. The reservoir capacitor may be a MOS transistor type capacitor having a unidirectional gate structure or a MOS transistor type capacitor having a bidirectional gate structure.

When the devices are MOS transistors having a dual gate oxide structure, the reserve capacitor is preferably a MOS transistor having a dual gate oxide structure. In addition, when the devices are MOS transistors having a single gate oxide structure, the reservoir capacitor is preferably a MOS transistor having a single gate oxide structure.

Preferably, the first and second voltage lines are electrically connected to a main voltage line formed to overlap on the leaf cell. Alternatively, the first voltage line is electrically connected to a first main voltage line formed to overlap on the leaf cell, and the second voltage line is electrically connected to a second main voltage line formed outside of the leaf cell. It is preferred to be connected.

Preferably, the elements formed in the N-type well region are PMOS transistors, and the elements formed in the P-type well region are NMOS transistors.

According to at least one example embodiment of the inventive concepts, a layout method of a semiconductor device includes: a first step of laying out an N-type well region and a P-type well region in a predetermined region; A second step of laying out elements in the N-type and P-type well regions; Laying out at least one or more reserve capacitors in at least one of the N-type and P-type well regions; And a fourth step of laying out lines for electrically connecting the reservoir capacitor and the elements on the N-type and P-type well regions.

Here, the reserve capacitor is preferably laid out in the remaining space after the elements are disposed in the N-type and P-type well region.

In addition, it is preferable that a MOS transistor type capacitor is laid out as the reserve capacitor. Here, it is preferable that a PMOS transistor type capacitor is laid out in the N-type well region, and an NMOS transistor type capacitor is laid out in the P-type well region.

In addition, the line is preferably a voltage line to which a voltage is supplied. In addition, PMOS transistors are laid out in the N-type well region, and NMOS transistors are laid out in the P-type well region.

In a fourth step, it is preferable that a voltage line for supplying a voltage to the reserve capacitor is further laid out, and the voltage line is laid out outside the predetermined area.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, by placing at least one or more reservoir capacitors in a space where elements are disposed and left in a standardized leaf cell, the performance of devices due to voltage stabilization, an increase in reserve capacitor capacity, and securing a subsequent process margin such as CMP are provided. You can get it.

Specifically, the semiconductor device of the present invention includes various leaf cell structures, and among the leaf cells having the layout structure of FIG. 3 as an example, will be described below.

In the following description, metal lines formed on the upper layer of the MOS transistor are defined as the first metal line, and metal lines formed on the upper layer of the first metal line are defined as the second metal line.

In addition, for convenience of description, the active region and the first metal line are electrically connected to each other through a contact MAC, and the gate and the first metal line are electrically connected to each other through a contact MCC. Note that the metal line and the second metal line are electrically connected to each other through a contact MMC.

First, the leaf cell of the semiconductor device of the present invention includes an N type well region 30 and a P type well region 31, and PMOS transistors PM having various widths are formed in the N type well region 30. In the P type well region 31, NMOS transistors NM having various widths are formed.

Here, one PMOS transistor PM and one NMOS transistor NM positioned on an extension line thereof may be connected in a CMOS structure. That is, the gate G of each of the PMOS and NMOS transistors PM and NM is commonly connected to the first metal line 32, and the drain region D of each of the PMOS and NMOS transistors PM and NM is connected to the contacts. It is commonly connected to the first metal line 35 through the MAC. In addition, the source region S of each PMOS transistor PM is electrically connected to the first metal line 33, and the source region S of each NMOS transistor NM is electrically connected to the first metal line 34. Is connected.

The first metal lines 33 are commonly connected to the second metal line 36, which is a power supply voltage line, and the first metal lines 34 are common to the second metal line 37, which is a ground voltage line. Is connected.

In addition, a center region in which the N-type well region 30 and the P-type well region 31 are in contact with each other, and a region that provides a bulk voltage to the PMOS transistors PM on both sides of the leaf cell based on the center region. 38 and a region 39 for providing a bulk voltage to the NMOS transistors NM are formed.

Here, regions 38 and 39 providing bulk voltages to the respective PMOS and NMOS transistors PM and NM are electrically connected to source regions S of the respective PMOS and NMOS transistors PM and NM through the first metal line. Can be connected.

In the P-type well region 30, at least one reserve capacitor (P) may be provided in the free space between the PMOS transistors PM having a smaller width and the region 38. RC) is formed.

Similarly, in the N-type well region 31, at least one reserve capacitor may be provided in the free space between the relatively narrow NMOS transistors NM and the region 39 among the NMOS transistors NM having various widths. RC) is formed.

In this case, when the type of the reserved capacitor RC is a MOS transistor type capacitor, the MOS transistor type capacitor is formed in the same direction or orthogonal direction to each of the PMOS and NMOS transistors PM and NM in accordance with the size of the free space in the leaf cell. Can be.

In addition, when the type of the reserve capacitor RC is a MOS transistor type capacitor, the MOS transistor type capacitor may have a bidirectional gate structure as shown in FIG. 4A or a unidirectional gate structure as shown in FIG. 4B depending on the arrangement and space area. have. 4A and 4B, 'A' represents an active region, 'G' represents a gate, 'D' represents a drain region, and 'C' represents a source region.

That is, not only a specific transistor is used as the reserve capacitor RC in the leaf cell of the semiconductor device of the present invention, but various types of the reserve capacitor RC may be used according to the free space inside the leaf cell.

In addition, the kind of reserve capacitor RC is determined by the kind of element provided in a leaf cell.

For example, as shown in FIG. 3, when the reservoir capacitor RC is formed in the P-type well region 30, a PMOS transistor type capacitor is formed as the reserve capacitor RC, and the reservoir is formed in the N-type well region 31. When the capacitor RC is formed, it is preferable that the NMOS transistor type capacitor is formed as the reserve capacitor RC.

In addition, when the devices included in the leaf cell are a thin MOS transistor having a dual gate oxide structure, the same thin MOS transistor is formed as the reserve capacitor RC, and the devices included in the leaf cell are single. In the case of a thick MOS transistor having a single gate oxide structure, the same thick MOS transistor is preferably formed as the reserve capacitor RC.

Meanwhile, the reserve capacitor RC may be disposed in all leaf cells to which a voltage that the reserve capacitor RC can use may be supplied. In this case, the gate power connection of the reservoir capacitor RC may be divided into a structure connected inside the leaf cell and a structure connected outside the leaf cell according to a method of supplying a voltage to the gate, and the drain and the drain capacitor of the reserve capacitor RC. The source power connections are all of the same structure.

First, the structure in which the power supply of the reservoir capacitor is connected inside the leaf cell may have a structure as shown in FIG. 5. Here, it is assumed that the reserve capacitor is a MOS transistor type capacitor.

Referring to FIG. 5, the gate of the PMOS transistor type capacitor 52 formed in the N-type well region 50 is the second metal line 59 which is a ground voltage line through the first metal line 54 formed in the leaf cell. Is electrically connected to the

In addition, the drain and the source of the PMOS transistor type capacitor 52 are electrically connected to the first metal line 56 corresponding to the source region S of the PMOS transistor formed in the N type well region 50. The first metal line 56 is electrically connected to the second metal line 58, which is a power supply voltage line.

The gate of the NMOS transistor type capacitor 53 formed in the P-type well region 51 is electrically connected to the second metal line 58 through the first metal line 55 formed in the leaf cell.

In addition, the drain and the source of the NMOS transistor type capacitor 53 are electrically connected to the first metal line 57 corresponding to the source region S of the NMOS transistor formed in the P-type well region 51. The first metal line 57 is electrically connected to the second metal line 59, which is a ground voltage line.

Here, the first metal lines 54 and 55 electrically connect the gates of the reservoir capacitors 52 and 53 and the voltage lines 58 and 59 in the leaf cell, such as the edge region of the leaf cell or the region between two adjacent MOS transistors. It can be formed in a free space that can be connected.

As described above, in the semiconductor device of the present invention, the gates of the respective reservoir capacitors 52 and 53 are electrically connected to the corresponding voltage lines 58 and 59 through the first metal lines 54 and 55 formed in the free space in the leaf cells. It may have a structure connected to receive a voltage.

Next, the structure in which the power supply connection of the reservoir capacitor is made outside the leaf cell may have a structure as shown in FIG. 6. Here, it is assumed that the reserve capacitor is a MOS transistor type capacitor.

Referring to FIG. 6, a plurality of leaf cells 60 are arranged in a line, and the gates of the reserve capacitors 61 formed in each leaf cell 60 extend out of each leaf cell 60 at the top of the gate. Is electrically connected to the first metal line 62. Each metal line 62 is electrically connected to a second metal line 64 formed outside the leaf cell 60. Here, the second metal line 64 is a power supply (or ground) voltage line.

That is, in the leaf cell of the semiconductor device of the present invention, the gate of the reservoir capacitor 61 is electrically connected to the power (or ground) voltage line 64 added to the outside through the first metal line 62 to supply a voltage. It can have a receiving structure.

As described above, the semiconductor device of the present invention has a structure in which a reserve capacitor is included in a free space in a leaf cell, thereby increasing the total capacity of the reserve capacitor disposed in the semiconductor device.

Also, since the reserve capacitor is disposed in the leaf cell, the distance between the elements constituting the leaf cell and the reserve capacitor can be reduced. Therefore, the elements constituting the leaf cell can be supplied with a sufficient amount of voltage from the reserve capacitor within an early time, there is an effect that can improve the device performance due to noise and level stabilization of the power supply.

In addition, as the unnecessary free space in the leaf cell is filled with the gate and the active region constituting the reserve capacitor, the gate threshold line width becomes regular and the uniformity of the active can be improved, so that the margin of a subsequent process such as CMP is sufficient. There is an effect that can be secured.

On the other hand, the method of inserting the reserve capacitor into the leaf cell as in the present invention can be largely divided into a manual (manual) insertion method and an insertion method using an automated program.

Manual is a method that a user calls an instance and inputs a width / space to a desired position. An automation program loads a reserve capacitor generator and drags it to a space where a user wants to insert a reserve capacitor. This creates a reserve capacitor for the space.

In this case, as shown in FIG. 7, it is preferable that both methods do not generate a contact and a metal line at the input (or output) terminal 70 at the position of the input (or output) terminal 70 when inserting a reserve capacitor into the leaf cell. Do.

As described above, the present invention has the effect of increasing the total capacity of the reserve capacitor disposed in the semiconductor device by disposing the reserve capacitor in the free space in the leaf cell.

In addition, the present invention can reduce the distance between the device and the reserve capacitor provided in the leaf cell by arranging the reserve capacitor in the leaf cell, there is an effect that the performance of the device can be improved by the noise and level stabilization of the power supply.

In addition, the present invention can improve the gate threshold line width and the uniformity of the active of the transistor provided in the leaf cell by disposing the reserve capacitor in unnecessary free space in the leaf cell, thereby ensuring sufficient margin for subsequent processes such as CMP. It can be effective.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (19)

A semiconductor device comprising a leaf cell including an N type well region and a P type well region, Elements formed in the N-type well region and the P-type well region, respectively, and receiving voltage through a first voltage line; And And at least one reserve capacitor formed in at least one of the N-type well region and the P-type well region, and configured to charge and supply the voltage supplied through the second voltage line to the devices. Device. The method of claim 1, And the reserve capacitor is a MOS transistor type capacitor. The method of claim 2, And a reserve capacitor formed in the N-type well region of the reserve capacitor is a PMOS transistor type capacitor, and a reserve capacitor formed in the P-type well region is an NMOS transistor type capacitor. The method of claim 3, wherein And the gate of the PMOS transistor type capacitor receives a ground voltage through a ground voltage line, and the gate of the NMOS transistor type capacitor receives a power supply voltage through a power supply voltage line. The method of claim 2, And the reserve capacitor is a MOS transistor type capacitor having a unidirectional gate structure. The method of claim 2, And the reserve capacitor is a MOS transistor type capacitor having a bidirectional gate structure. The method of claim 1, And when the devices are MOS transistors having a dual gate oxide structure, the reservoir capacitor is a MOS transistor having a dual gate oxide structure. The method of claim 1, And when the devices are MOS transistors having a single gate oxide structure, the reserve capacitor is a MOS transistor having a single gate oxide structure. The method of claim 1, And the first and second voltage lines are electrically connected to main voltage lines overlapping the leaf cells. The method of claim 1, The first voltage line is electrically connected to a first main voltage line overlapping the leaf cell, and the second voltage line is electrically connected to a second main voltage line formed outside the leaf cell. A semiconductor device characterized by the above-mentioned. The method of claim 1, Wherein the elements formed in the N-type well region are PMOS transistors, and the elements formed in the P-type well region are NMOS transistors. A first step of laying out an N-type well region and a P-type well region in a predetermined region; A second step of laying out elements in the N-type and P-type well regions; Laying out at least one or more reserve capacitors in at least one of the N-type and P-type well regions; And And a fourth step of laying out lines for electrically connecting the reservoir capacitor and the elements on the N-type and P-type well regions. 13. The method of claim 12, And the reserve capacitor is laid out in the remaining space after the elements are disposed in the N-type and P-type well regions. 13. The method of claim 12, And a MOS transistor type capacitor is laid out as said reserve capacitor. The method of claim 14, And a PMOS transistor capacitor in the N well region, and an NMOS transistor capacitor in the P well region. 13. The method of claim 12, And the line is a voltage line to which a voltage is supplied. 13. The method of claim 12, PMOS transistors are laid out in the N-type well region, and NMOS transistors are laid out in the P-type well region. 13. The method of claim 12, And in the fourth step, a voltage line for supplying a voltage to the reserve capacitor is further laid out. The method of claim 18, And a voltage line for supplying a voltage to the reserve capacitor is laid out outside the predetermined area.

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