KR20090043112A - Semi conductor device - Google Patents

Abstract

Disclosed is a semiconductor device that reduces stress applied to a semiconductor cell region. The semiconductor device includes a substrate including a chip area and a scribe lane, a semiconductor cell formed in the chip area, a dummy pattern formed in the scribe area, and an alignment key formed on the dummy pattern. The semiconductor chip may include a first contact region formed in the chip region, a second contact region spaced apart from the second contact region, a capacitor formed on the first contact region, a first plug and a capacitor electrically connecting the first contact region and the capacitor. And a second plug formed on and electrically connected to the first upper wiring and the second contact region. The stress applied to the semiconductor cell region can be reduced to reduce the defect of the semiconductor device.

Photo key, alignment key

Description

Semiconductor device {SEMI CONDUCTOR DEVICE}

The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device including a dummy pattern around a photo key.

Recent semiconductor devices require high speed operation while having a high storage capacity in terms of functionality. To this end, semiconductor devices are being manufactured with manufacturing techniques for improving integration, response speed, and reliability.

To this end, semiconductor devices include a plurality of patterns, and the plurality of patterns are stacked and electrically connected to each other. In this case, the plurality of stacked patterns should be aligned with each other. For this purpose, an alignment key pattern is required as an alignment mark.

The alignment key pattern is mainly formed in a scribe line located between the chip region where the circuit patterns are formed and the chip region. The alignment key pattern is not formed independently, but together when circuit patterns of the chip region are formed. Therefore, the thickness of the material forming the alignment key pattern and the alignment key pattern may vary according to the circuit pattern.

In addition, when another circuit pattern is further formed on or adjacent to the circuit pattern, the alignment pattern is affected by processes for forming the other circuit patterns.

For example, after the capacitor is formed in the ferroelectric memory (FRAM), an upper electrode electrically connected to the capacitor is formed. Next, in order to electrically connect the transistor element and the circuit wiring, a contact plug is formed to electrically connect the transistor element and the circuit wiring using a conductive material. The align key should be used to align each layer. When etching the region where the alignment key is to be formed, if a peel phenomenon occurs between the upper electrode and the interlayer insulating layer due to excessive etching, the yield of the wafer may be reduced due to such peel phenomenon. In addition, after repairing the defective cells generated by the peeling, the reliability of the ferroelectric memory product is deteriorated when the reliability test of the high / low temperature reliability test is performed.

An object of the present invention to solve the above problems is to provide a semiconductor device including a dummy pattern around the photo key.

In an embodiment, a semiconductor device may include a substrate including a chip area and a scribe lane, a semiconductor cell formed in the chip area, a dummy pattern formed in the scribe area, and the dummy pattern. And an alignment key formed. The semiconductor chip electrically connects a first contact region formed in the chip region, a second contact region spaced apart from the second contact region, a capacitor formed on the first contact region, the first contact region, and the capacitor. And a second plug formed on the capacitor, a first upper wiring connected to the capacitor, and a second plug electrically connected to the second contact region.

In one embodiment of the present invention, the dummy pattern may be formed on the same layer as the first upper wiring. The dummy pattern may be formed on the same layer as the capacitor. The dummy pattern may be formed on the same layer as the first plug.

In one embodiment of the present invention, the dummy pattern may include a first structure formed on the same layer as the first plug and a second structure formed on the same layer as the capacitor and formed on the first structure. The dummy pattern is formed on the same layer as the first upper wiring and a first structure formed on the same layer as the first plug, a second structure formed on the same layer as the capacitor and formed on the first structure, and the first upper wiring. It may include a third structure formed on the two structures.

In example embodiments, the semiconductor device may further include a second upper interconnection electrically connected to the first upper interconnection and formed on the first upper interconnection, and the dummy pattern may include the second upper interconnection. It may be formed on the same layer as the wiring.

According to another embodiment of the present invention, a semiconductor device includes a substrate including a chip area and a scribe lane, a semiconductor cell formed in the chip area, a dummy pattern formed in the scribe area, and formed next to the dummy pattern. Contains the align key. The semiconductor cell electrically connects a first contact region formed in the chip region, a second contact region spaced apart from the second contact region, a capacitor formed on the first contact region, the first contact region, and the capacitor. And a second plug formed on the capacitor, a first upper wiring connected to the capacitor, and a second plug electrically connected to the second contact region.

As described above, according to the preferred embodiment of the present invention, by forming a dummy pattern around the align key formed in the scribe region, the chip region is removed by eliminating excessive etching stress that may occur when the align region is formed in the scribe region. It can reduce the stress transmitted to.

Hereinafter, a semiconductor device according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited to the following embodiments, and has a general knowledge in the art. It will be apparent to those skilled in the art that the present invention may be embodied in various other forms without departing from the spirit of the invention. That is, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms and should be construed as being limited to the embodiments described herein. Is not. It is not to be limited by the embodiments described in the text, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but such components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may exist in the middle. Will be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it will be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring to", will be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "include" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features It will be understood that it does not exclude in advance the possibility of the presence or addition of numbers, steps, acts, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries are to be interpreted as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined in this application. .

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Hereinafter, a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention will be described in detail.

1 through 6 are cross-sectional views of a semiconductor device according to example embodiments.

1 to 6, the substrate 100 on which the semiconductor device is formed includes a chip region and a scribe region. The chip regions shown in FIGS. 1 to 6 will be described with the same reference numerals for the substantially identical or substantially similar components. The chip region is a region in which circuit patterns of the semiconductor device are formed, and a plurality of chip regions may be formed on the substrate 100. A scribe region is formed between the chip regions to distinguish the chip regions, respectively. An alignment key and a dummy pattern are formed on the scribe area.

In the chip region, transistors, conductive wirings, and capacitors of a general semiconductor element are formed. In the present invention, a ferroelectric memory element is exemplified, but may be substantially the same as or substantially similar to a chip region of a general DRAM or a PRAM.

In embodiments according to the invention, the first to third contact regions 110, 115, and 120, the gate structure (not shown), the first contact region 110, or the second contact region 115 in the chip region. ), A first plug 140 electrically connected to the first plug 140, a resistive adhesive layer pattern 155 formed on the first plug 140, a second plug 150 connected to the third contact region 120, and a resistive adhesive layer pattern ( The first upper wiring 220 and the first upper wiring 220 electrically connected to the ferroelectric capacitor 190 formed on the 155, the anti-deterioration layer 160 formed on the ferroelectric capacitor 190, and the ferroelectric capacitor 190. ) And a second upper wiring 240 electrically connected thereto.

An isolation layer (not shown) defining an active region and a field region is formed in the substrate 100. First to third contact regions 110, 115, and 120 are positioned in the active region.

The first to third contact regions 110, 115, and 120 are connected to transistors (not shown) including a gate structure (not shown). The gate structure is formed on the substrate 100 by adjoining the first to third contact regions 110, 115, and 120. The gate structure may include a gate insulating film, a gate electrode, a gate mask, and / or a gate spacer.

The resistive adhesive layer pattern 155 is formed on the first plug 140 and the first interlayer insulating layer 130. The resistive adhesive layer pattern 155 may increase the adhesion between the first interlayer insulating layer 130 and the lower electrode 170 of the ferroelectric capacitor 190 to prevent the lower electrode 170 from being separated. In addition, the resistive adhesive layer pattern 155 may serve as an ohmic layer between the first plug 140 and the lower electrode 170. The resistive adhesive layer pattern 155 may have a substantially wider width than the first plug 140 and the lower electrode 170.

The ferroelectric capacitor 190 is positioned on the resistive adhesive layer pattern 155. The ferroelectric capacitor 190 includes a lower electrode 170, a ferroelectric layer pattern 175, and an upper electrode 180. The ferroelectric capacitor 190 may be electrically connected to the first contact region or the second contact regions 110 and 115 through the first plug 140. The ferroelectric capacitor 190 may have a substantially pyramidal cross-sectional shape. That is, the lower electrode 170 may have a substantially wider width than the ferroelectric layer pattern 175, and the ferroelectric layer pattern 175 may have a substantially wider width than the upper electrode 180.

The anti-deterioration film 160 is formed on the first interlayer insulating film 130 while covering the ferroelectric capacitor 190, and the second interlayer insulating film 165 is formed on the anti-degradation film 160. The anti-deterioration film 160 prevents the ferroelectric capacitor 190 from being degraded by hydrogen diffusion during subsequent processes.

The first upper wiring 220 is connected to the upper electrode 180 of the ferroelectric capacitor 190 through the anti-deterioration film 160. The first upper wiring 220 may include a first adhesive layer 205, a wiring layer 210, and a second adhesive layer 215. The third interlayer insulating layer 230 is formed on the second interlayer insulating layer 165 and the ferroelectric capacitor 190 while covering the first upper wiring 220. The second upper wiring 240 penetrates through the third interlayer insulating layer 230 and is electrically connected to the first upper wiring 220. The third upper wiring 245 is formed on the second plug 150.

The dummy pattern 260 and the alignment key 250 are formed in the scribe area. The alignment key 250 is formed on the dummy pattern 260. The dummy pattern 260 is formed on the second interlayer insulating layer 165. The alignment key 250 may have a step. This is to more easily detect the alignment key 250 by the alignment equipment. The dummy pattern 260 may adjust excessive etching of the area where the alignment key 250 is disposed.

The dummy pattern 260 may be formed together when the first upper wiring 220 is formed. For example, after the second interlayer insulating layer 165 is formed, the deterioration preventing layer 160 and the upper electrode of the ferroelectric capacitor 190 formed on the upper electrode 180 of the ferroelectric capacitor 190 through a photolithography process. A contact hole (not shown) is formed in the second interlayer insulating film 165 formed on the 180. A preliminary first adhesive layer (not shown), a preliminary wiring layer (not shown), and a preliminary second adhesive layer (not shown) are formed on the second interlayer insulating film 165 while filling the contact holes. The preliminary first adhesive layer, the preliminary wiring layer, and the preliminary second adhesive layers are etched using a mask to form a first upper wiring 220 and a dummy pattern 260 on the second interlayer insulating layer 165. Although not shown, the dummy pattern 260 may be formed of a plurality of patterns instead of one pattern.

The alignment key 250 may be formed at the same time as the second plug 150. For example, the third interlayer insulating layer 230 is formed on the first upper wiring 220 and the dummy pattern 260. The second plug 150 to be electrically connected to the third contact region 120 by etching the first to third interlayer insulating layers 130, 165, and 230 disposed on the third contact region 120 and the dummy pattern 260. ) And an opening for exposing a portion of the dummy pattern 260 and a contact hole (not shown) to be formed. The etching depths of the contact hole and the opening may be different due to the dummy pattern 260. For example, the etching patterns of the dummy patterns 260 and the first to third interlayer insulating layers 130, 165, and 230 may have deeper etching depths of the contact holes.

In the absence of the dummy pattern 260, the first to third interlayer insulating layers 130, 165, and 230 formed in the scribe region are excessively etched, so that the etching stress caused by the etching may occur on the upper portion of the ferroelectric capacitor 190 in the chip region. Peeling of the electrode 180 and the upper wiring 220 may occur. The dummy pattern 260 suppresses excessive etching of the scribe region and suppresses etch stress generated during the etching while the first to third interlayer insulating layers 130, 165 and 230 of the chip region are etched. You can prevent it. The opening (not shown) may have a tapered shape that becomes narrower toward the bottom. The opening in which the alignment key 250 is to be formed may be formed at a constant depth without exposing the dummy pattern.

A contact hole and an opening are filled in and a conductive material, for example, polysilicon or metal doped with a high concentration of impurities is deposited on the third interlayer insulating film 230. For example, tungsten, aluminum, tantalum, ruthenium, iridium, platinum, tungsten silicide, tungsten nitride, or a combination thereof is used. In one embodiment according to the invention, tungsten (W) is deposited. The conductive material deposited in the scribe region may be formed to have a surface profile that matches the step difference of the opening along the opening exposing the dummy pattern. Therefore, the alignment key 250 formed on the opening may have a step.

The second plug 150 and the align key 250 are formed by performing a chemical mechanical polishing (CMP) process on the conductive material on the chip region until the surface of the third interlayer insulating film 230 is exposed. do. The second plug 150 penetrates through the first to third interlayer insulating layers 130, 165, and 230 to be electrically connected to the second contact region.

The third interlayer insulating layer 230 is etched to form an opening (not shown) that exposes the first upper wiring 220. A conductive material is formed on the third interlayer insulating film 230 and the alignment key 250 while filling the opening. The conductive material is etched to form a second upper wiring 240 and a third upper wiring 245.

In another embodiment according to the present invention, the second upper wiring 240 and the third upper wiring 245, the second plug 150, and the alignment key 250 may be simultaneously formed. For example, after forming the third interlayer insulating layer 230, the third interlayer insulating layer 230 is etched to contact the second upper wiring 240 with the first upper wiring 220. And an opening (not shown) in which the alignment key 250 is to be formed, and the first to third interlayer insulating layers 130, 165, and 230 are etched to form the second plug 150. A contact hole (not shown) is formed. Then, the conductive material may be embedded and patterned to simultaneously form the second upper wiring 240 and the third upper wiring 245, the second plug 150, and the alignment key 250.

Referring to FIG. 2, the dummy pattern 320 formed in the scribe region includes a first structure 305, a second structure 310, and a third structure 315. The dummy pattern 320 may be substantially the same as or similar to the structure and shape of the first plug 140, the ferroelectric capacitor 190, and the first upper wiring 220 formed in the chip region. In addition, a plurality of first to third structures 305, 310, and 315 illustrated in FIG. 2 may be formed as one. The dummy pattern 320 prevents excessive etching of the scribe region when the scribe region is etched. Excessive etching is prevented, reducing stress on the chip area.

The first structure 305 may be formed at the same time as the first plug 140. For example, the first interlayer insulating layer 130 is formed on the substrate 100. When the first interlayer insulating layer 130 is etched to form a contact hole (not shown) in which the first plug 140 is to be formed in the chip region, the first interlayer insulating layer 130 formed in the scribe region is etched to form a first interlayer insulating layer 130. 1 forms an opening (not shown) in which the structure 305 is to be formed. After filling the contact hole and the opening with a conductive material, a planarization process is performed on the chip region to form the first plug 140 and the first structure 305.

The second structure 310 may be formed at the same time as the ferroelectric capacitor 190. For example, after forming the first plug 140 and the first structure 305, a preliminary adhesion reinforcing layer (not shown), a preliminary bottom electrode (not shown), a preliminary ferroelectric layer (not shown), and A preliminary upper electrode (not shown) is formed in the chip region and the scribe region and then etched to simultaneously form the ferroelectric capacitor 190 and the second structure 310.

The third structure 315 may be formed at the same time as the first upper wiring 220. The method of forming the third structure is omitted because it is substantially the same as or similar to the method described with reference to FIG. 1.

The alignment key 330 is formed on the dummy pattern 320. The alignment key 330 may be formed together when the second plug 150 is formed. Since the method of forming the align key 330 is substantially the same as or similar to the method described with reference to FIG. 1, it is omitted.

The third interlayer insulating layer 230 is etched to form an opening (not shown) that exposes the first upper wiring 220. A conductive material is formed on the third interlayer insulating film 230 and the alignment key 330 while filling the opening. The conductive material is etched to form a second upper wiring 240 and a third upper wiring 245.

Referring to FIG. 3, the dummy pattern 350 formed in the scribe region includes a first structure 335, a second structure 340, and a third structure 345. The dummy pattern 350 may be substantially the same as or similar to the shape of the first plug 140, the ferroelectric capacitor 190, and the first upper wiring 220 formed in the chip region. The first and second structures 335 and 340 are disposed under a region corresponding to the third structures 345. The first structure may be formed simultaneously with the first plug 140. The second structure 310 may be formed at the same time as the ferroelectric capacitor 190. The third structure 315 may be formed at the same time as the first upper wiring 220. Since the method of forming the dummy pattern 350 is substantially the same as or similar to the method of forming the dummy patterns 250 and 320 described with reference to FIGS. 1 and 2, description thereof will be omitted.

The alignment key 355 is disposed on the dummy pattern 350. The alignment key 355 is formed on the dummy pattern 320. The alignment key 355 may be formed together when the second plug 150 is formed. The formation method of the alignment key 355 is omitted since it is substantially the same as or similar to the method described with reference to FIG. 1.

The third interlayer insulating layer 230 is etched to form an opening (not shown) that exposes the first upper wiring 220. A conductive material is formed on the third interlayer insulating film 230 and the alignment key 355 while filling the opening. The conductive material is etched to form a second upper wiring 240 and a third upper wiring 245.

2 and 3, it can be seen that the arrangement of the first to third structures may vary. That is, a plurality of first structures to third structures may be respectively formed, or may be formed of one structure each and may be disposed to cross each other.

Referring to FIG. 4, the dummy pattern 370 formed in the scribe region includes a first structure 360 and a second structure 365. The shape and structure of the first structure 360 and the second structure 365 are substantially the same as or similar to the first plug 140 and the ferroelectric capacitor 190, respectively. The first structure 360 and the second structure 365 may each be one structure.

The first structure 360 may be formed at the same time as the first plug 140. The second structure 365 may be formed at the same time as the ferroelectric capacitor 190. Since the method of forming the first structure 305 and the second structure 310 described with reference to FIG.

The alignment key 375 is formed on the second structure 365. The alignment key 375 is disposed on the dummy pattern 370. The alignment key 375 is formed on the dummy pattern 370. The alignment key 370 may be formed together when the second plug 150 is formed.

For example, a third interlayer insulating film 230 is formed on the first upper wiring 220 and the second interlayer insulating film 165. A contact hole (not shown) that exposes the third contact region 120 by etching the first to third interlayer insulating layers 130, 165, and 230 disposed on the third contact region 120 and the dummy pattern 370. ) And the second and third interlayer insulating layers 165 and 230 are etched to form openings (not shown) that expose a portion of the dummy pattern 370. The opening may have a tapered shape in which the width thereof is narrowed downward. The opening may be formed to have a constant depth without exposing the dummy pattern 370. A conductive material is formed on the third interlayer insulating film 230 to fill the contact hole and the opening. Since the conductive material is formed to have a predetermined thickness along the opening surface, the alignment key 375 may have a step. Thereafter, a planarization process is performed on the chip region to form the second plug 150 and the alignment key 375.

The third interlayer insulating layer 230 is etched to form an opening (not shown) that exposes the first upper wiring 220. A conductive material is formed on the third interlayer insulating film 230 while filling the opening. The conductive material is etched to form a second upper wiring 240 and a third upper wiring 245.

Referring to FIG. 5, the dummy pattern 380 formed in the scribe region is substantially the same as or substantially similar to the ferroelectric capacitor 190. The alignment key 385 is formed on the dummy pattern 380. Although not shown, a film that is the same as or similar to the deterioration preventing film 160 formed on the ferroelectric capacitor 190 may be formed between the dummy pattern 380 and the alignment key 385. Alignment key 385 has a step. The dummy pattern 380 may be one single structure.

The method of forming the dummy pattern 380 is omitted because it is substantially the same as or similar to the second structure 310 shown in FIG. 2.

The alignment key 385 is formed on the second structure 365. The alignment key 385 is disposed on the dummy pattern 380. The alignment key 385 is formed on the dummy pattern 380. The alignment key 385 may be formed together when the second plug 150 is formed. The formation method of the align key 385 is omitted since it is substantially the same as or similar to the align key 375 shown in FIG.

The third interlayer insulating layer 230 is etched to form an opening (not shown) that exposes the first upper wiring 220. A conductive material is formed on the third interlayer insulating film 230 while filling the opening. The conductive material is etched to form a second upper wiring 240 and a third upper wiring 245.

Referring to FIG. 6, the dummy pattern 390 formed in the scribe region is substantially the same as or substantially similar to the first plug 140. Since the method of forming the dummy pattern 390 is substantially the same as or similar to the method of forming the first structure 305 illustrated in FIG. 2, a description thereof will be omitted.

The alignment key 395 is formed on the dummy pattern 390. The alignment key 395 may be formed at the same time as the second plug 150. For example, an opening (not shown) for forming the third interlayer insulating layer 230 and then etching the first and second interlayer insulating layers 130 and 165 formed in the scribe region to expose the dummy pattern 390. The third contact region 120 is exposed by etching the first to third interlayer insulating layers 130, 165 and 230 formed in the chip region. The opening may have a tapered shape in which the width thereof is narrowed downward. The opening may be formed to have a constant depth without exposing the dummy pattern 390. A conductive material is formed on the third interlayer insulating film 230 to fill the exposed portions by the etching. The planarization process is performed on the chip region, and the second plug 150 and the alignment key 395 are formed.

7 through 11 are cross-sectional views of semiconductor devices in accordance with some example embodiments of the inventive concepts.

Referring to FIG. 7, a fourth interlayer insulating layer 247 is formed on the third interlayer insulating layer 230 formed in the chip region and the scribe region. The fourth interlayer insulating layer 247 covers the second upper wiring 240 and the third upper wiring 245. A third plug 248 electrically connected to the third upper wiring 245 through the fourth interlayer insulating layer 247 is formed in the chip region. The third plug 248 is electrically connected to the fourth upper wiring 249 formed on the fourth interlayer insulating layer 247. The dummy pattern 400 and the alignment key 405 are formed on the third interlayer insulating layer 230 formed in the scribe region. The dummy pattern 400 may be plural as shown, or may be formed of a single single pattern although not shown. The alignment key 405 is formed on the dummy pattern 400. The alignment key 405 has a step.

The dummy pattern 400 may be formed together when the second upper wiring 240 and the third upper wiring 245 are formed. For example, after forming the third interlayer insulating film 230, the third interlayer insulating film 230 is etched to form an opening (not shown) that exposes the first upper wiring 220. A conductive material is formed on the third interlayer insulating film 230 and the alignment key 405 while filling the opening. The conductive material is etched to form a second upper wiring 240, a third upper wiring 245, and a dummy pattern 400.

The alignment key 405 may be formed together with the third plug 248. For example, the fourth interlayer insulating layer 247 is formed on the third interlayer insulating layer 230 while covering the second upper wiring 240, the third upper wiring 245, and the dummy pattern 400. The fourth interlayer insulating layer 247 is etched to form contact holes (not shown) and opening portions (not shown) that expose the third upper wiring 245 and the dummy pattern 400, respectively. The opening may have a tapered shape that becomes narrower toward the bottom. A conductive material is formed on the fourth interlayer insulating film 247 by filling the contact hole and applying the opening to a predetermined thickness. The third plug 248 and the alignment key 405 are formed by performing a planarization process on the chip region to expose the fourth interlayer insulating layer 247. A conductive material is deposited and patterned on the fourth interlayer insulating layer 247 and the alignment key 405 to form a fourth upper interconnection 249.

Referring to FIG. 8, the structure of the chip region is substantially the same as or similar to that of the chip region illustrated in FIG. 7 except for the fourth upper wiring 249 illustrated in FIG. 7. The dummy pattern 410 and the alignment key 415 are formed in the scribe area. The dummy pattern 410 has a structure and shape substantially the same as or similar to that of the ferroelectric capacitor 190. The alignment key 415 is formed on the dummy pattern 410. Alignment key 415 has a step.

The dummy pattern 410 may be formed together when the ferroelectric capacitor 190 is formed. The method of forming the dummy pattern 410 is omitted because it is substantially the same as or similar to the second structure 310 shown in FIG. 2.

The alignment key 415 may be formed together when the third plug 248 is formed. For example, a fourth interlayer insulating layer 247 is formed on the third interlayer insulating layer 230 while covering the second upper wiring 240 and the third upper wiring 245. The dummy pattern 410 is formed by etching the fourth interlayer insulating layer 247 to etch the contact hole (not shown) exposing the third upper interconnection 245 and the second to fourth interlayer insulating layers 165, 230, and 247. Each opening forms an opening (not shown). The opening may have a tapered shape that becomes narrower toward the bottom. A conductive material is formed on the fourth interlayer insulating film 247 by filling the contact hole and applying the opening to a predetermined thickness. The third plug 248 and the alignment key 415 are formed by performing a planarization process on the chip region to expose the fourth interlayer insulating layer.

Referring to FIG. 9, the structure of the chip region is substantially the same as or similar to that of the chip region illustrated in FIG. 7 except for the fourth upper interconnection 249 illustrated in FIG. 7. The dummy pattern 435 and the alignment key 440 including the first to third structures 420, 425, and 430 are formed in the scribe area. Since the dummy pattern 435 has a structure and shape substantially the same as or similar to the dummy pattern 320 shown in FIG. The alignment key 440 is formed on the dummy pattern 435. Align key 440 has a step.

The alignment key 440 may be formed together when the third plug 248 is formed. Since the method of forming the align key 440 is substantially the same as or similar to the method of forming the align key 415 illustrated in FIG. 8, a description thereof will be omitted.

Referring to FIG. 10, the structure of the chip region is substantially the same as or similar to that of the chip region illustrated in FIG. 7 except for the fourth upper wiring 249 illustrated in FIG. 7. The dummy pattern 455 including the first to second structures 445 and 450 and the alignment key 460 are formed in the scribe area. Since the dummy pattern 445 has a structure and shape substantially the same as or similar to that of the dummy pattern 370 shown in FIG. The alignment key 460 is formed on the dummy pattern 450. Alignment key 460 has a step.

The alignment key 460 may be formed together when the third plug 248 is formed. For example, a fourth interlayer insulating film 247 is formed on the third interlayer insulating film 230 while covering the second upper wiring 240 and the third upper wiring 245. The dummy pattern is formed by etching the fourth interlayer insulating layer 247 to etch the contact hole (not shown) exposing the third upper interconnection 245 and the fourth to second interlayer insulating layers 247, 230, and 165. Opening portions (not shown) that expose 455 are each formed. The opening may have a tapered shape that becomes narrower toward the bottom. A conductive material is buried in the contact hole on the fourth interlayer insulating layer 247, and is formed to have a predetermined thickness on the opening. The third plug 248 and the alignment key 460 are formed by performing a planarization process on the chip region to expose the fourth interlayer insulating layer.

Referring to FIG. 11, the structure of the chip region is substantially the same as or similar to that of the chip region illustrated in FIG. 7 except for the fourth upper wiring 249 illustrated in FIG. 7. The dummy pattern 475 and the alignment key 480 are formed in the scribe area. The dummy pattern 475 is substantially the same as or similar in structure, shape, and formation method to the dummy pattern 390 shown in FIG. 6. The alignment key 480 is formed on the dummy pattern 475. The align key 480 has a step.

The alignment key 480 may be formed together when the third plug 248 is formed. For example, a fourth interlayer insulating film 247 is formed on the third interlayer insulating film 230 while covering the second upper wiring 240 and the third upper wiring 245. The dummy pattern is formed by etching the fourth interlayer insulating layer 247 to etch the contact hole (not shown) exposing the third upper interconnection 245 and the fourth to second interlayer insulating layers 247, 230, and 165. Openings (not shown) that expose 475 are each formed. The opening may have a tapered shape that becomes narrower toward the bottom. A conductive material is buried in the contact hole on the fourth interlayer insulating layer 247, and is formed to have a predetermined thickness on the opening. The third plug 248 and the alignment key 480 are formed by performing a planarization process on the chip region to expose the fourth interlayer insulating layer.

Referring to FIG. 12, the structure of the chip region is substantially the same as or similar to that of the chip region illustrated in FIG. 7 except for the fourth upper wiring 249 illustrated in FIG. 7. The dummy pattern 525 and the alignment key 530 are formed in the scribe area. The dummy pattern 525 includes first to fourth structures 505, 510, 515, and 520. The first to third structures 505, 510, and 515 are substantially the same as or similar in structure, shape, and formation method to the first to third structures 305, 310, and 315 illustrated in FIG. 2. The fourth structure 520 is formed on the third structure 515. Alignment key 530 is formed around dummy pattern 525. The dummy pattern 525 may have a shape and a structure of the dummy pattern illustrated in FIGS. 1 to 11. The align key 530 has a step.

The dummy pattern 525 removes the etching stress applied to the actual cell in advance so that the minimum stress is transmitted to the actual cell.

The alignment key 530 may be formed together when the second plug 150 is formed. For example, the first to third interlayer insulating layers 130, 165 and 230 may be etched to expose the third contact region 120 to fill a contact hole (not shown) for filling the second plug 150. When forming, the first to third interlayer insulating layers 130, 165 and 230 or the second to third interlayer insulating layers 165 and 230 or the third interlayer insulating layer 230 around the dummy pattern 525 are etched. To form an opening (not shown). The opening may have a tapered shape that becomes narrower toward the bottom. An alignment key 530 is formed by filling the contact hole and forming a conductive material on the third interlayer insulating layer 230 to have a uniform thickness on the opening. 12 illustrates an alignment key 530 having a step in contact with the substrate 100, the alignment key 530 may be a first interlayer insulating layer 130, a second interlayer insulating layer 165, or a third interlayer insulating layer. It may be formed with a step on the 230.

The fourth structure 520 may be formed at the same time when the second upper wiring 240 and the third upper wiring 245 are formed. For example, the third interlayer insulating layer 230 is etched to form contact holes (not shown) for exposing the first upper wiring and openings for exposing the third structure 515. A conductive material is formed on the third interlayer insulating film 230 to fill the contact hole and the opening. The conductive material formed on the third interlayer insulating layer 230 is patterned to form a second lower interconnection 240, a third upper interconnection 245, and a fourth structure 520.

While the foregoing has been described with reference to embodiments of the present invention, those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

An etching process is used to form alignment keys in the scribe area. In this case, defects may occur in the cells formed in the chip region due to the etching stress. Through the dummy pattern formed in the scribe region, the etching stress may be reduced and the etching stress applied to the cells formed in the chip region may be eliminated to reduce defects that may occur in the cells formed in the chip region.

1 through 6 are cross-sectional views of a semiconductor device according to example embodiments.

7 through 11 are cross-sectional views of semiconductor devices in accordance with some example embodiments of the inventive concepts.

12 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: substrate 110: first contact region

115: second contact region 120: second contact region

130: first interlayer insulating film 140: first plug

150: second plug 155: resistive adhesive layer

160: anti-deterioration film 165: second interlayer insulating film

170: lower electrode 175: ferroelectric layer pattern

180: upper electrode 190: ferroelectric capacitor

220: first upper wiring 230: third interlayer insulating film

240: second upper wiring 245: third upper wiring

250: alignment key 260: dummy pattern

Claims (8)

A substrate comprising a chip area and a scribe lane; A first plug formed in the chip region, a second contact region spaced apart from the second contact region, a capacitor formed on the first contact region, a first plug electrically connecting the first contact region and the capacitor A semiconductor cell formed on the capacitor and including a first upper interconnection electrically connected to the capacitor and a second plug electrically connected to the second contact region; A dummy pattern formed in the scribe region; And And an alignment key having a step formed on the dummy pattern. The semiconductor device of claim 1, wherein the dummy pattern comprises a first structure formed on the same layer as the first upper interconnection. The semiconductor device of claim 1, wherein the dummy pattern includes a second structure formed on the same layer as the capacitor. The semiconductor device of claim 1, wherein the dummy pattern comprises a third structure formed on the same layer as the first plug. The semiconductor device of claim 1, wherein the dummy pattern comprises a third structure formed on the same layer as the first plug and a second structure formed on the same layer as the capacitor and formed on the third structure. . The method of claim 1, wherein the dummy pattern is a third structure formed on the same layer as the first plug, a second structure formed on the same layer as the capacitor and formed on the first structure and the same layer as the first upper wiring. And a first structure formed on the second structure. The semiconductor device of claim 1, further comprising a second upper wiring electrically connected to the first upper wiring and formed on the first upper wiring, wherein the dummy pattern is formed on the same layer as the second upper wiring. 4. A semiconductor device comprising four structures. A substrate comprising a chip area and a scribe lane; A first plug formed in the chip region, a second contact region spaced apart from the second contact region, a capacitor formed on the first contact region, a first plug electrically connecting the first contact region and the capacitor A semiconductor cell formed on the capacitor and including a first upper interconnection electrically connected to the capacitor and a second plug electrically connected to the second contact region; A dummy pattern formed in the scribe region; And And an alignment key having a step formed next to the dummy pattern.

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