KR20090028593A - Semiconductor memory device having stack structure - Google Patents

Abstract

A semiconductor memory device of a stack structure is provided to reduce a loading of a column selection signal and to increase a data processing speed by arranging a column decoder array between two banks. A semiconductor memory device of a stack structure includes a first bank(BA-U), a second bank(BA-D), and a column decoder array(10). The second bank is separated from the first bank. The column decoder array is positioned between the first bank and the second bank. A cell of the first bank and a cell of the second bank are selected by the same column selection signal at the same time. The column decoder array provides the column selection signal to the first bank and the second bank at the same time. The column selection signal is used in order to select the cells of the first bank and the second bank by decoding a column address.

Description

Semiconductor Memory Device Having Stack Structure

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a stack structure.

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a stack structure.

In general, a semiconductor memory device is composed of a plurality of banks capable of independent data access. In addition, a row decoder, a column decoder, a read driver, a write driver, and the like are provided for each bank. The cells of the bank are accessed by the driving thereof, and data is transferred between the cells and the data input / output pads.

As an example of such a semiconductor memory device, as illustrated in FIG. 1, a 4-bank BA_HL, BA_HR, BA_LL, and BA_LR structure including a plurality of cell matrices (not shown) may be disclosed, and each bank BA_HL. A row decoder array (X-DEC Array), a column decoder array (Y-DEC Array), and a data input / output device array (DATA I / O Array) are disposed around the BA_HR, BA_LL, and BA_LR.

Here, the data input / output device array DATA I / O array includes a plurality of write drivers WDRV and a plurality of read drivers IOSA.

Referring to the read operation of the semiconductor memory device having such a structure, a word line is activated by a row decoder array (X-DEC Array) and a column selection signal provided by the column decoder array (Y-DEC Array), for example, a column selection. One cell is selected for the column select signal provided in the signal line YI_HL.

The data of the selected cell is transferred to the data input / output device array DATA I / O array via the local input / output line LIO_HL, and the data transferred to the data input / output device array DATA I / O array is read driver. After being amplified by IOSA, it is output to the outside via the global input / output line GIO.

In this read operation, the configuration of a plurality of cell matrices and column decoder arrays (Y-DEC Arrays) determines the number of data that can come out at one time.

In the case of FIG. 1, four data may be output at one bank as one word line and one column select signal line YI_HL in one bank (eg, BA_HL).

However, when operating with 8-bit prefetch, a total of 32 column decoders are required because 128 data are simultaneously output from one bank in the x16 structure. That is, the number of column decoders increases as the number of data processed at one time increases.

Accordingly, as shown in FIG. 2, the number of column decoders may be reduced by dividing one bank into two parts BA_U and BA_D in a stacking manner.

That is, the conventional semiconductor memory device has one column select signal line YI extending from the column decoder array Y-DEC Array and two word lines WL_U and WL_D extending from the row decoder (not shown). The data of the selected cell is divided into 4 bits and transmitted to local input / output lines LIO_U and LIO_D.

However, in the stack bank structure illustrated in FIG. 2, the column selection signal provided from the column decoder array (Y-DEC Array) takes longer to transfer to the corresponding cell of the bank BA_U than to the corresponding cell of the bank BA_D. As a result, there is a limit in loading column selection signals and reducing memory operation speed.

In addition, as the capacity of the semiconductor memory device increases, the capacity required for each bank increases, and as the capacity of the bank increases, the length of the local input / output line LIO_U connected to the upper bank BA_U may increase, thereby increasing loading. There is a problem.

In addition, when the length of the local input / output line LIO_U becomes longer, the size of the write driver WDRV_U and read driver IOSA_U for driving the same increases, resulting in increased current consumption and data input / output device array DATA in the semiconductor memory device. There is a problem that the area occupied by the I / O array may increase.

Accordingly, an object of the present invention is to reduce the time for the column select signal to be transferred to each bank by properly arranging the column decoder array in the stack bank structure.

Another object of the present invention is to reduce the length of a local I / O line by properly arranging a data input / output device array in a stack bank structure.

Yet another object of the present invention is to reduce the size of the write driver and the read driver by minimizing the length of the local input / output line.

In accordance with an aspect of the present invention, a semiconductor memory device includes: a first bank; A second bank spaced apart from the first bank; And a column decoder array interposed between the first bank and the second bank, wherein corresponding cells of each of the first and second banks are simultaneously selected by the same column select signal.

According to another aspect of the present invention, there is provided a semiconductor memory device including: a first bank and a second bank; A column decoder array disposed adjacent to one side of the first bank and one side of the second bank and interposed between the first and second banks; A first write / read driver disposed at the other side of the first bank to control whether data is transmitted to the first bank; A second write / read driver disposed on the other side of the second bank to control input / output of the second bank and data, and corresponding cells of each of the first and second banks are simultaneously connected by the same column selection signal. Is selected.

As described above, the present invention has an effect of disposing a column decoder array between two stacked banks to form a stack structure, thereby reducing loading of a column selection signal and increasing data processing speed.

In addition, the present invention has the effect of reducing the load of the local input and output lines by dividing the data input / output device array into two and arranged in the upper and lower portions of each bank of the stack structure.

In addition, the present invention has the effect of reducing the size of the write driver and the read driver by dividing the data input and output device array in each bank to minimize the length of the local input and output lines.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the semiconductor memory device of the present invention, one column decoder array 10 is disposed to overlap between two stacked banks BA_U and BA_D, and the data input / output device array so that the length of the local input / output lines LIO_U and LIO_D is minimized. The stacks 22 and 24 have a stack structure in which the banks 22 and 24 are overlapped at upper and lower portions of the banks BA_U and BA_D.

Specifically, in the semiconductor memory device of FIG. 3, two banks BA_U and BA_D, one column decoder array 10, two data input / output arrays 22 and 24, and two in the bank region are illustrated in FIG. 3. It includes two global input and output lines (GIO_U, GIO_D).

One column decoder array 10 is disposed between two banks BA_U and BA_D, and two global input / output lines GIO_U and GIO_D are disposed at the top and the bottom of the bank area, respectively.

At this time, the column decoder array 10 decodes the column address to generate a column select signal for simultaneously selecting the corresponding cells of the two banks BA_U and BA_D, and the column select signal corresponds to the corresponding banks BA_U and BA_D. It is preferable to be disposed between the two banks BA_U and BA_D so that the time delivered to the cell is the same.

The bank BA_U and the data input / output array 22 are stacked and overlapped between the column decoder array 10 and the global input / output line GIO_U, and the bank BA_U overlaps the upper portion of the column decoder array 10. The data input / output array 22 is disposed below the global input / output line GIO_U.

In addition, the bank BA_D and the data input / output array 24 are stacked and overlapped between the column decoder array 10 and the global input / output line GIO_D, and the bank BA_D overlaps the lower portion of the column decoder array 10. In this case, the data input / output array 24 is disposed above the global input / output line GIO_D.

Here, each of the data input / output arrays 22 and 24 includes a plurality of write drivers 22a and 24a and a plurality of read drivers 22b and 24b, respectively.

The local input / output lines LIO_U and LIO_D of each bank BA_U and BA_D may include a plurality of write drivers 22a and 24a and a plurality of read drivers 22a and 24a included in adjacent data input / output arrays 22 and 24. Are connected in common.

In addition, each global input / output line GIO_U, GIO_D is connected to a plurality of write drivers 22a and 24a and a plurality of read drivers 22a and 24a, respectively, and local input / output lines LIO_U and LIO_D of each bank GIO_U and GIO_D. ) Is connected vertically.

That is, the column decoder array 10 is interposed between the two banks BA_U and BA_D by being disposed adjacent to one side of the bank BA_U and one side of the bank BA_D. In addition, the write / read drivers 22a and 22b are disposed at the other side of the bank BA_U to control whether the bank BA_U and data are transferred. Similarly, the write / read drivers 24a and 24b are disposed on the other side of the bank BA_D to control input / output of the bank BA_D and data.

In addition, the column decoder array 10 provides the same column select signal to the column select signal line YI_U and the column select signal line YI_D, and the column select signal line YI_U extends to the bank BA_U and the column The select signal line YI_D extends in the bank BA_D.

According to the exemplary embodiment of the present invention having the arrangement, the corresponding cells of the two banks BA_U and BA_D are simultaneously selected as the column selection signals provided by the column decoder array 10.

The data of the cell selected in the bank BA_U is amplified and written or read through the write driver 22a and the read driver 22b of the data input / output device array 22.

In addition, data of the cell selected in the bank BA_D is amplified and written or read through the plurality of write drivers 24a and the plurality of read drivers 24b included in the data input / output device array 24.

For example, referring to FIG. 4, a row operation according to an exemplary embodiment of the present invention, a row decoder array (not shown) decodes a row address and drives two words to drive corresponding cells of two banks BA_U and BA_D, respectively. Activate the lines WL_U and WL_D.

The specific cell of the bank BA_D is driven by the activated word line WL_D, and data stored in the driven cell is transferred to one of the bit line pairs BL and BLB.

As a result, a minute potential difference occurs in the bit line pairs BL and BLB, and the bit line sense amplifier 34 operates by driving signals RTO and SB to sense and amplify the potential difference between the bit line pairs BL and BLB.

During this operation, the column decoder array 10 decodes the column address to generate a column select signal YI for simultaneously selecting the corresponding cells of the two banks BA_U and BA_D.

Accordingly, the NMOS transistors N1 and N2 are turned on by the column select signal YI, so that the bit line pairs BL and BLB and the segment input / output line pairs SIO and SIOB are connected to each other. The amplified signals of BL and BLB are transferred to the segment input / output line pairs SIO and SIOB.

The NMOS transistors N3 and N4 are turned on by the input / output line switching signal IOSW, so that the segment input / output line pairs SIO and SIOB and the local input / output line pairs LIO_D and LIOB_D are connected to each other. The signals of the pair SIO and SIOB are transferred to the local input / output line pairs LIO_D and LIOB_D.

Thereafter, the read driver 24b included in the data input / output device array 24 senses and amplifies a potential difference between signals transmitted to the local input / output line pairs LIO_D and LIOB_D and transfers the corresponding data to the global input / output line GIO_D. .

Similarly, a specific cell of the lower bank BA_U is driven by the activated word line WL_U, and data stored in the driven cell is transferred to the local input / output line pairs LIO_U and LIOB_U through the same process as that of the bank BA_D. do.

Thereafter, the read driver 22b included in the data input / output device array 22 senses and amplifies a potential difference between signals transmitted to the local input / output line pairs LIO_U and LIOB_U, and transfers the corresponding data to the global input / output line GIO_U. .

As described above, according to the exemplary embodiment of the present invention, n bits of data are output from the bank BA_U by the word line WL_U and the column select signal YI, and the bank BA_D is output by the word line WL_D and the column select signal YI. n bits of data are returned.

That is, 2n bits of data may be read or written at one time by two word lines WL_U and WL_D and one column select signal YI.

At this time, since the column decoder array 10 is disposed between the two banks BA_U and BA_D, the time for which the column selection signal YI is transferred to each of the banks BA_U and BA_D can be minimized.

Therefore, according to the embodiment of the present invention, since the time for selecting the corresponding cells of the two banks BA_U and BA_D is reduced by the column select signal YI, the loading of the column select signal YI can be reduced and the memory operation speed can be improved. It works.

In addition, according to an embodiment of the present invention, the upper data input / output device array 22 for driving data input / output of the bank BA_U is disposed adjacent to the upper portion of the bank BA_U, and the data input / output of the bank BA_D is driven. The data input / output device array 24 is disposed below the bank BA_D.

Accordingly, the embodiment of the present invention can reduce the length of each local input / output line LIO_U, LIO_D, thereby reducing the loading of each local input / output line LIO_U, LIO_D, thereby reducing the occurrence of data errors.

In addition, the embodiment of the present invention can minimize the length of each local I / O line LIO_U, LIO_D by properly arranging the data input / output device arrays 22 and 24, The sizes of the plurality of write drivers 22a and 24a and the plurality of read drivers 22b and 24b may be reduced.

Therefore, current consumption of each data input / output device array 22 and 24 is reduced, and the area occupied by each data input / output device array 22 and 24 in the semiconductor memory device can be reduced.

1 is a layout view showing a semiconductor memory device having a general 4-bank structure.

2 is a layout diagram illustrating an example of a semiconductor memory device having a conventional stack bank structure.

3 is a layout view illustrating an example of a semiconductor memory device having a stack structure according to an embodiment of the present invention.

FIG. 4 is a circuit diagram for describing a read operation of the bank BA_D of FIG. 3.

Claims (6)

A first bank; A second bank spaced apart from the first bank; And A column decoder array interposed between the first bank and the second bank, And a corresponding cell of each of the first and second banks is simultaneously selected by a same column select signal. The method of claim 1, And the column decoder array provides a column selection signal to the first and second banks simultaneously to decode a column address and to select a corresponding cell of the first and second banks. A first bank and a second bank; A column decoder array disposed adjacent to one side of the first bank and one side of the second bank and interposed between the first and second banks; A first write / read driver disposed at the other side of the first bank to control whether data is transmitted to the first bank; And A second write / read driver disposed at the other side of the second bank to control input / output of the second bank and data; And a corresponding cell of each of the first and second banks is simultaneously selected by a same column select signal. The method of claim 3, wherein A first local input / output line connected between the first bank and a first write / read driver to transmit corresponding data; And And a second local input / output line connected between the second bank and the second write / read driver to transmit corresponding data. The method of claim 4, wherein And the first local I / O line and the second local I / O line have the same length. The method of claim 3, wherein And the column decoder array simultaneously provides a column selection signal to the first and second banks to decode a column address and to select a corresponding cell of the first and second banks.

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