KR100571625B1 - Semiconductor memory device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device having a small chip area and capable of supporting high-speed operation. The present invention provides an upper and lower end having a plurality of unit memory cell array blocks and a plurality of control blocks for driving the same. Half bank; Disposed in the horizontal direction between the upper and lower half banks to activate an odd-numbered or even-numbered block of a unit memory cell array block including the same word line in the upper and lower half banks when a word line is activated; Main word line driving means for driving; Column decoding means arranged in a vertical direction to drive column lines in the upper and lower half banks; And a main sense amplifier block arranged in a vertical direction and having a plurality of sense amplifiers for sensing and amplifying input and output data of the upper and lower half banks.

Low power, pitch, loading, high speed operation, size

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}             

1 is a block diagram illustrating a core block of a semiconductor memory device according to the related art.

2 is a block diagram illustrating a core block of a semiconductor memory device according to another related art.

3 is a detailed circuit diagram of region A of FIG. 2.

4 is a block diagram illustrating a core block of a semiconductor memory device according to a first embodiment of the present invention.

5 is a diagram illustrating in detail a unit bank (region B) of an upper half bank of FIG. 4.

6 is a core block diagram of a semiconductor memory device according to a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

410 unit memory cell array block

422, 424, 462: sub word line driving unit

432, 434: Sense Amplifier Array Block

442, 444, 446, 448, 472, 474: intersection area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly to a semiconductor memory device having a small area and a high operating speed.

In accordance with the current trend of high direct and ultra high speed semiconductor memory devices, efforts are being actively made to achieve this through optimal placement.

1 is a block diagram illustrating a core block of a semiconductor memory device according to the related art.

Referring to FIG. 1, a core block of a semiconductor memory device according to the related art is vertically disposed and a main word line driving unit 10 for driving a word line WL, and horizontally disposed to decode a column address. A column decoding unit 20 for driving the column line YS, a main sense amplifier block 30 arranged to horizontally amplify selected memory cell data, a main word line driving unit 10 and a column A bank 40 disposed inside the decoding unit 20 is provided.

The bank 40 includes a plurality of unit memory cell array blocks 42 for storing data, and a word line WL of the unit memory cell array block 42 disposed perpendicularly to each of the unit memory cell array blocks 42. A sub-word line driving unit 44 for driving the sub-word line driving unit 44, and a sense amplifier array block for sensing and amplifying data of a unit memory cell connected to the selected word line horizontally disposed with each unit memory cell array block 42 (46).

In addition, an n-bit data input / output line (LIO) disposed in the sense amplifier array block 46 is provided in the cross region 48 of the sub word line driving unit 44 and the sense amplifier array block 46. A plurality of input / output switches 48a for connecting the n-bit main data input / output lines MIO disposed in the sub word line driving unit 44 to each other are disposed.

In addition, a plurality of word lines WL driven by the main word line driving unit 10 are disposed in the horizontal direction on the unit memory cell array block 42 and are driven by the column decoding unit 20. The column line YS is disposed on the unit memory cell array block 42 in the vertical direction.

Next, the read or write operation of the above-described semiconductor memory device will be briefly described.

First, one word line WL is activated by a row address applied with an active command, and the other word line WL is inactivated. All of the plurality of sense amplifier array blocks 46 (shown in gray in the drawing) located above and below the unit memory cell array block 42 having the selected word line WL are activated and applied to the bit lines. To detect and amplify.

 Subsequently, L column lines YS are activated by the column addresses applied together with the read command and the write command, and the remaining column lines YS are deactivated. Accordingly, the data input / output line LIO and the main input / output data line MIO are connected in the corresponding cross region 48 by the activated column line YS in the selected word line WL to input and receive data. Output is possible.

As described above, when the word line is activated, the sense amplifier array blocks located above and below the unit memory resell array block having the selected word line sense and amplify the data, and each of the sense amplifier array blocks has n bits. Since a data input / output line is provided, a total of 2n bits of data are output when the corresponding column line YS is driven.

Therefore, since the number of column lines YS activated by the application of one command is L, the total number of data that can be read by accessing the bank 40 once is L × 2n.

As such, since the number of data input or output at the same time in one access is L × 2n, the same number of sense amplifiers in the main sense amplifier block 30 is required to L × 2n in order to amplify them all at once.

On the other hand, the semiconductor memory device as described above arranges X x 1024 word lines in the vertical direction and Y x 1024 bit lines in the horizontal direction. Since the area of the unit memory cell 42a is configured to have an area of 6F ² , the pitch of the bit line is 2F (F: unit length) and the pitch of the word line is 3F, so that the unit memory cell 42a The vertical direction of the region is formed longer than the horizontal direction.

In this way, a semiconductor memory device in which the unit memory cells 42a are arranged to have an area of 6F ² (2F × 3F) is compared with a device in which the unit memory cells are arranged to have an area of 8F ² (4F × 2F). It can be seen that the area of the cell 42a is 1/2 times shorter in the horizontal direction and 3/2 times longer in the vertical direction.

Therefore, the loading value of the column line of the semiconductor memory device arranged such that the unit memory cell has an area of 6F ² is increased by 5.5 times compared to the device having an area of 8F ² .

Specifically, since the length of the horizontal direction in which the bit line is disposed is reduced by half compared to a device having an area of 8F ² , the pitch of the column line is also reduced by half, thereby increasing the loading value of the column line by two times. In addition, since the length in the vertical direction is increased 3/2 times compared to the device having an area of 8F ² , the loading value of the column line is increased 3/2 times. In addition, as the sensing amplifier increases, the loading value of the column line doubles. Therefore, the loading value of the total increased column line is 2 + 3/2 + 2, which is 5.5 times.

As described above, if the unit memory cell in the semiconductor memory device has an area of 6F ² , the chip area may be reduced, but the switching speed may be slowed down due to an increase in the loading value of the column line, thereby not supporting high-speed operation.

Accordingly, FIG. 2 is a block diagram of the semiconductor memory device for minimizing the increase in the column line loading value while the unit memory cell in the semiconductor memory device has an area of 6F ² .

As shown in FIG. 2, a core block of a semiconductor memory device according to the related art is horizontally disposed at a center of a bank to drive a word line WL in an upper or lower half bank 50 or 55. First and second column decoders 70 and 75 disposed in a vertical direction with the main word line driving unit 60 to drive column lines YS of the upper and lower half banks 50 and 55, respectively. And first and second main sense amplifier blocks 80 and 85 arranged in the vertical direction to amplify the memory cell data of the upper and lower half banks 50 and 55, respectively, and the main word line driving unit 60. ) And the upper half bank 50 positioned between the first column decoder 70 and the lower half bank 85 positioned between the main wordline driving unit 60 and the second column decoder 75. Equipped.

Since the upper and lower half banks 50 and 55 have the same circuit configuration, for example, the A region including one unit memory cell array block in the upper half bank 50 and a block for driving the same is shown in FIG. Let's take a closer look at 3.

FIG. 3 is a diagram illustrating an area A in the upper half bank of FIG. 2 in detail.

Referring to FIG. 3, the upper half bank 50 includes a plurality of unit memory cells (MCUs) accessed through word lines formed in a vertical direction and bit lines BL formed in a horizontal direction. Sub word line driving units 52a and 52b for driving the odd and even word lines located above and below the array block 51, the unit memory cell array block 51, and the unit memory. Sense amplifiers 53a-1, 53a-2, 53b-1, and 53b-2, which are positioned on the left and right sides of the cell array block 51 to sense and amplify odd-numbered and even-numbered bit lines BL, respectively. The input / output data line (LIO) and the main as intersecting portions of the sense amplifier array blocks 53a and 53b and the sub word line driving units 52a and 52b and the sense amplifier array blocks 53a and 53b. I / O to connect input / output data lines (MIO) It includes a plurality of intersection areas that includes a power switch (54a, 54b, 54c, 54d).

Also, the word line selection signals FXBi <0: 7> and the sense amplifiers 53a-1, 53a-2, 53b-1, and 53b-2 for controlling the driving of the sub wordline driving units 52a and 52b. Sensing amplifier drive signals (SANi, SAPi, SANj, SAPj) to control the operation of the array is arranged in the vertical direction, such as the word line, which is located in the periphery of the unit memory cell array block containing the word line activation This is because the sense amplifier block and the sub word line driving unit are activated.

For reference, the subword line driving units 52a and 52b and the sense amplifier array blocks 53a and 53b are shared by adjacent unit memory cell array blocks.

In addition, the NMOS transistor shown in the figure in the intersecting regions 54a, 54b, 54c, 54d is a switch for controlling the driving of the sense amplifier.

2 and 3, the read or write operation of the above-described semiconductor memory device will be briefly described.

First, when a low address is applied together with an active command, the main word line driving unit 60 activates corresponding word lines in the upper or lower half banks 50 and 55 in response thereto. At this time, the division of the upper and lower half banks 50 and 55 is determined according to the logic value of the most significant bit of the low address.

Then, the memory cell data of the selected word line is detected and detected by all the sense amplifier array blocks located on the left and right sides of the unit memory cell array block including the selected word line, as indicated in gray in the drawing (see FIG. 2). Is amplified.

Subsequently, L columns of the corresponding column lines YS are activated by the column addresses applied together with the read command and the write command, so that the data input / output line LIO and the main input / output data line MIO) is connected to enable data input and output.

Meanwhile, as shown in FIG. 2, the semiconductor memory device according to the related art has 2 x Y x 1024 total bit lines in the vertical direction, and X / 2 x 1024 total word lines in the horizontal direction.

As described above, since the length of the column line in the semiconductor memory device according to another conventional technology is 1/2 times shorter than that of the semiconductor memory device of FIG. 1, the loading value of the column line is also 1 compared to the loading value of the semiconductor memory device of FIG. 1. It is reduced by 2 times.

Therefore, the load value which is within the column lines of a semiconductor memory device 2 is increased compared with the element having an area of 8F ² 5.5 / ² times, that is, 2.75 times.

Therefore, the semiconductor memory device according to another conventional technology divides a bank into two half banks, arranges a main word line driving unit among them, and arranges column decoding units in units of half banks, respectively. In comparison, the loading value is reduced by 1/2 times to enable high speed operation.

However, as described above, another semiconductor memory device according to the related art includes a column decoding unit and a main sense amplifier block for each half bank unit to support driving of a half bank unit. Accordingly, the area of the column decoding unit and the main sense amplifier block is increased twice as much as that of the semiconductor memory device of FIG. 1, resulting in an increase in the total area of the chip.

The present invention has been proposed to solve the above problems of the prior art, and has an object to provide a semiconductor memory device having a small chip area and capable of supporting high-speed operation.

In the semiconductor memory device having a plurality of banks consisting of a plurality of unit banks according to another aspect of the present invention, the unit bank, a unit memory cell array block having a plurality of unit memory cells accessed through a word line and a bit line ; First and second sub word line driving means for driving odd-numbered and even-numbered word lines in the unit memory cell array block and not shared, respectively; Sense amplifiers located on the left and right sides of the unit memory cell array block and shared by adjacent unit memory cell array blocks and detecting and amplifying odd and even bit lines of the unit memory cell array block, respectively. First and second sensing amplifier array blocks having a plurality; And an input / output data line LIO and a main input / output data line MIO as an intersection portion of the first and second sub word line driving means and the first and second sense amplifier array blocks. And first to fourth cross regions including a plurality of input / output switches.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

(First embodiment)

4 is a block diagram illustrating a core block of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 4, a core block of a semiconductor memory device according to an embodiment may include upper and lower half banks 400 and 500 having a plurality of unit memory cell array blocks and a plurality of control blocks for driving the same. And a unit memory cell array block disposed in a horizontal direction between the upper and lower half banks 400 and 500 and including the same word lines in the upper and lower half banks 400 and 500 when the word line WL is activated. The main word line driving unit 100 for activating the odd-numbered or even-numbered blocks among the 410s is vertically disposed to drive the column lines YS in the upper and lower half banks 400 and 500. A main decoder amplifier block 300 arranged in a vertical direction and having a plurality of sense amplifiers for sensing and amplifying input and output data of upper and lower half banks 400 and 500. phrase The.

For reference, the area of the unit memory cell in the half bank is configured to have an area of 6F ² , the pitch of the bit line is 2F (F: unit length), and the pitch of the word line is 3F.

On the other hand, since the upper and lower half banks 400 and 500 have the same circuit configuration, for example, one unit memory cell array block in the upper half bank 400 and a unit bank including a block for driving thereof (B area) ) With reference to FIG. 5.

FIG. 5 is a diagram illustrating in detail a unit bank (region B) of an upper half bank of FIG. 4.

Referring to FIG. 5, the unit bank B region includes a unit memory cell array block 410 including a plurality of unit memory cells MCU accessed through word lines formed in a vertical direction and bit lines BL formed in a horizontal direction. ), Sub word line driving units 424 and 422 for driving word lines that are located above and below the unit memory cell array block 410 and are not shared, and are located in odd-numbered and even-numbered positions, respectively, and in unit memory cells. Sense amplifier array blocks positioned on the left and right sides of the array block 410 and including a plurality of sense amplifiers 432a, 432b, 434a, and 434b for sensing and amplifying odd-numbered and even-numbered bit lines BL, respectively. The input / output data line LIO and the main input / output data line MIO are intersecting portions of the 432 and 434 and the sub word line driving units 422 and 424 and the sense amplifier array blocks 432 and 434. I / O to connect It includes an intersection region (442, 444, 446, 448) that includes a plurality of locations.

On the other hand, it can be seen that the sub word line driving units 422 and 462 for driving word lines in the unit memory cell array block are adjacent to each other. This is because the unit memory cell array block does not share the sub word line driving unit as in the prior art. This is because two sub word line driving units are independently provided for each unit memory cell array block.

Further, the word line selection signal FXB ₀ <0: 7> is a signal for controlling the driving of both sub word line driving units of the odd-numbered unit memory cell array block, and the word line selection signal FXB ₁ <0: 7> is A signal for controlling the driving of both sub word line driving units of the even-numbered unit memory cell array block. The sense amplifier drive signals SAP 0 and SAN0 represent both sense amplifier blocks of the odd-numbered unit memory cell array block, and the sense amplifier drive signals SAP 1 and SAN1 represent both sense amplifier blocks of the even-numbered unit memory cell array block. This signal is for driving.

As such, the word line selection signals FXB ₀ <0: 7 and FXB ₁ <0: 7> and the sense amplifier array blocks 432 and 434 for controlling the driving of the sub word line driving units 422, 424 and 462. Sensing amplifier drive signals (SAN ₀ , SAP ₀ , SAN ₁ , SAP ₁ ) are divided according to the odd-numbered or even-numbered position to control the driving of the Is placed.

This is because only the odd-numbered blocks or the even-numbered blocks of the unit memory cell array blocks including the selected word line are activated when the word lines are activated. The wordline driving and sense amplifier blocks are also intended to be active, depending on whether they are odd or even.

4 and 5, the read or write operation of the semiconductor memory device described above will be briefly described.

First, when a low address is applied together with an active command, the main word line driving unit 100 activates corresponding word lines in the upper and lower half banks 400 and 500 in response thereto.

Next, the memory cell data of the selected word line is positioned evenly among the sense amplifier array blocks positioned at the left and right sides of the unit memory cell array block including the selected word line as shown in black in FIG. 4 (see FIG. 4). It is detected and amplified by the block. At this time, the even or odd division of adjacent blocks for driving the same word line is determined according to the logic value of the most significant bit of the low address.

Subsequently, L column lines YS are activated in the upper and lower half banks 400 and 500 by the column addresses applied together with the read command and the write command, and 2n bits of main per one column line YS are activated. The input / output data line MIO is activated and connected to the main sense amplifier block 300. For example, the data input / output line LIO and the main input / output data line MIO are connected in the corresponding cross regions 442, 444, 446, and 448 to enable data input and output.

If the semiconductor memory device according to the embodiment of the present invention is a DDR 2 SDRAM, since the number of data simultaneously input or output in one access is 64 bits, 32 bits of data are input / output for each half bank.

A sense amplifier block for sensing and amplifying these memory cell data also includes 64 sense amplifiers.

Therefore, the semiconductor memory device according to the present invention having the area of the 6F ² unit memory cell has half the column decoding unit and the main sense amplifier block, compared to the semiconductor memory device according to the prior art, and thus has a small chip area.

(Second embodiment)

FIG. 6 is a core block diagram of a semiconductor memory device according to a second embodiment of the present invention, and has the same circuit configuration and operation as that of a conventional semiconductor memory device except for the area of the main sense amplifier block.

Referring to FIG. 6, the main sense amplifier block 600 in the core block of the semiconductor memory device according to the second embodiment of the present invention is connected to the main sense amplifier blocks 80 and 85 in the conventional semiconductor memory device (see FIG. 2). Compared with half the sense amplifier.

This is because only a word line in one half bank is active during core access, and data is input / output, so that the upper and lower half banks share the main sense amplifier block.

Accordingly, in the semiconductor memory device according to the second embodiment of the present invention, the semiconductor memory device according to the related art (see FIG. 2) reduces the area increase due to the main sense amplifier block.

However, if the semiconductor memory device according to the second embodiment of the present invention is a DDR 2 SDRAM, the half bank inputs / outputs 64-bit data in one access. Thus, instead of having only 64 sense amplifiers, the main sense amplifier block shared by the upper and lower half banks has a total of 128 data lines for receiving respective data from the upper and lower half banks.

Therefore, the semiconductor memory device according to the second embodiment of the present invention having the area of the unit memory cell of 6F ² has a smaller chip area than half of the conventional sense amplifier blocks by sharing the main sense amplifier blocks. As a result, a plurality of data lines for sharing with upper and lower half banks are required, thereby limiting chip area reduction.

Meanwhile, in the first embodiment of the present invention, since the semiconductor memory device includes a sub word line driving unit that is not shared in unit memory cell array block units, all the same word lines in the half bank are activated during core access, Activate only the unit memory cell array blocks or activate only the odd numbered unit memory cell array blocks.

Therefore, since the number of bits of data output per half bank is always constant in one access, the main sense amplifier block includes only as many sense amplifiers as the number of bits of data output.

Therefore, the semiconductor memory device according to the present invention described above can drive high-speed operation by minimizing column line loading while driving a bank into half banks while having a unit memory cell area of 6F ² . In addition, the number of bits of data output per half bank in a single access is kept constant, thereby eliminating unnecessary column decoding units and sense amplifiers, thereby minimizing area.

As described above, the present invention relates to an array structure capable of minimizing chip area through placement, and is applicable to SDR, DDR, and DDR2 SDRAM.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The above-described present invention supports high-speed operation by reducing column line loading by dividing banks into half-bank units, and makes constant the number of bits of data output from these half-banks during access, thereby reducing the number of unnecessary sense amplifiers. Reduce the area.

Claims (14)

In a semiconductor memory device having a plurality of banks divided into half bank units, An upper and lower half bank having a plurality of unit memory cell array blocks and a plurality of control blocks for driving the same; Disposed in the horizontal direction between the upper and lower half banks to activate an odd-numbered or even-numbered block of a unit memory cell array block including the same word line in the upper and lower half banks when a word line is activated; Main word line driving means for driving; Column decoding means arranged in a vertical direction to drive column lines in the upper and lower half banks; And A main sense amplifier block disposed in a vertical direction and having a plurality of sense amplifiers for sensing and amplifying input and output data of the upper and lower half banks; A semiconductor memory device having a. The method of claim 1, And the number of data output from the upper and lower half banks in the bank access is the same. The method of claim 2, And the main sense amplifier block includes the sense amplifiers as many as the number of bits of the input / output data. The method of claim 3, And the most significant bit of the low address is used to activate the unit memory cell array region positioned in the odd or even numbers. The method of claim 4, wherein The unit memory cell array area is A plurality of unit memory cells are accessed through the word line and the bit line, And the area of the unit memory cell has an area of 6F ² . In a semiconductor memory device having a plurality of banks consisting of a plurality of unit banks, The unit bank, A unit memory cell array block having a plurality of unit memory cells accessed through word lines and bit lines; First and second sub word line driving means for driving odd-numbered and even-numbered word lines in the unit memory cell array block and not shared, respectively; Sense amplifiers located on the left and right sides of the unit memory cell array block and shared by adjacent unit memory cell array blocks and detecting and amplifying odd and even bit lines of the unit memory cell array block, respectively. First and second sensing amplifier array blocks having a plurality; And A plurality of input / output switches for connecting an input / output data line and a main input / output data line as intersecting portions of the first and second sub word line driving means and the first and second sense amplifier array blocks. The first to fourth cross regions Semiconductor memory device comprising a. The method of claim 6, A semiconductor memory device, characterized in that only odd and even unit banks of a plurality of unit banks including a selected word line are activated. The method of claim 7, wherein And sub word line driving means disposed adjacent to each other. The method of claim 8, A word line selection signal activated through a low address to control driving of the sub word line driving means; Arrangement of the sense amplifier driving signal for controlling the driving of the sense amplifier array block in a direction perpendicular to the word line. A semiconductor memory device characterized in that. The method of claim 9, And the area of the unit memory cell has an area of 6F ² . In a semiconductor memory device having a plurality of banks divided into half bank units, Upper and lower half banks having a plurality of unit memory cells accessed through word lines and bit lines; Main word line driving means disposed in a horizontal direction between the upper and lower half banks to drive word lines in the upper and lower half banks; First and second column decoding means arranged in a vertical direction to drive column lines of the upper and lower half banks, respectively; And Having a main sense amplifier block arranged vertically and shared by the upper and lower half banks to amplify memory cell data A semiconductor memory device characterized in that. The method of claim 11, The main sense amplifier block, And a sensing amplifier equal to the number of bits of data output in one access. The method of claim 12, And a word line is activated in any one of the upper and lower half banks when one bank is accessed. The method of claim 13, And the area of the unit memory cell has an area of 6F ² .

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