KR20090027561A - Multi-layered memory apparatus - Google Patents

Abstract

A multi-layered memory apparatus is provided to improve a data storage density by forming one or more memory layer by a plurality of sub arrays. A multi-layered memory apparatus includes two or more memory parts(12) and an active circuit part(11). The active circuit part includes a decoder, and is formed between the memory parts. The memory part includes one or more memory layer. The memory layer is a memory array of a cross point type, and has a plurality of sub arrays. The active circuit part is formed on a non-silicone substrate. The non-silicone substrate is made of plastic, glass, ceramic, oxide material, or nitride material.

Description

Multi-Layered Memory Apparatus

The present invention relates to a stacked memory device, and more particularly, to a stacked memory device having a multilayer structure including at least one memory layer on at least one surface of an active circuit unit.

With the development of the industry and the development of multimedia, the demand for a large-capacity information storage device used for a computer, a communication equipment, etc. is gradually increasing. Due to this demand, information devices with high information storage density and operation speed have been researched and developed.

The memory device generally includes an active circuit portion and a memory portion. The active circuitry includes an address decoder, read / write control logic, sense amplifiers, output buffers, multiplexers and many for data reading and writing. These are commonly referred to as overhead and occupy a portion of the physical memory area. If the overhead area is kept small, more space can be used for the memory area.

In order to improve the density of memory devices, studies have been made to form multiple layers. Techniques for 3D memory, in which active circuits that support the operation of memory devices, such as data read and write, are formed on a silicon substrate and stacked with a plurality of memory cell arrays thereon have been described in US Pat. No. 6,185,122 and the like.

An object of the present invention is to provide a highly integrated stacked memory device capable of improving data storage density.

In order to achieve the above object, in the present invention,

In a stacked memory device,

Two or more memory units; And

Provided is a stacked memory device formed between the memory units and including an active circuit unit including a decoder.

In addition, in the present invention, a multilayer memory device, comprising a memory unit and an active circuit unit for controlling the memory unit, wherein the memory unit and the active circuit unit are provided as one memory unit, and the memory unit is provided in plural. To provide.

In the present invention, the memory unit may include one or more memory layers.

In the present invention, the memory layer may be a cross point type memory array.

In the present invention, the memory layer may be formed with a plurality of subarrays.

In the present invention, the cross point type memory array may have a structure in which adjacent memory array layers share electrodes.

In the present invention, the active circuit unit may be formed on a non-silicon substrate.

In the present invention, the non-silicon substrate may be a plastic, glass, ceramic, oxide or nitride substrate.

In the present invention, the memory unit may be continuously deposited using the active circuit unit and the memory unit as one memory unit.

In the present invention, the active circuit unit may include at least one of a column decoder and a row decoder.

The column address line branched from the column decoder may be connected to the memory unit through a via, and the row address line branched from the row decoder may be connected to the memory layer through a via.

The active circuit unit may include a first active circuit unit including a column decoder and a second active circuit unit including a row decoder, and the memory unit is connected to the first active circuit unit and the second active circuit unit, respectively. Can be.

In the present invention, a column address line branched from the column decoder of the first active circuit unit is connected to the memory unit through a via, and a row address line branched from the row decoder of the second active circuit unit is connected to the memory through a via. It may be connected to the layer.

In the present invention, it may further include a logic unit formed on one surface of the active circuit unit or the memory unit.

A memory device comprising: a memory area formed on a substrate, the memory area including the plurality of memory layers and the active circuit part;

An I / O chip connected by the memory area and a parallel bus line; And

And a serial bus line connecting the I / O chip and the master.

Hereinafter, a multilayer memory device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. For reference, it should be noted that the thickness and width of each layer shown in the drawings are somewhat exaggerated for explanation.

The stacked memory device according to an embodiment of the present invention may include a plurality of memory units including at least one memory layer, and an active circuit unit including an active circuit unit between each memory unit. The memory unit is formed in a structure in which one or more memory layers are stacked. The active circuit unit may control the memory unit, and the memory unit and the active circuit unit may be configured as one memory unit, and the memory unit may be continuously formed. By forming the active circuit portion on the non-silicon substrate, the memory portion and the active circuit portion can be formed continuously by the vapor deposition process rather than the bonding process. In the stacked memory device according to the exemplary embodiment of the present invention, the active circuit unit may be formed at a desired position without limitation on the lower, middle, or upper portions of the memory units.

1A is a diagram illustrating a stacked memory device according to a first embodiment of the present invention. 1A illustrates a memory unit including a plurality of memory layers formed on one surface of an active circuit unit.

Referring to FIG. 1A, the memory device according to the first embodiment of the present invention includes an active circuit 11 and a memory 12 formed on one surface of the active circuit 11. The memory unit 12 includes one or more memory layers a1, a2, a3... An, and the number of memory layers a1, a2, a3. The active circuit unit 11 includes a row decoder and a column decoder. Each of the memory layers a1, a2, a3..., An constituting the memory unit 12 is formed in an array structure including a plurality of memory cells.

Referring to FIG. 1B, each of the memory layers a1, a2, a3..., An may have a cross point type memory array structure, and the plurality of first electrode lines 101 and the second formed in the first direction may be used. An information storage unit 103 and a switch structure 104 such as a diode may be formed between the plurality of second electrode lines 102 formed in the direction. The information storage unit 103 may be a memory structure of various forms, for example, a ferroelectric capacitor, a magnetoresistive element, a phase change element, a resistance conversion element, and an anti-fuse memory element having a reversible and irreversible structure. have. In addition, each of the adjacent memory layers may be formed in a structure in which electrodes are shared with each other and stacked.

Each of the memory layers a1, a2, a3..., An may include one memory array 120 as shown in FIG. 1C, and as shown in FIG. 1D, a plurality of subarrays ( 121) may be formed.

2A and 2B are diagrams illustrating a modification of the stacked memory device according to the first embodiment of the present invention. 2A and 2B illustrate a structure in which the active circuit unit and the memory unit are stacked in succession as one memory unit.

Referring to FIG. 2A, a first active circuit unit 21 is formed on a logic unit 20, which is one of active circuits, and a first memory unit 22 is formed on a first active circuit unit 21. . The first memory unit 22 has a structure in which a plurality of memory layers are stacked. On the first memory section 22, a second active circuit section 23 and a second memory section 24 are formed. That is, in FIG. 2A, the memory units 22, 24, and 26 including one or more memory layers are formed on one active circuit unit 21, 23, and 25. The logic unit 20 basically includes a logic circuit, and may select each of the active circuit units 21, 23, and 25. Each active circuit unit 21, 23, 25 basically includes a decoder, and each of the memory units 22, 24, 26 may be selected.

That is, in the present invention, a plurality of active circuit units 21, 23, and 25 capable of selecting one or more memory units, recording and reproducing information, and forming a plurality of active circuit units 21, 23 and 25, and a logic unit for controlling the active circuit units 21, 23 and 25 ( 20). In the prior art, a structure in which a plurality of memory layers are formed on an active circuit part is proposed, but by designing a single active circuit part, an excessively large number of via holes is required and a complicated line process is required. However, in the stacked memory device according to the embodiment of the present invention, the number of memory parts that can be stacked is substantially limited by forming a plurality of memory layers and active circuit parts controlling the same as a single unit. none.

Referring to FIG. 2B, a first memory unit 201 is formed on the logic unit 200, and a first active circuit unit 202 is formed on the first memory unit 201. The second memory portion 203 and the second active circuit portion 204 are formed on the first active circuit portion 202. That is, in FIG. 2B, active circuit units 202, 204, and 206 are formed on the memory units 201, 203, and 205, and the memory unit and the active circuit unit are continuously formed on the logic unit 200 as one unit. The structure laminated | stacked is shown. The logic unit 200 basically includes a logic circuit and may select each of the active circuit units 202, 204, and 206. Each active circuit unit 202, 204, and 206 basically includes a decoder, and each of the memory units 201, 203, and 205 can be selected.

2C and 2D are diagrams for describing a driving principle of a stacked memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2C, a plurality of memory units M and a plurality of active circuit units D are formed on a logic unit 210 in a stacked memory device according to an embodiment of the present invention. The logic unit 210 may be connected to the plurality of active circuit units D through the decoder selection line 221 and may select a specific active circuit unit. In addition, an address (row, column) of a desired memory cell is input through a memory address selection line connected to the logic unit 210 and the active circuit unit D. FIG. In this case, a signal may be input through the row line 222a and the column line 222b. Only the specific memory layer of the memory unit M may be selected through the memory level decoder. This will be described in more detail with reference to FIG. 2D.

Referring to FIG. 2D, first, a plurality of memory units 211 and 213 and active circuit units 212 and 214 are formed on the logic unit 210. The first active circuit unit 212 records and reproduces data in the first memory unit 211, and the second active circuit unit 214 records and reproduces data in the second memory unit 213. If one active circuit unit and a memory unit are denoted by D as one unit, a combination of the active circuit unit and the memory units may be formed on the second active circuit unit 214 without limitation.

The logic unit 210 is connected to the active circuit units 212 and 214 through the decoder select lines 221, respectively. The logic unit 210 may select a specific active circuit unit among the active circuit units 212 and 214 through the decoder select lines 221. For example, when the first active circuit unit 212 is selected, the selection line s1 is set on, and the remaining lines are set off. Then, through the memory address selection line 222 connected in common with the logic unit 210 and all active circuit units 212, 214..., An address (row, column) of a desired memory cell is input. At this time, since only the first active circuit unit 212 is in an on state, only addresses of specific memory cells of each memory layer of the first memory unit 211 are input. Then, only the specific memory layer of the first memory unit 211 is selected through the memory level decoder. As a result, the desired memory cell can be selected.

3 is a diagram illustrating a stacked memory device according to a second embodiment of the present invention. 3 illustrates a memory unit including one or more memory layers formed on both surfaces of one active circuit unit.

Referring to FIG. 3, the memory device according to the second embodiment of the present invention includes an active circuit unit 31 and memory units 32 and 33 formed at both sides of the active circuit unit 31. The first memory unit 32 includes one or more memory layers b1, b2, b3... Bn, and the second memory unit 33 also includes one or more memory layers b1, b2, b3. It includes. The number of memory layers included in each memory unit 32 and 33 is not limited. The active circuit 31 is formed on a non-silicon substrate and basically includes a decoder for selecting memory layers of the memory units 32 and 33, and optionally includes a sense amplifier, a buffer, a step-down circuit, a boost circuit, and a detection circuit. It may further include a circuit or a reference contact circuit.

4 is a view showing a modification of the second embodiment of the present invention. 4 illustrates a structure in which the active circuit unit and the memory units formed on both surfaces of the active circuit unit are sequentially stacked with one memory unit.

Referring to FIG. 4, the first memory unit 41 is formed on the logic unit 40, and the first active circuit unit 42 and the second memory unit 43 are formed on the first memory unit 41. It is. Above the second memory section 43, a third memory section 44, a second active circuit section 45, and a fourth memory section 46 are formed. The logic unit 40 basically includes a logic circuit and may select each of the active circuit units 42 and 45. Each of the active circuits 42 and 45 basically includes a decoder, and each of the active circuits 42 and 45 may select memory units 41, 43, 44, and 46 formed on both surfaces thereof.

5 is a diagram illustrating a stacked memory device according to a third embodiment of the present invention. In FIG. 5, a column decoder and a row decoder of an active circuit unit capable of selecting each memory layer are formed on separate layers, and thus the memory unit may be selected.

Referring to FIG. 5, a first active circuit portion 51a is formed, a first memory portion 53 is formed on the first active circuit portion 51a, and a second active circuit portion is formed on the first memory portion 53. 52a, a second memory section 54, and a third active circuit section 51b are formed. The first active circuit unit 51a and the third active circuit unit 51b include one of a column decoder and a row decoder. If the first active circuit portion 51a and the third active circuit portion 51b include a column decoder, the second active circuit portion 52a includes a row decoder.

The first memory unit 53 includes one or more memory layers d1, d2... Dn, and the second memory unit 54 also includes one or more memory layers e1, e2. And the number is unlimited. Each active circuit portion 51a, 52a, 51b is connected to the upper and lower memory portions 53, 54 so that one or more memory layers d1, d2 ..., dn, e1, e2 of the memory portions 53, 54 are connected. ..., en). For example, when the first active circuit portion 51a includes the column decoder and the second active circuit portion 52a includes the row decoder, the first active circuit portion 51a and the second active circuit portion 52a The memory layers d1, d2,... Dn of the first memory unit 53 therebetween can be selected.

6 is a diagram illustrating a modification of the stacked memory device according to the third embodiment of the present invention.

Referring to FIG. 6, a first active circuit unit 61 and a first memory unit 64 are formed on a logic unit 60, and a second active circuit unit 62 and a second active circuit unit 62 are formed on the first memory unit 64. Two memory sections 65 are formed. The third active circuit portion 63 and the third memory portion 66 are formed above the second memory portion 65. The logic unit 60 basically includes a logic circuit and may select each of the active circuit units 61, 62, and 63. Each active circuit portion 61, 62, 63 basically includes one of a column decoder or a row decoder, and each active circuit portion 61, 62, 63 has its own memory portion 64, 65, 66 formed on both sides thereof. You can choose. In this manner, the active circuit unit including one of the column decoder and the row decoder and the memory unit may be continuously formed on the logic unit to form a continuous stacked structure.

As described above, the memory layers of the stacked memory device according to the exemplary embodiment of the present invention may be formed in the form of a cross point type memory array. Specifically, the memory layer includes a plurality of lower electrode lines and a plurality of upper electrode lines that intersect the lower electrode lines, and a switch structure and charge storage in an area where the lower electrode lines and the upper electrode lines intersect. The structure may be a structure formed sequentially. The upper electrode line and the lower electrode line may be connected to the row decoder or the column decoder of the active circuit layer, respectively.

There is only a memory array in the memory layer, and unlike the prior art, it does not include a separate memory array enable circuit. In the stacked memory device according to the embodiment of the present invention, the logic unit may be formed on a silicon substrate or a non-silicon substrate. For example, after forming a logic circuit constituting a logic unit on a silicon or non-silicon substrate, an interlayer dielectrics (ILD) process is performed, and a memory unit and an active circuit unit are repeatedly formed on the logic unit. Non-silicon substrates include, for example, plastic, glass, ceramic, oxide or nitride substrates. The active circuit unit basically includes a decoder, and may further include a sense amplifier, a buffer, a step-down circuit, a boost circuit, a detection circuit, or a reference contact circuit. In the prior art, by forming the active circuit portion on the silicon substrate, the area is limited, and the memory cell area that can be processed therefrom is also limited, which limits the number of memory layers that can be stacked. However, according to the present invention, this limitation can be overcome by being able to form an active circuit section between the memory sections.

7A and 7B are diagrams illustrating an arrangement structure of a decoder circuit that is a part of an active circuit unit in a structure in which a memory unit is formed on one surface of an active circuit unit according to an embodiment of the present invention. The decoder circuit includes a row decorder (RD) and a column decorder (CD).

Referring to FIG. 7A, the active circuit unit 71 includes both the row decoder RD and the column decoder CD. Row address lines (r) and column address lines (c) branched from the row decoder RD and the column decoder CD, respectively, are formed in the upper portion of the active circuit unit 71 through the vias. It can be seen that formed to be connected to the memory unit 72. When the memory unit 72 on the active circuit unit 71 is formed of one or more memory layers, the memory unit 72 may be connected in the same form as each of the memory layers.

Referring to FIG. 7B, the active circuit unit 701 includes both the row decoder LD and the column decoder CD, and the row address lines r branched from the row decoder RD and the column decoder CD, respectively, and It can be seen that the column address line c is formed to be connected to the memory unit 702 under the active circuit unit 701 through the via v. When the memory unit 702 is formed of one or more memory layers, the memory unit 702 may be connected in the same form as each of the memory layers.

In the structure in which a row decoder and a column decoder are formed in the active circuit unit, and memory units including a plurality of memory layers are formed on the upper and lower surfaces of the active circuit unit, the row address line and the column decoder are connected to each memory layer in the active circuit unit. It is also possible to form a.

8A and 8B illustrate a stacked memory device in accordance with an embodiment of the present invention, wherein one of the row or column decoder circuits is formed on the lower layer based on the memory unit, and the other of the row or column decoder circuits is formed on the memory layer. To show and record information in the memory layer.

Referring to FIG. 8A, the memory unit 82 and the second active circuit unit 83 are sequentially formed on the first active circuit unit 81. In this case, a column decoder CD may be formed in the first active circuit unit 81, and a row decoder RD may be formed in the second active circuit unit 83. Column line address lines c branched from the column decoder CD at both sides of the first active circuit unit 81 are alternately connected to the memory unit 82 through vias v alternately left and right. The row address lines r branched from the row decoder RD are alternately connected to the memory unit 82 through vias V at the front and rear ends of the second active circuit unit 83. When the memory unit 82 is formed of multiple memory layers, the memory unit 82 may be connected in the same form as each of the memory layers.

In FIG. 8B, the column address line c branched from the column decoder CD is connected to the memory unit 802 through the via v only on one side of the first active circuit unit 801. The row address line r branched from the row decoder RD at the front end of the second active circuit unit 803 is connected to the memory unit 802 through a via v. When the memory unit 802 is formed of one or more memory layers, the memory unit 802 may be connected in the same form as each of the memory layers.

9A and 9B illustrate a structure in which vias v are alternately formed in order to increase the density of address lines branched from a column decoder and a row decoder in a stacked memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 9A, a row decoder RD and a column decoder CD are formed at one end of each of the active circuit units 91, and a memory unit 92 is formed on one surface of the active circuit unit 91. The memory unit 92 and the via v are alternately formed with the row address line r and the column address line c branched from the row decoder RD and the column decoder CD of the active circuit unit 91, respectively. It is connected.

Referring to FIG. 9B, the active circuit unit 901 includes both a row decoder LD and a column decoder CD, and column decoders CD are formed at both sides of the active circuit unit 901, and at the front and rear ends thereof. The row decoder RD is formed. The memory unit 902 is formed on one surface of the active circuit unit 901. The memory unit 72 and the via address line r and the column address line c branched from the row decoder RD and the column decoder CD of the active circuit unit 901 are alternately formed. You can see that it is connected.

The formation position and the form of the via v are selectively determined according to the configuration and the degree of integration of the array elements of the memory units 92 and 902, but are not limited thereto. The structures of the active circuit portion and the memory portion shown in FIGS. 7A, 7B, 8A, 8B, 9A, and 9B can be set in one unit and repeatedly stacked. Therefore, the connection line can be simplified and the number of vias can be greatly reduced as compared with the memory device using one active circuit unit.

10 is a diagram illustrating an implementation of a stacked memory device according to an embodiment of the present invention. Referring to FIG. 10, a multilayer memory device 100 according to an embodiment of the present invention may include a memory region 102, an I / O chip 104, and a memory region 102 having a multilayer structure formed on a substrate 101. The parallel bus line 103 connects the I / O chip 104 and the serial bus line 105 connects the I / O chip 104 and the master.

Through the above embodiments, those skilled in the art will be able to manufacture a variety of electronic devices by the technical idea of the present invention. The stacked memory device according to the embodiment of the present invention can be used as media of various products. The scope of the invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

1A is a diagram illustrating a stacked memory device according to a first embodiment of the present invention.

1B to 1D are diagrams illustrating a memory layer.

2A and 2B are diagrams illustrating a modification of the stacked memory device according to the first embodiment of the present invention.

2C and 2D are diagrams for describing a driving principle of a stacked memory device according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a stacked memory device according to a second embodiment of the present invention.

4 is a view showing a modification of the second embodiment of the present invention.

5 is a diagram illustrating a stacked memory device according to a third embodiment of the present invention.

6 is a diagram illustrating a modification of the stacked memory device according to the third embodiment of the present invention.

7A and 7B are diagrams illustrating an arrangement structure of a decoder circuit that is a part of an active circuit unit in a structure in which a memory unit is formed on one surface of an active circuit unit according to an embodiment of the present invention.

8A and 8B illustrate a stacked memory device in accordance with an embodiment of the present invention, wherein one of the row or column decoder circuits is formed on the lower layer based on the memory unit, and the other of the row or column decoder circuits is formed on the memory layer. To show and record information in the memory layer.

9A and 9B illustrate a structure in which vias v are alternately formed in order to increase the density of address lines branched from a column decoder and a row decoder in a stacked memory device according to an exemplary embodiment of the present invention.

10 is a diagram illustrating an implementation of a stacked memory device according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

11, 21, 23, 25, 202, 204, 206, 31, 42, 45, 51a, 51b, 52a, 61, 62, 63, 71, 701, 81, 83, 801, 803, 91, 901 ... Active circuit,

12, 22, 24, 26, 201, 203, 205, 32, 33, 41, 43, 44, 46, 53, 54, 64, 65, 66, 72, 702, 82, 802, 92, 902 ... Memory

20, 200, 40, 60 ... logic section

CD ... column decoder RD ... row decoder

c ... column address line r ... row address line

v ... via

Claims (25)

In a stacked memory device, Two or more memory units; And A stacked memory device formed between the memory units and including an active circuit unit including a decoder. The method of claim 1, The memory unit includes at least one memory layer. The method of claim 2, And the memory layer is a cross point type memory array. The method of claim 3, wherein The memory layer has a plurality of sub-array formed. The method of claim 3, wherein The cross-point type memory array has a structure in which adjacent memory array layers share electrodes with each other. The method of claim 1, The active circuit unit is a stacked memory device formed on a non-silicon substrate. The method of claim 1, The non-silicon substrate is a plastic, glass, ceramic, oxide or nitride substrate. The method of claim 1, And a memory unit on which the active circuit unit and the memory unit are configured as one memory unit. The method of claim 1, And the active circuit unit comprises at least one of a column decoder and a row decoder. The method of claim 9, And a column address line branched from the column decoder is connected to the memory unit through a via, and a row address line branched from the row decoder is connected to the memory layer through a via. The method of claim 1, The active circuit unit includes a first active circuit unit including a column decoder and a second active circuit unit including a row decoder, wherein the memory unit is connected to the first active circuit unit and the second active circuit unit, respectively. The method of claim 11, A stacked memory in which a column address line branched from the column decoder of the first active circuit unit is connected to the memory unit through a via, and a row address line branched in the row decoder of the second active circuit unit is connected to the memory layer through a via Device. The method of claim 1, And a logic unit formed on one surface of the active circuit unit or the memory unit. The method of claim 1, A memory region formed on a substrate, the memory region including the plurality of memory layers and the active circuit unit; An I / O chip connected by the memory area and a parallel bus line; And And a serial bus line connecting the I / O chip and the master. In a stacked memory device, And a memory unit and an active circuit unit for controlling the memory unit, wherein the memory unit and the active circuit unit are provided as one memory unit, and the memory unit is provided in plural. The method of claim 15, The memory unit includes at least one memory layer. The method of claim 16, And the memory layer is a cross point type memory array. The method of claim 17, The memory layer has a plurality of sub-array formed. The method of claim 17, The cross-point type memory array has a structure in which adjacent memory array layers share electrodes with each other. The method of claim 15, The active circuit unit is a stacked memory device formed on a non-silicon substrate. The method of claim 15, And the active circuit unit comprises at least one of a column decoder and a row decoder. The method of claim 21, And a column address line branched from the column decoder is connected to the memory unit through a via, and a row address line branched from the row decoder is connected to the memory layer through a via. The method of claim 15, The active circuit unit includes a first active circuit unit including a column decoder and a second active circuit unit including a row decoder, wherein the memory unit is connected to the first active circuit unit and the second active circuit unit, respectively. The method of claim 23, wherein A stacked memory in which a column address line branched from the column decoder of the first active circuit unit is connected to the memory unit through a via, and a row address line branched in the row decoder of the second active circuit unit is connected to the memory layer through a via Device. The method of claim 15, And a logic unit formed on one surface of the active circuit unit or the memory unit.

Images