CN101388236B - Multi-layered memory devices - Google Patents
Multi-layered memory devices Download PDFInfo
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- CN101388236B CN101388236B CN200810213119.1A CN200810213119A CN101388236B CN 101388236 B CN101388236 B CN 101388236B CN 200810213119 A CN200810213119 A CN 200810213119A CN 101388236 B CN101388236 B CN 101388236B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
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Abstract
A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array.
Description
Technical field
The present invention relates to a kind of multi-layered memory devices.
Background technology
Along with the development of multimedia technology, the demand of the more jumbo information-storing device for computing machine, communicator etc. is increased.In order to meet the demand of this increase, developed the massaging device with relatively high information storage density and relative high operating speed.
Conventionally, memory storage includes source circuit unit and storage unit.Active circuit unit comprises address decoder, reads/record logic controller, sensing amplifier, output buffer, multiplexer and other assembly to be to read and record data.These assemblies are commonly called " top arrangement (overhead) ", and occupy a part for physical storage areas.If the region that top arrangement occupies is relatively little, larger region can be used as storage area.In order to increase the density of memory storage, carry out the research that is intended to form multi-layered memory devices.
Summary of the invention
Example embodiment relates to multi-layered memory devices, for example, has the multi-layered memory devices of the sandwich construction that comprises at least one the lip-deep one or more accumulation layer that is arranged in active circuit unit.
Example embodiment provides a kind of more highly integrated multi-layered memory devices that can increase the density of data storage.
At least one example embodiment provides a kind of multi-layered memory devices.At least, according to this example embodiment, described multi-layered memory devices can comprise: two or more storage unit and active circuit unit.Active circuit element can comprise demoder, and can be formed between each in described two or more storage unit.
At least one other example embodiment provides a kind of multi-layered memory devices.Described multi-layered memory devices can comprise stacking each other multiple storage sets.Storage sets can comprise storage unit and be constructed to the active circuit unit of control store unit.
According to example embodiment, storage unit can comprise one or more accumulation layers.Described one or more accumulation layer is for intersecting point type storage array.The point type storage array that intersects can have such structure, that is, and and adjacent storage array layer shared electrode.Multiple subarrays can be formed in described one or more accumulation layer.Active circuit unit can be formed in non-silicon base.Non-silicon base can be plastic-substrates, substrate of glass, ceramic bases, oxide base and the one at the nitride based end.Each active circuit unit and corresponding storage unit composition storage sets.Multiple storage sets can be stacking each other.Each active circuit unit can comprise at least one in column decoder (CD) and row decoder (RD).
At least, according to some example embodiment, the column address conductor extending from CD can be connected to storage unit by path, and the row address line extending from RD can be connected to described one or more accumulation layer by path.
At least, according to some example embodiment, active circuit unit can comprise the first active circuit unit and the second active circuit unit, and the first active circuit unit can comprise CD, and the second active circuit unit can comprise RD.Storage unit can be connected to each in the first active circuit unit and the second active circuit unit.The column address conductor extending from the CD of the first active circuit unit can be connected to storage unit by path, and the row address line extending from the RD of the second active circuit unit can be connected to described one or more accumulation layer by path.
At least, according to some example embodiment, logical block can be formed on the surface of in active circuit unit and storage unit.Described multi-layered memory devices can also comprise: storage area, is formed in substrate.Storage area comprises storage unit and active circuit unit.I/O (I/O) chip can be connected to storage area and parallel bus.Universal serial bus can connect I/O chip and main device.
At least one other example embodiment provides a kind of multi-layered memory devices.Described multi-layered memory devices can comprise at least one active circuit unit and at least one storage unit.Described at least one memory circuit can comprise demoder.Each at least one storage unit can be connected to demoder.Described at least one storage unit can be separated with described at least one active circuit unit.Described at least one active circuit can be arranged in above or below described at least one storage unit.
At least, according to some example embodiment, described at least one storage unit can comprise stacking each other multiple accumulation layers.Each in described multiple accumulation layer can be connected to demoder.
At least, according to some example embodiment, demoder can comprise column decoder and row decoder.Column decoder can comprise the first row decoder circuit at the first sidepiece place that is arranged in described at least one active circuit unit and be arranged in the secondary series decoder circuit at the second sidepiece place of described at least one active circuit unit.Row decoder can comprise the first row decoder circuit at the 3rd sidepiece place that is arranged in described at least one active circuit unit and be arranged in second row decoder circuit at the 4th sidepiece place of described at least one active circuit unit.The first sidepiece and the second sidepiece can be toward each other, and the 3rd sidepiece and the 4th sidepiece can be toward each other.
At least according to some example embodiment, demoder can through from described at least one active circuit unit up or down vertically extending address wire be connected to each described at least one storage unit.Demoder can comprise column decoder and row decoder.Column decoder can by from described at least one active circuit unit up or down vertically extending column address conductor be connected to each described at least one storage unit.Column address conductor can be connected to described at least one storage unit by being arranged in the path at least one sidepiece place of active circuit unit.Described path can be setovered mutually along the vertical direction of the direction of extending with described at least one sidepiece.
At least according to some example embodiment, row decoder can by from described at least one active circuit unit up or down vertically extending row address line be connected to each described at least one storage unit.Row address line can be connected to described at least one storage unit by being arranged in the path at least one sidepiece place of active circuit unit.Described path is setovered mutually along the vertical direction of the direction of extending with described at least one side.
At least, according to some example embodiment, described at least one storage unit can comprise at least one accumulation layer.Described at least one accumulation layer can comprise at least one storage array.
Accompanying drawing explanation
By the detailed description to example embodiment of the present invention with reference to accompanying drawing, it is more obvious that the present invention will become, in accompanying drawing:
Figure 1A is the diagram illustrating according to the multi-layered memory devices of example embodiment;
Figure 1B to Fig. 1 D is the diagram illustrating according to the accumulation layer of example embodiment;
Fig. 2 A and Fig. 2 B are the diagrams illustrating according to the multi-layered memory devices of example embodiment;
Fig. 2 C and Fig. 2 D are for describing according to the diagram of the example drive principle of the multi-layered memory devices of example embodiment;
Fig. 3 is the diagram illustrating according to the multi-layered memory devices of another example embodiment;
Fig. 4 is the diagram illustrating according to the multi-layered memory devices of another example embodiment;
Fig. 5 is the diagram illustrating according to the multi-layered memory devices of another example embodiment;
Fig. 6 is the diagram illustrating according to the multi-layered memory devices of another example embodiment;
Fig. 7 A and Fig. 7 B are the diagrams illustrating according to the array structure of the decoder circuit of parts as active circuit unit of the multi-layered memory devices of example embodiment, wherein, the structure of multi-layered memory devices is that storage unit is formed on the surface of active circuit unit;
Fig. 8 A and Fig. 8 B are the diagrams illustrating according to the structure of the multi-layered memory devices of example embodiment, wherein, one in row decoder (RD) circuit and column decoder (CD) circuit is formed on storage unit below, another in RD circuit and CD circuit is formed on storage unit top, thereby the information of storage unit is recorded in multi-layered memory devices, and from the information of multi-layered memory devices reading cells;
Fig. 9 A and Fig. 9 B are the diagrams illustrating according to the structure of the multi-layered memory devices of example embodiment, wherein, alternately form path (via) V to increase in multi-layered memory devices from the density of the address wire of CD and RD branch;
Figure 10 is the diagram illustrating according to the multi-layered memory devices of example embodiment.
Embodiment
Now, with reference to the accompanying drawing that shows some example embodiment of the present invention, various example embodiment of the present invention is described more fully.In the accompanying drawings, for clarity, exaggerated the thickness in layer and region.
Disclosed herein is the embodiment being shown specifically of the present invention.But concrete structure disclosed herein and function detail only represent for the object of describing example embodiment of the present invention.But the present invention can implement with many replacement forms, should not be interpreted as the embodiment that only limits to set forth here.
Therefore, although example embodiment of the present invention can have various modifications and selectable form, in the mode of the example in accompanying drawing, embodiments of the invention are shown, and will be described in detail here.It should be understood, however, that and be not intended to example embodiment of the present invention to be restricted to disclosed concrete form, but contrary, example embodiment of the present invention is intended to cover all modifications that fall within the scope of the present invention, equivalent and alternative.In the whole description of accompanying drawing, identical label represents identical element.
Although it should be understood that and can describe various elements by first, second grade of term here, these elements are not limited by these terms should.These terms are only used to distinguish an element and another element.For example, in the case of not departing from the scope of illustrated embodiments of the invention, the first element can be called as the second element, and similarly, the second element can be called as the first element.As used herein, term "and/or" comprises one or more relevant any and all combinations of lising.
In addition, it should be understood that it can directly connect or be attached to another element, or can have intermediary element in the time that element is called as " connection " or " combination " to another element.On the contrary, in the time that element is called as " directly connection " or " directly combination " to another element, there is not intermediary element.Should explain in an identical manner other word for describing the relation between element (for example, " and ... between " with " and directly exist ... between ", " adjacent " and " direct neighbor " etc.).
In addition, it should be understood that when element or layer be called as " being formed on " another element or layer " on " time, it can be formed on directly or indirectly another element or layer on., for example, can there is intermediary element or layer.On the contrary, when element or layer be called as " being formed directly into " another element " on " time, do not exist intermediary element or layer.Should explain in an identical manner other word for describing the relation between element or layer (for example, " and ... between " with " and directly exist ... between ", " adjacent " and " direct neighbor " etc.).
Term used herein only, for the object of describing specific embodiment, is not intended to limit example embodiment of the present invention.As used herein, unless context clearly point out in addition, otherwise singulative is intended to comprise plural form.It should also be understood that, when using term " to comprise " here and/or when " comprising ", show to exist described feature, entirety, step, operation, element and/or assembly, exist or add one or more other feature, entirety, step, operation, element, assembly and/or their groups but do not get rid of.
Should also be understood that in some optional embodiments, the function/action of mark can be with occurring in sequence beyond the order marking in accompanying drawing.For example, according to relevant function/action, in fact two accompanying drawings that illustrate continuously can substantially side by side be carried out, or sometimes can carry out in reverse order.
Describe more fully according to multi-layered memory devices of the present invention now with reference to the accompanying drawing that shows illustrated embodiments of the invention.In the accompanying drawings, for clarity, thickness and the width of layer have been exaggerated.
Can there is such structure according to the multi-layered memory devices of example embodiment, that is, comprise that multiple storage unit of one or more accumulation layers are formed in multi-layered memory devices.Active circuit unit can be included in each in multiple storage unit.Can stacking described one or more accumulation layer to form each in multiple storage unit.Each in multiple storage unit can be controlled in active circuit unit.In active circuit unit and multiple storage unit each can by composition storage sets.Multi-layered memory devices can have such structure, that is, multiple storage sets are stacking each other.By be formed with source circuit unit in non-silicon base, can form each in multiple storage unit and active circuit unit by depositing operation rather than by bonding technology order.According in the multi-layered memory devices of example embodiment, active circuit unit can be formed in the position of any desired at bottom, middle part or the top of multiple storage unit.
Figure 1A is the diagram illustrating according to the multi-layered memory devices of example embodiment.With reference to Figure 1A, storage unit 12 can comprise the lip-deep multiple accumulation layer a1 to an that are formed on active circuit unit 11.Active circuit unit 11 and the lip-deep storage unit 12 that is formed on active circuit unit 11 can form the example embodiment of multi-layered memory devices.The quantity that can be formed in the accumulation layer a1 to an on active circuit unit 11 is unrestricted.Active circuit unit 11 can comprise demoder.Demoder can also comprise row decoder (RD) and column decoder (CD).Each can being formed in multiple accumulation layer a1 to an has the array structure that comprises multiple storage cells (cell).
With reference to Figure 1B, each in multiple accumulation layer a1 to an can be point of crossing formula memory array structure.In the example embodiment shown in Figure 1B, information memory cell 103 and construction of switch 104 (for example, diode, transistor etc.) can be formed on the each point of crossing place between many first electrode wires 101 that form along first direction and many second electrode wires 102 that form along second direction.Many the first electrode wires 101 can be formed as being perpendicular to one another with many second electrode wires 102 or be substantially vertical.Information memory cell 103 can have various forms of storage organizations.For example, information memory cell 103 can be formed by the ferroelectric condenser of the memory element as reversible construction or irreversible structure, magnetoresistive element, phase-change element, variable resistor element, anti-fuse etc.In addition, in multiple accumulation layer a1 to an, adjacent accumulation layer can be formed as shared electrode and be stacked.
Each in multiple accumulation layer a1 to an can comprise storage array.Fig. 1 C illustrates the example embodiment of storage array 120.Fig. 1 D illustrates another example embodiment of the storage array that comprises multiple subarrays 121.Each storage array that can comprise the storage array shown in Fig. 1 C and Fig. 1 D in multiple accumulation layer a1 to an.Can be bonded to each other ground or use individually each in the example embodiment shown in Fig. 1 C and Fig. 1 D.For example, in example embodiment, can as shown in Fig. 1 C, construct accumulation layer a1, and can construct as shown in Figure 1 D accumulation layer a2.According to example embodiment, the accumulation layer shown in Fig. 1 C and Fig. 1 D can be replaced stacking to form memory storage.Selectively, can as shown in Fig. 1 C, construct each in accumulation layer a1 to an.In another example, can construct as shown in Figure 1 D each in accumulation layer a1 to an.
Fig. 2 A and Fig. 2 B are the diagrams illustrating according to the multi-layered memory devices of another example embodiment.For example, Fig. 2 A and Fig. 2 B illustrate such structure, that is, sequence stack includes the storage sets of source circuit unit and storage unit.
With reference to Fig. 2 A, memory storage can comprise multiple storage sets of stacking (for example, vertical stacking) each other.Each in multiple storage sets can include source circuit unit and storage unit.Each storage unit can comprise one or more accumulation layers.For example, the first storage sets can comprise the first active circuit unit 21 and the first storage unit 22.The first storage unit 22 can comprise multiple accumulation layers, and can be arranged in 21 tops, the first active circuit unit or be arranged on the first active circuit unit 21.The first storage sets can be formed in logical circuit or logical block 20.Logical block 20 also can be used as active circuit.The second storage sets can comprise the second active circuit unit 23 and the storage unit 24 being arranged in above 23 surfaces, the second active circuit unit.The second storage sets can be stacked in the first storage sets.The 3rd storage sets can comprise the 3rd active circuit unit 25 and the 3rd storage unit 26 being arranged in above 25 surfaces, the 3rd active circuit unit.The 3rd storage sets can be arranged in the second storage sets.
In the structure of Fig. 2 A, each in storage unit 22,24 and 26 can be respectively formed on each in active circuit unit 21,23 and 25.Logical block 20 can comprise logical circuit, and can select one or more in active circuit unit 21,23 and 25.Each in active circuit unit 21,23 and 25 can comprise demoder, and one or more in can select storage unit 22,24 and 26.Demoder can comprise row decoder (RD) and column decoder (CD).
At least can comprise and can select one or more storage unit 22,24 and 26 multiple active circuits unit 21,23 and 25 that can recording and reconstruction information according to the multi-layered memory devices of this example embodiment.Multi-layered memory devices can also comprise the logical block 20 of controlling active circuit unit 21,23 and 25.Traditional memory storage has such structure, that is, active circuit unit is formed in silicon base, and multiple accumulation layer is formed on active circuit unit.But active circuit unit is designed to individual unit, thereby need many through holes (via hole), and need complicated Wiring technique.Different from traditional technology, at least according to the multi-layered memory devices of this example embodiment, the active circuit unit of multiple accumulation layers and the described multiple accumulation layers of control is grouped into storage sets, and multiple storage sets are stacking each other, therefore, the quantity of the storage unit that can be stacked is unrestricted.
With reference to Fig. 2 B, at least according to this example embodiment, memory storage can comprise multiple storage sets, each source circuit unit and the storage unit of including in multiple storage sets.Each storage unit can comprise multiple accumulation layers.Multiple storage sets can be stacked in logical circuit or logical block.
At least, in this example embodiment, the first storage unit 201 can be formed in logical block 200.The first active circuit unit 202 can be formed in the first storage unit 201.The first storage unit 201 and the first active circuit unit 202 form the first storage sets.The second storage unit 203 and the second active circuit unit 204 can be formed on the first active circuit unit 202.The second storage unit 203 and the second active circuit unit 204 form the second storage sets.The 3rd storage unit 205 and the 3rd active circuit unit 206 can be formed on the second active circuit unit 204.The 3rd storage unit 205 and the 3rd active circuit unit 206 form the 3rd storage sets.
In the structure of Fig. 2 B, active circuit unit 202,204 and 206 can be respectively formed in storage unit 201,203 and 205, comprise the storage sets of storage unit and active circuit unit can sequence stack in logical block 200.Logical block 200 can comprise logical circuit, and can select one or more in active circuit unit 202,204 and 206.Each in active circuit unit 202,204 and 206 can comprise demoder, and one or more in can select storage unit 201,203 and 205.Demoder can comprise row decoder (RD) and column decoder (CD).
Fig. 2 C and Fig. 2 D are for describing according to the diagram of the drive principle of the multi-layered memory devices of example embodiment.
With reference to Fig. 2 C, at least can there is such structure according to the multi-layered memory devices of an example embodiment, that is, multiple storage unit M and multiple active circuit cells D are formed on (for example,, as shown in Fig. 2 A or Fig. 2 B) in logical block 210.Logical block 210 can select line 221 to be connected to multiple active circuit cells D by demoder, and can from multiple active circuit cells D, select specific active circuit unit.Can select by being connected to the memory address of logical block 210 and multiple active circuit cells D the address (row and column) of the storage unit of line input expectation.Can select signal by line 222a and alignment 222b input memory address.Can select specific accumulation layer in multiple storage unit M by storage level demoder.To be described in detail this with reference to Fig. 2 D below.
With reference to Fig. 2 D, multiple storage unit 211 and 213 and multiple active circuits unit 212 and 214 can be formed in logical block 210.The first active circuit unit 212 can write data the first storage unit 211, and from the first storage unit 211 reading out datas.The second active circuit unit 214 can write data the second storage unit 213, and from the second storage unit 213 reading out datas.In the time that active circuit unit and storage unit are grouped into the storage sets for being represented by the G in Fig. 2 D, multiple (for example, unlimited) storage sets G can be formed on the second active circuit unit 214.
Fig. 3 is the diagram illustrating according to the multi-layered memory devices of another example embodiment.At least according to this example embodiment, storage unit can be formed on each in many sides of active circuit unit.
With reference to Fig. 3, storage unit 32 and 33 can be formed on the top surface and basal surface of active circuit unit 31.The first storage unit 32 can comprise one or more (for example, multiple) accumulation layer b1 to bn.The second storage unit 33 can comprise one or more (for example, multiple) accumulation layer c1 to cn.The quantity that can be included in the accumulation layer in storage unit 32 and 33 does not limit.Active circuit unit 31 can comprise the demoder of the one or more accumulation layer b1 to bn in can select storage unit 32 and/or the one or more accumulation layer c1 to cn in storage unit 33.Active circuit unit 31 can comprise that (step-down) circuit, booster circuit, testing circuit and/or reference voltage circuit fall in sensing amplifier, impact damper, step.
Fig. 4 is the diagram illustrating according to the multi-layered memory devices of another example embodiment.Fig. 4 illustrates such structure,, multiple storage sets can be stacking each other, wherein, each two (for example, relative) lip-deep one or more storage unit that include source circuit unit and be formed on active circuit unit in multiple storage sets.
With reference to Fig. 4, the first storage sets can be arranged on logical circuit 40.The first storage sets can comprise the first active circuit unit 42 and be formed on the second storage unit 43 on the apparent surface of the first storage unit 41.The second storage sets can be formed on the first storage sets top.The second storage sets can comprise the 3rd storage unit 44 and the 4th storage unit 46 on the apparent surface who is formed on the second active circuit unit 45.Logical block 40 can comprise logical circuit, and can select one or more in active circuit unit 42 and 45.Each in active circuit unit 42 and 45 can comprise demoder.One or more in the lip- deep storage unit 41 and 43 of active circuit unit 42 can be selected to be formed in active circuit unit 42.One or more in the lip- deep storage unit 44 and 46 of active circuit unit 45 can be selected to be formed in active circuit unit 45.
Fig. 5 is the diagram illustrating according to the multi-layered memory devices of another example embodiment.In the multi-layered memory devices of Fig. 5, it is upper with select storage unit that column decoder (CD) and row decoder (RD) can be formed on the layer separating.
With reference to Fig. 5, the first storage unit 53 can be formed on the first active circuit unit 51a.The second active circuit unit 52a, the second storage unit 54 and the 3rd active circuit unit 51b can be formed in the first storage unit 53.The first active circuit unit 51a and the 3rd active circuit unit 51b can comprise in CD and RD.If the first active circuit unit 51a and the 3rd active circuit unit 51b comprise CD, the second active circuit unit 52a can comprise RD.Selectively, if the first active circuit unit 51a and the 3rd active circuit unit 51b comprise RD, the second active circuit 52a can comprise CD.
The first storage unit 53 can comprise one or more accumulation layer d1 to dn, and the second storage unit 54 can comprise one or more accumulation layer e1 to en.The quantity that can be formed in the accumulation layer on active circuit unit does not limit.Each in active circuit unit 51a, 52a and 51b can be connected to one or more in the first storage unit 53 and the second storage unit 54 along direction up and down, to select the one or more accumulation layer e1 to en in one or more accumulation layer d1 to dn or the second storage unit 54 in the first storage unit 53.For example, if the first active circuit unit 51a comprises CD and the second active circuit unit 52a and comprise RD, the first active circuit unit 51a and the second active circuit unit 52a can be used to select the one or more accumulation layer d1 to dn in the first storage unit 53.Similarly, if the 3rd active circuit unit 51b comprises CD and the second active circuit unit 52a and comprise RD, the second active circuit unit 52a and the 3rd active circuit unit 51b can be used to select the one or more accumulation layer e1 to en in the second storage unit 53.
Fig. 6 is the diagram illustrating according to the multi-layered memory devices of another example embodiment.
With reference to Fig. 6, the first active circuit unit 61 and the first storage unit 64 can be formed in logical block 60.The second active circuit unit 62 and the second storage unit 65 can be formed in the first storage unit 64.The 3rd active circuit unit 63 and the 3rd storage unit 66 can be formed on the second storage unit 65 tops.Logical block 60 can comprise logical circuit, and can select one or more in active circuit unit 61,62 and 63.Each of can comprise in CD and RD in active circuit unit 61,62 and 63, and can distinguish one or more in select storage unit 64,65 and 66.At least according to this example embodiment, the first storage unit 64 can be formed on the second surface of active circuit unit 61 and on the first surface of the second active circuit unit 62.The second storage unit 65 can be formed on the second surface of the second active circuit unit 62 and the first surface of the 3rd active circuit unit 63.The 3rd storage unit 66 can be formed on the second surface of the 3rd active circuit unit 63.Form by order in logical block 60 the active circuit unit and the storage unit that comprise CD or RD, can form stacking structure.
Selectively, each CD and the RD of all can comprising in active circuit unit 61,62 and 63.At least, in this example embodiment, the RD of the CD of the first active circuit unit 61 and the second active circuit unit 62 can be used to the first storage unit 64 addressing.The RD of the CD of the second active circuit unit 62 and the 3rd active circuit unit 63 can be used to the second storage unit 65 addressing.
Selectively, the CD of the RD of the first active circuit unit 61 and the second active circuit unit 62 can be used to the first storage unit 64 addressing, and the CD of the RD of the second active circuit unit 62 and the 3rd active circuit unit 63 can be for to the second storage unit 65 addressing.
As mentioned above, at least can be formed as intersecting point type storage array according to the accumulation layer of the multi-layered memory devices of some example embodiment.For example, many bottom electrode lines and can being formed in each accumulation layer with many polar curves that power on that many bottom electrode lines intersect, construction of switch and charge storage structure can sequentially be formed on many and power in polar curve and many bottom electrode lines region intersected with each other.Many bottom electrode lines and many polar curves that power on can be connected to RD or the CD of active circuit unit independently.
Each accumulation layer can comprise storage array, different from conventional art, and each accumulation layer can not comprise independent storage array enable circuits.At least, according in the multi-layered memory devices of some example embodiment, logical block 60 can be formed in silicon base or non-silicon base.For example, after the logical circuit that forms logical block 60 is formed in the one in silicon base and non-silicon base, can carry out interlayer dielectric (ILD) technique.Then, storage unit and active circuit unit can repeatedly be formed in logical block 60.Non-silicon base be exemplified as plastic-substrates, substrate of glass, ceramic bases, oxide base or the nitride based end.Active circuit unit can comprise demoder, preferably, can comprise that circuit, booster circuit, testing circuit and/or reference voltage circuit fall in sensing amplifier, impact damper, step.Traditionally, active circuit unit is formed in silicon base, and area is restricted, and accessible storage cell area is also restricted, and the quantity of stackable accumulation layer is restricted.But according to example embodiment, active circuit unit can be formed between each storage unit, thereby can overcome such restriction.
Fig. 7 A and Fig. 7 B are the diagrams illustrating according to the array structure of the decoder circuit of the active circuit unit of the multi-layered memory devices of another example embodiment, and wherein, the structure of multi-layered memory devices is that storage unit is formed on a surface of active circuit unit.Each decoder circuit can comprise RD and CD.
With reference to Fig. 7 A, RD and CD can be formed on active circuit unit 71.From the upwardly extending row address line r of RD, active circuit unit 71 is connected to the storage unit 72 that is arranged in 71 tops, active circuit unit by path V.Also active circuit unit 71 is connected to storage unit 72 by path V from the upwardly extending column address conductor c of CD.If storage unit 72 comprises one or more accumulation layers, row address line r and column address conductor c can be connected to each in one or more accumulation layers.
With reference to Fig. 7 B, active circuit unit 701 can comprise RD and CD.Row address line r from from RD to downward-extension is connected to active circuit unit 701 storage unit 702 that is arranged in 701 belows, active circuit unit by path V.Column address conductor c from from CD to downward-extension is also connected to storage unit 702 by active circuit unit 701 by path V.If storage unit 702 comprises one or more accumulation layers, row address line r and column address conductor c can be connected to each in one or more accumulation layers.
Be formed in the structure on active circuit unit 701 at RD and CD, storage unit (each storage unit comprises multiple accumulation layers) is formed on the top surface and basal surface of active circuit unit 701 simultaneously, and row address line r and column address conductor c can be connected to each in multiple accumulation layers.
Fig. 8 A and Fig. 8 B are the diagrams illustrating according to the structure of the multi-layered memory devices of example embodiment, wherein, one in RD circuit and CD circuit is formed on storage unit below, another in RD circuit and CD circuit is formed on storage unit top, thereby records the information in reading information in multi-layered memory devices and from multi-layered memory devices.
With reference to Fig. 8 A, storage unit 82 and the second active circuit unit 83 can sequentially be formed on the first active circuit unit 81.CD can be formed on the first active circuit unit 81, and RD can be formed on the second active circuit unit 83.Can be connected to storage unit 82 by path V from the upwardly extending column address conductor c of CD of the first active circuit unit 81.As shown in Figure 8 A, the CD of the first active circuit unit 81 can be connected in alternating fashion to storage unit 82, thereby the adjacent row of storage array are connected to the different sidepiece of CD.For example, first in two adjacent row can be connected to the path V at the first sidepiece place of the first active circuit unit 81, and in two adjacent row of storage unit 82 second can be connected to the second relative sidepiece of CD.Can be connected to storage unit 82 from the RD of the second active circuit unit 83 by path V to the row address line r of downward-extension.As shown in Figure 8 A, the RD of the second active circuit unit 83 can be connected to storage unit 82 with the form replacing, thereby the adjacent row of storage array is connected to the different sidepiece of RD.For example, first in two adjacent row can be connected to the path V at the first sidepiece place of the second active circuit unit 83, and in two adjacent row of storage unit 82 second can be connected to the second relative sidepiece of the second active circuit unit 83.The first sidepiece that row address line r is connected to is different with the second sidepiece with the first sidepiece that the second sidepiece can be connected to from column address conductor c.
If storage unit 82 is formed as having multiple accumulation layers, row address line r and column address conductor c can be connected to each in multiple accumulation layers.
In Fig. 8 B, can be connected to storage unit 802 by the path V on a side of the first active circuit unit 801 only from the upwardly extending column address conductor c of CD of the first active circuit unit 801.The row address line r extending from the RD of the second active circuit unit 803 can be connected to storage unit 802 by the path V at the front end of the second active circuit unit 803 only.If storage unit 802 comprises multiple accumulation layers, row address line r and column address conductor c can be connected to each in multiple accumulation layers.
Fig. 9 A and Fig. 9 B are the structures illustrating according to the multi-layered memory devices of another example embodiment, wherein, alternately form path V to increase in multi-layered memory devices the density of the address wire of extending from CD and RD.
With reference to Fig. 9 A, RD and CD can be formed on the first corresponding sidepiece of active circuit unit 91 and the end of the second sidepiece.Storage unit 92 can be formed on 91 belows, active circuit unit.The row address line r and the column address conductor c that extend from RD and the CD of active circuit unit 91 respectively can be connected to storage unit 92 by path V.Path V can alternately be formed as mutual biasing along given direction.For example, the path V that is connected to row address line r can setover mutually along the vertical direction of the direction of extending with the first sidepiece of active circuit unit 91.Similarly, the path V that is connected to column address conductor c can setover mutually along the vertical direction of the direction of extending with the second sidepiece of active circuit unit 91.
With reference to Fig. 9 B, active circuit unit 901 can comprise RD and CD.In this example embodiment, CD can be formed on the first sidepiece of active circuit unit 901 and the end of the second sidepiece, and RD can be formed on the 3rd sidepiece of active circuit unit 901 and the end of the 4th sidepiece.The first sidepiece and the second sidepiece can be toward each other, and the 3rd sidepiece and the 4th sidepiece can be toward each other.Storage unit 902 can be formed on 901 belows, active circuit unit.The row address line r and the column address conductor c that extend from RD and the CD of active circuit unit 901 respectively can be connected to storage unit 902 by path V.Path V can alternately be formed as mutual biasing along given direction.For example, the path V that is connected to row address line r can setover mutually along the vertical direction of the direction of extending with the second sidepiece with the first sidepiece of active circuit unit 901.Similarly, the path V that is connected to column address conductor c can setover mutually along the vertical direction of the direction of extending with the 4th sidepiece with the 3rd sidepiece of active circuit unit 901.
Can optionally determine according to the structure of the array apparatus of storage unit 92 and 902 and/or density position and the shape of path V, but example embodiment is not limited to this.Active circuit unit and storage unit shown in each in Fig. 7 A to Fig. 9 B can be grouped into storage sets, and described storage sets can be by repeatedly stacking.Therefore,, compared with only using traditional memory storage of single active circuit unit, can simplify connecting line to reduce the quantity of path.
Figure 10 is the diagram illustrating according to the multi-layered memory devices of another example embodiment.
With reference to Figure 10, multi-layered memory devices 100 can comprise the parallel bus 103 of the storage area 102, input/input (I/O) chip 104, connection storage area 102 and the I/O chip 104 that are formed in substrate 101 and be connected I/O chip 104 and the universal serial bus 105 of main device or module (not shown).For example, as mentioned above, storage area 102 can have sandwich construction.
According to example embodiment, can manufacture various electronic components according to those of ordinary skills' knowledge.For example, according to the multi-layered memory devices of example embodiment can be used as various products (such as, Mobile or cellular telephone, smart phone, personal digital assistant (PDA), on knee or desktop PC, digital camera, digital camera, MP3 or other portable music player etc.) media apparatus.
Although specifically illustrate and described example embodiment with reference to the example embodiment shown in accompanying drawing, but it should be understood by one skilled in the art that, do not departing under the condition of the spirit and scope that are defined by the claims of the present invention, can make in the present invention the change in form and details.
Claims (29)
1. a multi-layered memory devices, comprising:
Two or more storage unit;
Active circuit unit, is arranged between each in described two or more storage unit, and each active circuit unit comprises demoder;
Logical block, comprises logical circuit, and selects one or more in active circuit unit, wherein, described two or more storage unit and active circuit element stack in logical block,
Wherein, demoder comprises at least one in column decoder and row decoder,
Wherein, column address conductor is connected to described two or more storage unit by column decoder by path, and row address line is connected to described two or more storage unit by row decoder by path.
2. multi-layered memory devices as claimed in claim 1, wherein, each storage unit comprises one or more accumulation layer.
3. multi-layered memory devices as claimed in claim 2, wherein, accumulation layer is for intersecting point type storage array.
4. multi-layered memory devices as claimed in claim 3, wherein, multiple subarrays are formed in accumulation layer.
5. multi-layered memory devices as claimed in claim 3, wherein, the point type storage array that intersects has the structure of adjacent accumulation layer shared electrode.
6. multi-layered memory devices as claimed in claim 1, wherein, active circuit unit is formed in non-silicon base.
7. multi-layered memory devices as claimed in claim 6, wherein, non-silicon base is plastic-substrates, substrate of glass, ceramic bases, oxide base and the one at the nitride based end.
8. multi-layered memory devices as claimed in claim 1, wherein, active circuit unit and described two or more storage unit composition storage sets, and multiple storage sets is stacking each other.
9. multi-layered memory devices as claimed in claim 1, wherein, active circuit unit comprises the first active circuit unit and the second active circuit unit, the first active circuit unit comprises column decoder, the second active circuit unit comprises row decoder, and at least one in described two or more storage unit is connected to each in the first active circuit unit and the second active circuit unit.
10. multi-layered memory devices as claimed in claim 9, wherein, column address conductor is connected at least one in described two or more storage unit by the column decoder of the first active circuit unit by path, and row address line is connected at least one in described two or more storage unit by the row decoder of the second active circuit unit by path.
11. multi-layered memory devices as claimed in claim 1, also comprise:
Storage area, is formed in substrate, and storage area comprises described two or more storage unit and active circuit unit;
I/O chip, is connected to storage area and parallel bus;
Universal serial bus, is connected to main device by I/O chip.
12. 1 kinds of multi-layered memory devices, comprising:
Multiple storage sets, stacking each other, each storage sets comprises the active circuit unit of storage unit and control store unit, active circuit unit comprises at least one in column decoder and row decoder;
Logical block, comprises logical circuit, and selects one or more in active circuit unit, and wherein, described multiple storage sets are stacked in logical block,
Wherein, column address conductor is connected to two or more storage unit by column decoder by path, and row address line is connected to two or more storage unit by row decoder by path.
13. multi-layered memory devices as claimed in claim 12, wherein, storage unit comprises one or more accumulation layer.
14. multi-layered memory devices as claimed in claim 13, wherein, accumulation layer is for intersecting point type storage array.
15. multi-layered memory devices as claimed in claim 14, wherein, multiple subarrays are formed in described one or more accumulation layer.
16. multi-layered memory devices as claimed in claim 14, wherein, the point type storage array that intersects has the structure of adjacent accumulation layer shared electrode.
17. multi-layered memory devices as claimed in claim 12, wherein, active circuit unit is formed in non-silicon base.
18. multi-layered memory devices as claimed in claim 12, wherein, active circuit unit comprises that the first active circuit unit with column decoder and the second active circuit unit with row decoder, storage unit are connected to each in the first active circuit unit and the second active circuit unit.
19. multi-layered memory devices as claimed in claim 18, wherein, column address conductor is connected to storage unit by the column decoder of the first active circuit unit by path, and row address line is connected to storage unit by the row decoder of the second active circuit unit by path.
20. 1 kinds of multi-layered memory devices, comprising:
At least one active circuit, comprises demoder;
At least one storage unit, each at least one demoder that is connected in described at least one storage unit, described at least one storage unit is separated with described at least one active circuit, and described at least one active circuit is arranged in above or below described at least one storage unit;
Logical circuit, selects one or more in active circuit, wherein, described at least one active circuit and described at least one stacked memory cell on logical circuit,
Wherein, demoder comprises at least one in row decoder and column decoder,
Wherein, column address conductor is connected to described at least one storage unit by column decoder by path, and row address line is connected to described at least one storage unit by row decoder by path.
21. multi-layered memory devices as claimed in claim 20, wherein, described at least one storage unit comprises:
Multiple accumulation layers, stacking each other, the each demoder that is connected in described multiple accumulation layers.
22. multi-layered memory devices as claimed in claim 20, wherein, demoder through from described at least one active circuit unit up or down vertically extending address wire be connected to each described at least one storage unit.
23. multi-layered memory devices as claimed in claim 20, wherein, demoder comprises row decoder and column decoder, column decoder comprises the first row decoder circuit at the first sidepiece place that is arranged in described at least one active circuit unit and is arranged in the secondary series decoder circuit at the second sidepiece place of described at least one active circuit unit, row decoder comprises the first row decoder circuit at the 3rd sidepiece place that is arranged in described at least one active circuit unit and is arranged in second row decoder circuit at the 4th sidepiece place of described at least one active circuit unit, wherein
The first sidepiece and the second sidepiece toward each other,
The 3rd sidepiece and the 4th sidepiece are toward each other.
24. multi-layered memory devices as claimed in claim 23, wherein, column decoder by from described at least one active circuit unit up or down vertically extending column address conductor be connected to each described at least one storage unit.
25. multi-layered memory devices as claimed in claim 24, wherein, column address conductor is connected to described at least one storage unit by being arranged in the path at least one sidepiece place of active circuit unit, and described path is setovered mutually along the vertical direction of the direction of extending with described at least one sidepiece.
26. multi-layered memory devices as claimed in claim 23, wherein, row decoder by from described at least one active circuit unit up or down vertically extending row address line be connected to each described at least one storage unit.
27. multi-layered memory devices as claimed in claim 26, wherein, row address line is connected to described at least one storage unit by being arranged in the path at least one sidepiece place of active circuit unit, and described path is setovered mutually along the vertical direction of the direction of extending with described at least one side.
28. multi-layered memory devices as claimed in claim 20, wherein, described at least one storage unit comprises at least one accumulation layer, described at least one accumulation layer comprises at least one storage array.
29. multi-layered memory devices as claimed in claim 20, also comprise:
Storage area, is formed in substrate, and storage area comprises described at least one storage unit and described at least one active circuit unit;
Input/input chip, is connected to storage area and parallel bus;
Universal serial bus, is connected to main device by I/O chip.
Applications Claiming Priority (6)
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| KR20070092651 | 2007-09-12 | ||
| KR1020070092651 | 2007-09-12 | ||
| KR10-2007-0092651 | 2007-09-12 | ||
| KR1020080047092 | 2008-05-21 | ||
| KR1020080047092A KR100935936B1 (en) | 2007-09-12 | 2008-05-21 | Multi-Layered Memory Apparatus |
| KR10-2008-0047092 | 2008-05-21 |
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| CN101388236A CN101388236A (en) | 2009-03-18 |
| CN101388236B true CN101388236B (en) | 2014-06-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2010263211A (en) * | 2009-05-04 | 2010-11-18 | Samsung Electronics Co Ltd | Laminated memory element |
| KR20110105255A (en) | 2010-03-18 | 2011-09-26 | 삼성전자주식회사 | Stacked memory device and method of fabricating the same |
| KR101738533B1 (en) | 2010-05-24 | 2017-05-23 | 삼성전자 주식회사 | Stacked memory devices and method of manufacturing the same |
| KR20110135299A (en) | 2010-06-10 | 2011-12-16 | 삼성전자주식회사 | Semiconductor memory device |
| KR101772117B1 (en) | 2010-09-03 | 2017-08-28 | 삼성전자 주식회사 | Semiconductor Memory Device of stacked structure having logic circuit based on resistor switch and Manufacturing method of the same |
| WO2013147743A1 (en) * | 2012-03-26 | 2013-10-03 | Intel Corporation | Three dimensional memory control circuitry |
| CN106782666B (en) * | 2015-11-25 | 2020-05-05 | 北京大学深圳研究生院 | Three-dimensional stacked memory |
| US9792958B1 (en) * | 2017-02-16 | 2017-10-17 | Micron Technology, Inc. | Active boundary quilt architecture memory |
| US10347333B2 (en) | 2017-02-16 | 2019-07-09 | Micron Technology, Inc. | Efficient utilization of memory die area |
| CN113454718A (en) | 2019-02-22 | 2021-09-28 | 株式会社半导体能源研究所 | Semiconductor device and electric appliance having the same |
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| US5991224A (en) * | 1998-05-22 | 1999-11-23 | International Business Machines Corporation | Global wire management apparatus and method for a multiple-port random access memory |
| KR20010088672A (en) * | 2001-08-20 | 2001-09-28 | 심재택 | pile-up type semi-conductor structure and semi-conductor thereof |
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| KR20090027561A (en) | 2009-03-17 |
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