CN101388236A - Multi-layered memory devices - Google Patents
Multi-layered memory devices Download PDFInfo
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- CN101388236A CN101388236A CN200810213119.1A CN200810213119A CN101388236A CN 101388236 A CN101388236 A CN 101388236A CN 200810213119 A CN200810213119 A CN 200810213119A CN 101388236 A CN101388236 A CN 101388236A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
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Abstract
A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array.
Description
Technical field
The present invention relates to a kind of multi-layered memory devices.
Background technology
Along with Development of Multimedia Technology, the more bulky information storage need for equipment that is used for computing machine, communicator etc. is increased.In order to satisfy the demand of this increase, developed massaging device with high relatively information storage density and relative high operating speed.
Usually, memory storage includes source circuit unit and storage unit.The active circuit unit comprises address decoder, reads/write down logic controller, sensing amplifier, output buffer, multiplexer and other assembly to be to read and record data.These assemblies are commonly called " top arrangement (overhead) ", and occupy the part of physical storage areas.If the zone that top arrangement occupies is less relatively, then bigger zone can be used as storage area.In order to increase the density of memory storage, carried out the research that is intended to form multi-layered memory devices.
Summary of the invention
Example embodiment relates to multi-layered memory devices, for example, has the multi-layered memory devices of the sandwich construction that comprises the lip-deep one or more accumulation layer of at least one that be arranged in the active circuit unit.
Example embodiment provides a kind of more highly integrated multi-layered memory devices that can increase the density of data storage.
At least one example embodiment provides a kind of multi-layered memory devices.At least according to this example embodiment, described multi-layered memory devices can comprise: two or more storage unit and active circuit unit.Active circuit element can comprise demoder, and can be formed between in described two or more storage unit each.
At least one other example embodiment provides a kind of multi-layered memory devices.Described multi-layered memory devices can comprise a plurality of storage sets of piling up each other.Storage sets can comprise storage unit and be constructed to the active circuit unit of control store unit.
According to example embodiment, storage unit can comprise one or more accumulation layers.Described one or more accumulation layer is for intersecting the point type storage array.The point type storage array that intersects can have such structure, that is, and and adjacent storage array layer shared electrode.A plurality of subarrays can be formed on the described one or more accumulation layer.The active circuit unit can be formed on the non-silicon base.Non-silicon base can be plastic-substrates, substrate of glass, ceramic bases, oxide base and a kind of at the nitride based end.Each active circuit unit and corresponding storage unit are formed storage sets.A plurality of storage sets can be piled up each other.Each active circuit unit can comprise at least one in column decoder (CD) and the row decoder (RD).
At least according to some example embodiment, the column address conductor that extends from CD can be connected to storage unit by path, and the row address line that extends from RD can be connected to described one or more accumulation layer by path.
At least according to some example embodiment, the active circuit unit can comprise the first active circuit unit and the second active circuit unit, and the first active circuit unit can comprise CD, and the second active circuit unit can comprise RD.Storage unit can be connected to each in the first active circuit unit and the second active circuit unit.The column address conductor that extends from the CD of the first active circuit unit can be connected to storage unit by path, and the row address line that extends from the RD of the second active circuit unit can be connected to described one or more accumulation layer by path.
At least according to some example embodiment, logical block can be formed on one the surface in active circuit unit and the storage unit.Described multi-layered memory devices can also comprise: storage area is formed in the substrate.Storage area comprises storage unit and active circuit unit.I/O (I/O) chip can be connected to storage area and parallel bus.Universal serial bus can connect I/O chip and main device.
At least one other example embodiment provides a kind of multi-layered memory devices.Described multi-layered memory devices can comprise at least one active circuit unit and at least one storage unit.Described at least one memory circuit can comprise demoder.In at least one storage unit each can be connected to demoder.Described at least one storage unit can be separated with described at least one active circuit unit.Described at least one active circuit can be arranged in above or below described at least one storage unit.
At least according to some example embodiment, described at least one storage unit can comprise a plurality of accumulation layers of piling up each other.In described a plurality of accumulation layer each can be connected to demoder.
At least according to some example embodiment, demoder can comprise column decoder and row decoder.Column decoder can comprise first column decoder circuit at the first sidepiece place that is arranged in described at least one active circuit unit and be arranged in the secondary series decoder circuit at the second sidepiece place of described at least one active circuit unit.Row decoder can comprise first row decoder circuit at the 3rd sidepiece place that is arranged in described at least one active circuit unit and be arranged in second row decoder circuit at the 4th sidepiece place of described at least one active circuit unit.First sidepiece and second sidepiece can be toward each other, and the 3rd sidepiece and the 4th sidepiece can be toward each other.
At least according to some example embodiment, demoder can be connected in described at least one storage unit each through the vertically extending up or down address wire in described at least one active circuit unit of associating.Demoder can comprise column decoder and row decoder.Column decoder can be by being connected to each described at least one storage unit from the vertically extending up or down column address conductor in described at least one active circuit unit.Column address conductor can be by being arranged in the active circuit unit the path at least one sidepiece place be connected to described at least one storage unit.Described path can be setovered mutually along the direction vertical with the direction of described at least one sidepiece extension.
At least according to some example embodiment, row decoder can be by being connected to each described at least one storage unit from the vertically extending up or down row address line in described at least one active circuit unit.Row address line can be by being arranged in the active circuit unit the path at least one sidepiece place be connected to described at least one storage unit.Described path is setovered mutually along the direction vertical with the direction of described at least one side extension.
At least according to some example embodiment, described at least one storage unit can comprise at least one accumulation layer.Described at least one accumulation layer can comprise at least one storage array.
Description of drawings
By the detailed description of reference accompanying drawing to example embodiment of the present invention, it is more obvious that the present invention will become, in the accompanying drawing:
Figure 1A is the diagrammatic sketch that illustrates according to the multi-layered memory devices of example embodiment;
Figure 1B to Fig. 1 D is the diagrammatic sketch that illustrates according to the accumulation layer of example embodiment;
Fig. 2 A and Fig. 2 B are the diagrammatic sketch that illustrates according to the multi-layered memory devices of example embodiment;
Fig. 2 C and Fig. 2 D are the diagrammatic sketch that is used to describe according to the example drive principle of the multi-layered memory devices of example embodiment;
Fig. 3 is the diagrammatic sketch that illustrates according to the multi-layered memory devices of another example embodiment;
Fig. 4 is the diagrammatic sketch that illustrates according to the multi-layered memory devices of another example embodiment;
Fig. 5 is the diagrammatic sketch that illustrates according to the multi-layered memory devices of another example embodiment;
Fig. 6 is the diagrammatic sketch that illustrates according to the multi-layered memory devices of another example embodiment;
Fig. 7 A and Fig. 7 B are the diagrammatic sketch as the array structure of the decoder circuit of parts of active circuit unit that illustrates according to the multi-layered memory devices of example embodiment, wherein, the structure of multi-layered memory devices is that storage unit is formed on the surface of active circuit unit;
Fig. 8 A and Fig. 8 B are the diagrammatic sketch that illustrates according to the structure of the multi-layered memory devices of example embodiment, wherein, one in row decoder (RD) circuit and column decoder (CD) circuit is formed on the storage unit below, in RD circuit and the CD circuit another is formed on the storage unit top, thereby the information of storage unit is recorded in the multi-layered memory devices, and from the information of multi-layered memory devices reading cells;
Fig. 9 A and Fig. 9 B are the diagrammatic sketch that illustrates according to the structure of the multi-layered memory devices of example embodiment, wherein, alternately form path (via) V to increase in the multi-layered memory devices from the density of the address wire of CD and RD branch;
Figure 10 is the diagrammatic sketch that illustrates according to the multi-layered memory devices of example embodiment.
Embodiment
Now, with reference to the accompanying drawing that shows some example embodiment of the present invention various example embodiment of the present invention is described more fully.In the accompanying drawings, for clarity, exaggerated the thickness in layer and zone.
Disclosed herein is the embodiment that is shown specifically of the present invention.Yet concrete structure disclosed herein and function detail are only represented for the purpose of describing example embodiment of the present invention.Yet the present invention can implement with many replacement forms, should not be interpreted as the embodiment that only limits to set forth here.
Therefore, though example embodiment of the present invention can have various modifications and selectable form, in the mode of the example in the accompanying drawing embodiments of the invention are shown, and will be described in detail here.It should be understood, however, that not to be intended to example embodiment of the present invention is restricted to disclosed concrete form that but opposite, example embodiment of the present invention is intended to cover all modifications that fall within the scope of the present invention, equivalent and alternative.In the whole description of accompanying drawing, identical label is represented components identical.
Though it should be understood that and to use term here first, second waits and describes various elements that these elements are not limited by these terms should.These terms only are used to distinguish an element and another element.For example, under the situation of the scope that does not break away from illustrated embodiments of the invention, first element can be called as second element, and similarly, second element can be called as first element.As used herein, term " and/or " comprise one or more relevant listd arbitrarily and all combinations.
In addition, it should be understood that it can directly connect or be attached to another element, perhaps can have intermediary element when element is called as " connection " or " combination " to another element.On the contrary, when element is called as " directly connection " or " directly combination " to another element, there is not intermediary element.Should explain in an identical manner the relation that is used to describe between the element other speech (for example, " and ... between " with " and directly exist ... between ", " adjacent " and " direct neighbor " etc.).
In addition, it should be understood that when element or the layer be called as " being formed on " another element or the layer " on " time, it can be formed on directly or indirectly another element or the layer on.That is, for example, can there be intermediary element or layer.On the contrary, when element or the layer be called as " being formed directly into " another element " on " time, do not exist intermediary element or the layer.Should explain in an identical manner other speech of being used to describe the relation between element or the layer (for example, " and ... between " with " and directly exist ... between ", " adjacent " and " direct neighbor " etc.).
Term used herein is only for the purpose of describing specific embodiment, and is not intended to restriction example embodiment of the present invention.As used herein, unless context points out clearly that in addition otherwise singulative is intended to comprise plural form.It should also be understood that, when using term " to comprise " here and/or when " comprising ", show to have described feature, integral body, step, operation, element and/or assembly, do not exist or add one or more other feature, integral body, step, operation, element, assembly and/or their groups but do not get rid of.
Should also be understood that in some optional embodiments the function/action of mark can be with occurring in sequence beyond the order that marks in the accompanying drawing.For example, according to function associated/action, in fact two accompanying drawings that illustrate continuously can substantially side by side be carried out, and perhaps can carry out with opposite order sometimes.
Describe more fully according to multi-layered memory devices of the present invention now with reference to the accompanying drawing that shows illustrated embodiments of the invention.In the accompanying drawings, for clarity, thickness and the width of layer have been exaggerated.
Multi-layered memory devices according to example embodiment can have such structure,, comprises that a plurality of storage unit of one or more accumulation layers are formed in the multi-layered memory devices that is.The active circuit unit can be included in in a plurality of storage unit each.Can pile up described one or more accumulation layer to form each in a plurality of storage unit.In a plurality of storage unit of active circuit unit may command each.In active circuit unit and a plurality of storage unit each can be formed storage sets.Multi-layered memory devices can have such structure, that is, a plurality of storage sets are piled up each other.By on non-silicon base, being formed with the source circuit unit, can form in a plurality of storage unit and the active circuit unit each by depositing operation rather than by the bonding technology order.In the multi-layered memory devices according to example embodiment, the active circuit unit can be formed in the position of any desired at bottom, middle part or top of a plurality of storage unit.
Figure 1A is the diagrammatic sketch that illustrates according to the multi-layered memory devices of example embodiment.With reference to Figure 1A, storage unit 12 can comprise the lip-deep a plurality of accumulation layer a1 to an that are formed on active circuit unit 11.Active circuit unit 11 and the lip-deep storage unit 12 that is formed on active circuit unit 11 can constitute the example embodiment of multi-layered memory devices.The quantity that can be formed in the accumulation layer a1 to an on the active circuit unit 11 is unrestricted.Active circuit unit 11 can comprise demoder.Demoder can also comprise row decoder (RD) and column decoder (CD).Among a plurality of accumulation layer a1 to an each can be formed has the array structure that comprises a plurality of storage cells (cell).
With reference to Figure 1B, each among a plurality of accumulation layer a1 to an can be point of crossing formula memory array structure.In the example embodiment shown in Figure 1B, information memory cell 103 and construction of switch 104 (for example, diode, transistor etc.) can be formed on many first electrode wires 101 forming along first direction and many second electrode wires 102 forming along second direction between each place, point of crossing.Many first electrode wires 101 and many second electrode wires 102 can form and be perpendicular to one another or vertical substantially.Information memory cell 103 can have various forms of storage organizations.For example, information memory cell 103 can be by forming as the ferroelectric condenser of the memory element of reversible construction or irreversible structure, magnetoresistive element, phase-change element, variable resistor element, anti-fuse etc.In addition, adjacent accumulation layer can form shared electrode and be stacked in a plurality of accumulation layer a1 to an.
Among a plurality of accumulation layer a1 to an each can comprise storage array.Fig. 1 C illustrates the example embodiment of storage array 120.Fig. 1 D illustrates another example embodiment of the storage array that comprises a plurality of subarrays 121.Among a plurality of accumulation layer a1 to an each can comprise the storage array of the storage array shown in Fig. 1 C and Fig. 1 D.Can be bonded to each other ground or use in the example embodiment shown in Fig. 1 C and Fig. 1 D each individually.For example, in example embodiment, can as shown in Fig. 1 C, construct accumulation layer a1, and can as shown in Fig. 1 D, construct accumulation layer a2.According to example embodiment, the accumulation layer shown in Fig. 1 C and Fig. 1 D can alternately be piled up to form memory storage.Selectively, can as shown in Fig. 1 C, construct among the accumulation layer a1 to an each.In another example, can as shown in Fig. 1 D, construct among the accumulation layer a1 to an each.
Fig. 2 A and Fig. 2 B are the diagrammatic sketch that illustrates according to the multi-layered memory devices of another example embodiment.For example, Fig. 2 A and Fig. 2 B illustrate such structure, that is, sequence stack includes the storage sets of source circuit unit and storage unit.
With reference to Fig. 2 A, memory storage can comprise each other a plurality of storage sets of piling up (for example, vertical stacking).In a plurality of storage sets each can include source circuit unit and storage unit.Each storage unit can comprise one or more accumulation layers.For example, first storage sets can comprise the first active circuit unit 21 and first storage unit 22.First storage unit 22 can comprise a plurality of accumulation layers, and can be arranged in 21 tops, the first active circuit unit or be arranged on the first active circuit unit 21.First storage sets can be formed on logical circuit or the logical block 20.Logical block 20 also can be used as active circuit.Second storage sets can comprise the second active circuit unit 23 and be arranged on 23 surfaces, the second active circuit unit or the storage unit 24 of top.Second storage sets can be stacked on first storage sets.The 3rd storage sets can comprise the 3rd active circuit unit 25 and be arranged on 25 surfaces, the 3rd active circuit unit or the 3rd storage unit 26 of top.The 3rd storage sets can be arranged on second storage sets.
In the structure of Fig. 2 A, each in the storage unit 22,24 and 26 can be respectively formed in active circuit unit 21,23 and 25 each.Logical block 20 can comprise logical circuit, and can select one or more in active circuit unit 21,23 and 25.In the active circuit unit 21,23 and 25 each can comprise demoder, and one or more in can select storage unit 22,24 and 26.Demoder can comprise row decoder (RD) and column decoder (CD).
At least can comprise according to the multi-layered memory devices of this example embodiment and can select one or more storage unit 22,24 and 26 and can write down and a plurality of active circuits unit 21,23 and 25 of information reproduction.Multi-layered memory devices can also comprise the logical block 20 of control active circuit unit 21,23 and 25.Traditional memory storage has such structure, that is, the active circuit unit is formed on the silicon base, and a plurality of accumulation layer is formed on the active circuit unit.Yet the active circuit unit is designed to individual unit, thereby needs many through holes (via hole), and needs complicated Wiring technique.Different with traditional technology, at least according to the multi-layered memory devices of this example embodiment the active circuit unit packet of a plurality of accumulation layers and the described a plurality of accumulation layers of control is become storage sets, and a plurality of storage sets are piled up each other, and therefore, the quantity of the storage unit that can be stacked is unrestricted.
With reference to Fig. 2 B, at least according to this example embodiment, memory storage can comprise a plurality of storage sets, and each in a plurality of storage sets includes source circuit unit and storage unit.Each storage unit can comprise a plurality of accumulation layers.A plurality of storage sets can be stacked on logical circuit or the logical block.
At least in this example embodiment, first storage unit 201 can be formed on the logical block 200.The first active circuit unit 202 can be formed on first storage unit 201.First storage unit 201 and the first active circuit unit 202 constitute first storage sets.Second storage unit 203 and the second active circuit unit 204 can be formed on the first active circuit unit 202.Second storage unit 203 and the second active circuit unit 204 constitute second storage sets.The 3rd storage unit 205 and the 3rd active circuit unit 206 can be formed on the second active circuit unit 204.The 3rd storage unit 205 and the 3rd active circuit unit 206 constitute the 3rd storage sets.
In the structure of Fig. 2 B, active circuit unit 202,204 and 206 can be respectively formed on storage unit 201,203 and 205, comprise the storage sets of storage unit and active circuit unit can sequence stack on logical block 200.Logical block 200 can comprise logical circuit, and can select one or more in active circuit unit 202,204 and 206.In the active circuit unit 202,204 and 206 each can comprise demoder, and one or more in can select storage unit 201,203 and 205.Demoder can comprise row decoder (RD) and column decoder (CD).
Fig. 2 C and Fig. 2 D are the diagrammatic sketch that is used to describe according to the drive principle of the multi-layered memory devices of example embodiment.
With reference to Fig. 2 C, the multi-layered memory devices according to an example embodiment can have such structure at least, that is, a plurality of storage unit M and a plurality of active circuit cells D are formed on (for example, as shown in Fig. 2 A or Fig. 2 B) on the logical block 210.Logical block 210 can be connected to a plurality of active circuit cells D by demoder selection wire 221, and can select specific active circuit unit from a plurality of active circuit cells D.Can import the address (row and column) of the storage unit of expectation by the memory address selection wire that is connected to logical block 210 and a plurality of active circuit cells D.Can select signal by line 222a and alignment 222b input memory address.Can select specific memory layer among a plurality of storage unit M by the storage level demoder.To be described in detail this with reference to Fig. 2 D below.
With reference to Fig. 2 D, a plurality of storage unit 211 and 213 and a plurality of active circuits unit 212 and 214 can be formed on the logical block 210.The first active circuit unit 212 can write data first storage unit 211, and from first storage unit, 211 reading of data.The second active circuit unit 214 can write data second storage unit 213, and from second storage unit, 213 reading of data.When active circuit unit and storage unit were grouped into to the storage sets represented by the G among Fig. 2 D, a plurality of (for example, do not limit quantity) storage sets G can be formed on the second active circuit unit 214.
Fig. 3 is the diagrammatic sketch that illustrates according to the multi-layered memory devices of another example embodiment.At least according to this example embodiment, storage unit can be formed on in many sides of active circuit unit each.
With reference to Fig. 3, storage unit 32 and 33 can be formed on the top surface and basal surface of active circuit unit 31.First storage unit 32 can comprise one or more (for example, a plurality of) accumulation layer b1 to bn.Second storage unit 33 can comprise one or more (for example, a plurality of) accumulation layer c1 to cn.The quantity that can be included in the accumulation layer in storage unit 32 and 33 without limits.Active circuit unit 31 can comprise one or more accumulation layer b1 to bn in can select storage unit 32 and/or the demoder of the one or more accumulation layer c1 to cn in the storage unit 33.Active circuit unit 31 can comprise that (step-down) circuit, booster circuit, testing circuit and/or reference voltage circuit fall in sensing amplifier, impact damper, step.
Fig. 4 is the diagrammatic sketch that illustrates according to the multi-layered memory devices of another example embodiment.Fig. 4 illustrates such structure, that is, a plurality of storage sets can be piled up each other, and wherein, each in a plurality of storage sets includes the source circuit unit and be formed on two (for example, relative) lip-deep one or more storage unit of active circuit unit.
With reference to Fig. 4, first storage sets can be arranged on the logical circuit 40.First storage sets can comprise the first active circuit unit 42 and be formed on second storage unit 43 on the apparent surface of first storage unit 41.Second storage sets can be formed on first storage sets top.Second storage sets can comprise the 3rd storage unit 44 and the 4th storage unit 46 on the apparent surface who is formed on the second active circuit unit 45.Logical block 40 can comprise logical circuit, and can select one or more in active circuit unit 42 and 45.In the active circuit unit 42 and 45 each can comprise demoder.One or more in the lip-deep storage unit 41 and 43 of active circuit unit 42 can be selected to be formed in active circuit unit 42.One or more in the lip-deep storage unit 44 and 46 of active circuit unit 45 can be selected to be formed in active circuit unit 45.
Fig. 5 is the diagrammatic sketch that illustrates according to the multi-layered memory devices of another example embodiment.In the multi-layered memory devices of Fig. 5, the layer that column decoder (CD) and row decoder (RD) can be formed on is separately gone up with select storage unit.
With reference to Fig. 5, first storage unit 53 can be formed on the first active circuit unit 51a.The second active circuit unit 52a, second storage unit 54 and the 3rd active circuit unit 51b can be formed on first storage unit 53.The first active circuit unit 51a and the 3rd active circuit unit 51b can comprise among CD and the RD.If the first active circuit unit 51a and the 3rd active circuit unit 51b comprise CD, then the second active circuit unit 52a can comprise RD.Selectively, if the first active circuit unit 51a and the 3rd active circuit unit 51b comprise RD, then the second active circuit 52a can comprise CD.
First storage unit 53 can comprise one or more accumulation layer d1 to dn, and second storage unit 54 can comprise one or more accumulation layer e1 to en.The quantity that can be formed in the accumulation layer on the active circuit unit without limits.Among active circuit unit 51a, 52a and the 51b each can be connected to one or more in first storage unit 53 and second storage unit 54 along direction up and down, to select one or more accumulation layer d1 to dn in first storage unit 53 or the one or more accumulation layer e1 to en in second storage unit 54.For example, if the first active circuit unit 51a comprises the CD and the second active circuit unit 52a and comprise RD, then the first active circuit unit 51a and the second active circuit unit 52a can be used to select the one or more accumulation layer d1 to dn in first storage unit 53.Similarly, if the 3rd active circuit unit 51b comprises the CD and the second active circuit unit 52a and comprise RD, then the second active circuit unit 52a and the 3rd active circuit unit 51b can be used to select the one or more accumulation layer e1 to en in second storage unit 53.
Fig. 6 is the diagrammatic sketch that illustrates according to the multi-layered memory devices of another example embodiment.
With reference to Fig. 6, the first active circuit unit 61 and first storage unit 64 can be formed on the logical block 60.The second active circuit unit 62 and second storage unit 65 can be formed on first storage unit 64.The 3rd active circuit unit 63 and the 3rd storage unit 66 can be formed on second storage unit, 65 tops.Logical block 60 can comprise logical circuit, and can select one or more in active circuit unit 61,62 and 63.In the active circuit unit 61,62 and 63 each can comprise among CD and the RD, and can distinguish one or more in select storage unit 64,65 and 66.At least according to this example embodiment, first storage unit 64 can be formed on the second surface of active circuit unit 61 and on the first surface of the second active circuit unit 62.Second storage unit 65 can be formed on the first surface of the second surface of the second active circuit unit 62 and the 3rd active circuit unit 63.The 3rd storage unit 66 can be formed on the second surface of the 3rd active circuit unit 63.Form active circuit unit and the storage unit that comprises CD or RD by order on logical block 60, can form the structure of piling up.
Selectively, each in the active circuit unit 61,62 and 63 all can comprise CD and RD.At least in this example embodiment, the RD of the CD of the first active circuit unit 61 and the second active circuit unit 62 can be used to 64 addressing of first storage unit.The RD of the CD of the second active circuit unit 62 and the 3rd active circuit unit 63 can be used to 65 addressing of second storage unit.
Selectively, the CD of the RD of the first active circuit unit 61 and the second active circuit unit 62 can be used to 64 addressing of first storage unit, and the CD of the RD of the second active circuit unit 62 and the 3rd active circuit unit 63 can be used for 65 addressing of second storage unit.
As mentioned above, can form according to the accumulation layer of the multi-layered memory devices of some example embodiment at least and intersect the point type storage array.For example, many bottom electrode lines and can be formed in each accumulation layer with many polar curves that power on that many bottom electrode lines intersect, construction of switch and charge storage structure can be formed in many power on polar curve and the many bottom electrode lines zone intersected with each other in proper order.Many bottom electrode lines and many polar curves that power on can be connected to the RD or the CD of active circuit unit independently.
Each accumulation layer can comprise storage array, and is different with conventional art, and each accumulation layer can not comprise independent storage array enable circuits.In the multi-layered memory devices according to some example embodiment at least, logical block 60 can be formed on silicon base or the non-silicon base.For example, after the logical circuit that forms logical block 60 is formed on a kind of in silicon base and the non-silicon base, can carry out interlayer dielectric (ILD) technology.Then, storage unit and active circuit unit can repeatedly be formed on the logical block 60.Non-silicon base be exemplified as plastic-substrates, substrate of glass, ceramic bases, oxide base or the nitride based end.The active circuit unit can comprise demoder, preferably, can comprise that circuit, booster circuit, testing circuit and/or reference voltage circuit fall in sensing amplifier, impact damper, step.Traditionally, the active circuit unit is formed on the silicon base, makes area be restricted, and accessible storage cell area also is restricted, and the quantity of stackable accumulation layer is restricted.Yet according to example embodiment, the active circuit unit can be formed between each storage unit, thereby can overcome such restriction.
Fig. 7 A and Fig. 7 B are the diagrammatic sketch that illustrates according to the array structure of the decoder circuit of the active circuit unit of the multi-layered memory devices of another example embodiment, and wherein, the structure of multi-layered memory devices is that storage unit is formed on the surface of active circuit unit.Each decoder circuit can comprise RD and CD.
With reference to Fig. 7 A, RD and CD can be formed on the active circuit unit 71.From the upwardly extending row address line r of RD active circuit unit 71 is connected to the storage unit 72 that is arranged in 71 tops, active circuit unit by path V.Also active circuit unit 71 is connected to storage unit 72 by path V from the upwardly extending column address conductor c of CD.If storage unit 72 comprises one or more accumulation layers, then row address line r and column address conductor c can be connected to each in the one or more accumulation layers.
With reference to Fig. 7 B, active circuit unit 701 can comprise RD and CD.The row address line r that extends downwards from RD is connected to the storage unit 702 that is arranged in 701 belows, active circuit unit with active circuit unit 701 by path V.The column address conductor c that extends downwards from CD also is connected to storage unit 702 with active circuit unit 701 by path V.If storage unit 702 comprises one or more accumulation layers, then row address line r and column address conductor c can be connected to each in the one or more accumulation layers.
In RD and CD are formed on structure on the active circuit unit 701, storage unit (each storage unit comprises a plurality of accumulation layers) is formed on the top surface and basal surface of active circuit unit 701 simultaneously, and row address line r and column address conductor c can be connected to each in a plurality of accumulation layers.
Fig. 8 A and Fig. 8 B are the diagrammatic sketch that illustrates according to the structure of the multi-layered memory devices of example embodiment, wherein, one in RD circuit and the CD circuit is formed on the storage unit below, in RD circuit and the CD circuit another is formed on storage unit top, thereby records the information in the multi-layered memory devices and read information from multi-layered memory devices.
With reference to Fig. 8 A, the storage unit 82 and the second active circuit unit 83 can be formed on the first active circuit unit 81 in proper order.CD can be formed on the first active circuit unit 81, and RD can be formed on the second active circuit unit 83.Can be connected to storage unit 82 by path V from the upwardly extending column address conductor c of the CD of the first active circuit unit 81.As shown in Fig. 8 A, the CD of the first active circuit unit 81 can be connected in alternating fashion to storage unit 82, thereby the adjacent row of storage array are connected to the different sidepiece of CD.For example, first in two adjacent row can be connected to the path V at the first sidepiece place of the first active circuit unit 81, and second second relative sidepiece that can be connected to CD in two adjacent row of storage unit 82.Can be connected to storage unit 82 by path V from the downward row address line r that extends of the RD of the second active circuit unit 83.As shown in Fig. 8 A, the RD of the second active circuit unit 83 can be connected to storage unit 82 with the form that replaces, thereby the adjacent row of storage array is connected to the different sidepiece of RD.For example, first in two adjacent row can be connected to the path V at the first sidepiece place of the second active circuit unit 83, and second second relative sidepiece that can be connected to the second active circuit unit 83 in two adjacent row of storage unit 82.First sidepiece that row address line r is connected to can be different with second sidepiece with first sidepiece that column address conductor c is connected to second sidepiece.
Have a plurality of accumulation layers if storage unit 82 forms, then row address line r and column address conductor c can be connected to each in a plurality of accumulation layers.
In Fig. 8 B, can be connected to storage unit 802 by the path V on a side of the first active circuit unit 801 only from the upwardly extending column address conductor c of the CD of the first active circuit unit 801.The row address line r that extends from the RD of the second active circuit unit 803 can be connected to storage unit 802 by the path V at the front end of the second active circuit unit 803 only.If storage unit 802 comprises a plurality of accumulation layers, then row address line r and column address conductor c can be connected to each in a plurality of accumulation layers.
Fig. 9 A and Fig. 9 B are the structures that illustrates according to the multi-layered memory devices of another example embodiment, wherein, alternately form path V to increase in the multi-layered memory devices density of the address wire of extending from CD and RD.
With reference to Fig. 9 A, RD and CD can be formed on the end of first sidepiece of correspondence of active circuit unit 91 and second sidepiece.Storage unit 92 can be formed on 91 belows, active circuit unit.Can be connected to storage unit 92 by path V from the RD of active circuit unit 91 and the row address line r and the column address conductor c of CD extension respectively.Path V can alternately form mutual biasing along given direction.For example, the path V that is connected to row address line r can setover mutually along the vertical direction of the direction of extending with first sidepiece of active circuit unit 91.Similarly, the path V that is connected to column address conductor c can setover mutually along the vertical direction of the direction of extending with second sidepiece of active circuit unit 91.
With reference to Fig. 9 B, active circuit unit 901 can comprise RD and CD.In this example embodiment, CD can be formed on the end of first sidepiece of active circuit unit 901 and second sidepiece, and RD can be formed on the end of the 3rd sidepiece of active circuit unit 901 and the 4th sidepiece.First sidepiece and second sidepiece can be toward each other, and the 3rd sidepiece and the 4th sidepiece can be toward each other.Storage unit 902 can be formed on 901 belows, active circuit unit.Can be connected to storage unit 902 by path V from the RD of active circuit unit 901 and the row address line r and the column address conductor c of CD extension respectively.Path V can alternately form mutual biasing along given direction.For example, the path V that is connected to row address line r can setover mutually along the vertical direction of the direction of extending with first sidepiece of active circuit unit 901 and second sidepiece.Similarly, the path V that is connected to column address conductor c can setover mutually along the vertical direction of the direction of extending with the 3rd sidepiece of active circuit unit 901 and the 4th sidepiece.
Position and the shape that can come optionally to determine path V according to the structure and/or the density of the array apparatus of storage unit 92 and 902, but example embodiment is not limited thereto.Active circuit unit shown among Fig. 7 A to Fig. 9 B each and storage unit can be grouped into storage sets, and described storage sets can repeatedly be piled up.Therefore, compare, can simplify connecting line to reduce the quantity of path with the traditional memory storage that only uses single active circuit unit.
Figure 10 is the diagrammatic sketch that illustrates according to the multi-layered memory devices of another example embodiment.
With reference to Figure 10, multi-layered memory devices 100 can comprise the parallel bus 103 of the storage area 102, input/input (I/O) chip 104, connection storage area 102 and the I/O chip 104 that are formed in the substrate 101 and be connected I/O chip 104 and the universal serial bus 105 of main device or module (not shown).For example, as mentioned above, storage area 102 can have sandwich construction.
According to example embodiment, can make various electronic components according to those of ordinary skills' knowledge.For example, according to the multi-layered memory devices of example embodiment can be used as various products (such as, Mobile or cellular telephone, smart phone, personal digital assistant (PDA), on knee or desktop PC, digital camera, digital camera, MP3 or other portable music player etc.) media apparatus.
Though specifically illustrate and described example embodiment with reference to the example embodiment shown in the accompanying drawing, but it should be understood by one skilled in the art that, under the condition that does not break away from the spirit and scope that are defined by the claims of the present invention, can make the change on form and the details in the present invention.
Claims (35)
1, a kind of multi-layered memory devices comprises:
Two or more storage unit;
The active circuit unit is arranged between each in described two or more storage unit, and each active circuit unit comprises demoder.
2, multi-layered memory devices as claimed in claim 1, wherein, each storage unit comprises one or more accumulation layer.
3, multi-layered memory devices as claimed in claim 2, wherein, accumulation layer is for intersecting the point type storage array.
4, multi-layered memory devices as claimed in claim 3, wherein, a plurality of subarrays are formed on the accumulation layer.
5, multi-layered memory devices as claimed in claim 3, wherein, the point type storage array that intersects has the structure of adjacent accumulation layer shared electrode.
6, multi-layered memory devices as claimed in claim 1, wherein, the active circuit unit is formed on the non-silicon base.
7, multi-layered memory devices as claimed in claim 6, wherein, non-silicon base is plastic-substrates, substrate of glass, ceramic bases, oxide base and a kind of at the nitride based end.
8, multi-layered memory devices as claimed in claim 1, wherein, active circuit unit and described two or more storage unit are formed storage sets, and a plurality of storage sets is piled up each other.
9, multi-layered memory devices as claimed in claim 1, wherein, demoder comprises at least one in column decoder and the row decoder.
10, multi-layered memory devices as claimed in claim 9, wherein, column address conductor is connected to described two or more storage unit with column decoder by path, and row address line is connected to described two or more storage unit with row decoder by path.
11, multi-layered memory devices as claimed in claim 1, wherein, the active circuit unit comprises the first active circuit unit and the second active circuit unit, the first active circuit unit comprises column decoder, the second active circuit unit comprises row decoder, and at least one in described two or more storage unit is connected to each in the first active circuit unit and the second active circuit unit.
12, multi-layered memory devices as claimed in claim 11, wherein, column address conductor is connected to described at least one storage unit with the column decoder of the first active circuit unit by path, and row address line is connected to described at least one storage unit with the row decoder of the second active circuit unit by path.
13, multi-layered memory devices as claimed in claim 1 also comprises:
Logical block is formed on one the surface in active circuit unit and the storage unit.
14, multi-layered memory devices as claimed in claim 1 also comprises:
Storage area is formed in the substrate, and storage area comprises described two or more storage unit and active circuit unit;
The I/O chip is connected to storage area and parallel bus;
Universal serial bus is connected to main device with the I/O chip.
15, a kind of multi-layered memory devices comprises:
A plurality of storage sets are piled up each other, and each storage sets comprises the active circuit unit of storage unit and control store unit.
16, multi-layered memory devices as claimed in claim 15, wherein, storage unit comprises one or more accumulation layer.
17, multi-layered memory devices as claimed in claim 16, wherein, accumulation layer is for intersecting the point type storage array.
18, multi-layered memory devices as claimed in claim 17, wherein, a plurality of subarrays are formed on the described one or more accumulation layer.
19, multi-layered memory devices as claimed in claim 17, wherein, the point type storage array that intersects has the structure of adjacent accumulation layer shared electrode.
20, multi-layered memory devices as claimed in claim 15, wherein, the active circuit unit is formed on the non-silicon base.
21, multi-layered memory devices as claimed in claim 15, wherein, the active circuit unit comprises at least one in column decoder and the row decoder.
22, multi-layered memory devices as claimed in claim 21, wherein, column address conductor is connected to storage unit with column decoder by path, and row address line is connected to storage unit with row decoder by path.
23, multi-layered memory devices as claimed in claim 15, wherein, the active circuit unit comprises first active circuit unit with column decoder and the second active circuit unit with row decoder, and storage unit is connected to each in the first active circuit unit and the second active circuit unit.
24, multi-layered memory devices as claimed in claim 23, wherein, column address conductor is connected to storage unit with the column decoder of the first active circuit unit by path, and row address line is connected to storage unit with the row decoder of the second active circuit unit by path.
25, multi-layered memory devices as claimed in claim 15 also comprises:
Logical block is formed on one the surface in active circuit unit and the storage unit.
26, a kind of multi-layered memory devices comprises:
At least one active circuit comprises demoder;
At least one storage unit, in described at least one storage unit each is connected at least one demoder, described at least one storage unit is separated with described at least one active circuit, and described at least one active circuit is arranged in above or below described at least one storage unit.
27, multi-layered memory devices as claimed in claim 26, wherein, described at least one storage unit comprises:
A plurality of accumulation layers are piled up each other, and each in described a plurality of accumulation layers is connected to demoder.
28, multi-layered memory devices as claimed in claim 26, wherein, demoder is connected in described at least one storage unit each through the vertically extending up or down address wire in described at least one active circuit unit of associating.
29, multi-layered memory devices as claimed in claim 26; Wherein, Decoder comprises row decoder and column decoder; Column decoder comprises the first row decoder circuit at the first sidepiece place that is arranged in described at least one active circuit unit and is arranged in the secondary series decoder circuit at the second sidepiece place of described at least one active circuit unit; Row decoder comprises the first row decoder circuit at the 3rd sidepiece place that is arranged in described at least one active circuit unit and is arranged in second row decoder circuit at the 4th sidepiece place of described at least one active circuit unit; Wherein
First sidepiece and second sidepiece toward each other,
The 3rd sidepiece and the 4th sidepiece are toward each other.
30, multi-layered memory devices as claimed in claim 29, wherein, column decoder is by being connected to each described at least one storage unit from the vertically extending up or down column address conductor in described at least one active circuit unit.
31, multi-layered memory devices as claimed in claim 30, wherein, the path at least one the sidepiece place of column address conductor by being arranged in the active circuit unit is connected to described at least one storage unit, and described path is setovered mutually along the vertical direction of the direction of extending with described at least one sidepiece.
32, multi-layered memory devices as claimed in claim 29, wherein, row decoder is by being connected to each described at least one storage unit from the vertically extending up or down row address line in described at least one active circuit unit.
33, multi-layered memory devices as claimed in claim 32, wherein, the path at least one the sidepiece place of row address line by being arranged in the active circuit unit is connected to described at least one storage unit, and described path is setovered mutually along the vertical direction of the direction of extending with described at least one side.
34, multi-layered memory devices as claimed in claim 26, wherein, described at least one storage unit comprises at least one accumulation layer, described at least one accumulation layer comprises at least one storage array.
35, multi-layered memory devices as claimed in claim 26 also comprises:
Storage area is formed in the substrate, and storage area comprises described at least one storage unit and described at least one active circuit unit;
Input/input chip is connected to storage area and parallel bus;
Universal serial bus is connected to main device with the I/O chip.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
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| KR1020070092651 | 2007-09-12 | ||
| KR20070092651 | 2007-09-12 | ||
| KR10-2007-0092651 | 2007-09-12 | ||
| KR1020080047092A KR100935936B1 (en) | 2007-09-12 | 2008-05-21 | Multi-Layered Memory Apparatus |
| KR1020080047092 | 2008-05-21 | ||
| KR10-2008-0047092 | 2008-05-21 |
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| CN101388236A true CN101388236A (en) | 2009-03-18 |
| CN101388236B CN101388236B (en) | 2014-06-25 |
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| KR (1) | KR100935936B1 (en) |
| CN (1) | CN101388236B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101882620A (en) * | 2009-05-04 | 2010-11-10 | 三星电子株式会社 | Stacked memory devices |
| CN104380382A (en) * | 2012-03-26 | 2015-02-25 | 英特尔公司 | Three dimensional memory control circuitry |
| CN106782666A (en) * | 2015-11-25 | 2017-05-31 | 北京大学深圳研究生院 | A kind of three-dimensional stacked memory |
| US11968820B2 (en) | 2019-02-22 | 2024-04-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device including the semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110105255A (en) | 2010-03-18 | 2011-09-26 | 삼성전자주식회사 | Stacked memory device and method of fabricating the same |
| KR101738533B1 (en) | 2010-05-24 | 2017-05-23 | 삼성전자 주식회사 | Stacked memory devices and method of manufacturing the same |
| KR20110135299A (en) | 2010-06-10 | 2011-12-16 | 삼성전자주식회사 | Semiconductor memory device |
| KR101772117B1 (en) | 2010-09-03 | 2017-08-28 | 삼성전자 주식회사 | Semiconductor Memory Device of stacked structure having logic circuit based on resistor switch and Manufacturing method of the same |
| US10347333B2 (en) | 2017-02-16 | 2019-07-09 | Micron Technology, Inc. | Efficient utilization of memory die area |
| US9792958B1 (en) * | 2017-02-16 | 2017-10-17 | Micron Technology, Inc. | Active boundary quilt architecture memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5991224A (en) * | 1998-05-22 | 1999-11-23 | International Business Machines Corporation | Global wire management apparatus and method for a multiple-port random access memory |
| KR20010088672A (en) * | 2001-08-20 | 2001-09-28 | 심재택 | pile-up type semi-conductor structure and semi-conductor thereof |
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2008
- 2008-05-21 KR KR1020080047092A patent/KR100935936B1/en active IP Right Grant
- 2008-09-12 CN CN200810213119.1A patent/CN101388236B/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882620A (en) * | 2009-05-04 | 2010-11-10 | 三星电子株式会社 | Stacked memory devices |
| CN101882620B (en) * | 2009-05-04 | 2015-01-28 | 三星电子株式会社 | Stacked memory devices |
| CN104380382A (en) * | 2012-03-26 | 2015-02-25 | 英特尔公司 | Three dimensional memory control circuitry |
| US9620229B2 (en) | 2012-03-26 | 2017-04-11 | Intel Corporation | Three dimensional memory control circuitry |
| CN106782666A (en) * | 2015-11-25 | 2017-05-31 | 北京大学深圳研究生院 | A kind of three-dimensional stacked memory |
| CN106782666B (en) * | 2015-11-25 | 2020-05-05 | 北京大学深圳研究生院 | Three-dimensional stacked memory |
| US11968820B2 (en) | 2019-02-22 | 2024-04-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device including the semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101388236B (en) | 2014-06-25 |
| KR100935936B1 (en) | 2010-01-11 |
| KR20090027561A (en) | 2009-03-17 |
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