KR20090026679A - Method for manufacturing of phase change ram device - Google Patents

Abstract

A method for manufacturing of phase change RAM device is provided to reduce the contact resistance between PN diode and word line by connecting the PN diode and word line through a salicide layer. A method for manufacturing of phase change RAM device is comprised of the steps: forming the salicide layer(120) on the active area of a semiconductor substrate(100); forming the vertical type PN diode(130) on the active area in which the salicide layer is formed; forming a word line connected with the vertical type PN diode on the active area where the salicide layer is formed through a salicide layer; forming a first conductive type impurity region of the line type is formed within the surface of the active area before forming the salicide layer. The first conductive type impurity region is formed through an N type impurity ion injection process.

Description

Manufacturing method of phase change memory device {METHOD FOR MANUFACTURING OF PHASE CHANGE RAM DEVICE}

The present invention relates to a method of manufacturing a phase change memory device, and more particularly, to a method of manufacturing a phase change memory device that can increase the sensing margin by reducing the resistance between the vertical PN diode and the contact plug of the word line. will be.

The memory device is a volatile random access memory (RAM) device that loses input information when the power is cut off, and a read only memory (ROM) device that maintains the storage state of the input information even when the power is cut off. It is largely divided. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include flash memory devices such as EEPROM (Elecrtically Erasable and Programmable ROM). have.

However, although the DRAM is a very good memory device as is well known, high charge storage capability is required, and for this purpose, it is difficult to achieve high integration because the electrode surface area must be increased. In addition, the flash memory device requires a high operating voltage compared to a power supply voltage in connection with a structure in which two gates are stacked, so that a separate boost circuit may be used to form a voltage required for write and erase operations. There is a difficulty in high integration because it is necessary.

Accordingly, many studies have been conducted to develop a new memory device having the characteristics of the nonvolatile memory device and having a simple structure. For example, recently, a phase change RAM device has been developed. Was proposed.

In the phase change memory device, a phase change film interposed between the electrodes through a current flow between the lower electrode and the upper electrode is changed from a crystal state to an amorphous state. It is a memory element for determining information stored in a cell by using a resistance difference.

In detail, the phase change memory device uses a chalcogenide film as a phase change film. The chalcogenide film is a compound film made of germanium (Ge), stevilium (Sb) and tellurium (Te), and is amorphous by heat generated by an applied current, that is, Joule heat. A phase change occurs between the state and the crystalline state.

At this time, since the specific resistance of the phase change film having an amorphous state is higher than that of the phase change film having a crystalline state, the current flowing through the phase change film in the read mode is sensed so that the information stored in the phase change memory cell is logical '1' or It is determined whether the logic is '0'.

In particular, a method of applying a vertical PN diode has been proposed in the manufacture of a phase change memory device of 512 Mb or more. When the vertical PN diode is applied, the cell size can be reduced to 6F ² or less. The vertical PN diode is formed on a line type N-type impurity region formed in the surface of the active region, and a contact plug is formed on the N-type impurity region between the vertical PN diodes to contact an electrode electrically connected to a word line. do.

However, in the above-described prior art, the current flow between the vertical PN diodes formed in one string is about 40% or more, and thus the sensing margin of the phase change memory device is lowered.

In detail, the difference in current flow between the vertical PN diode adjacent to the contact plug electrically contacting the word line and the vertical PN diode farthest from the contact plug occurs as much as 50%. The difference in current flow between the vertical PN diodes is due to the high resistance of the N-type impurity region connecting the vertical PN diode and the contact plug.

Thus, a method of increasing the energy at the time of doping the impurity for forming the N-type impurity region in order to lower the resistance of the N-type impurity region has been proposed. In this case, damage to the portion of the active region during the impurity doping ), There is a limitation that the vertical PN diode cannot be stably formed.

The present invention provides a phase change memory device capable of reducing the resistance between a vertical PN diode and a contact plug of a word line.

In addition, the present invention provides a method of manufacturing a phase change memory device capable of increasing the sensing margin.

In a method of manufacturing a phase change memory device according to an embodiment of the present invention, in the method of manufacturing a phase change memory device for reducing resistance between a vertical PN diode and a word line, a salicide film is formed on an active region of a semiconductor substrate. Forming; Forming a vertical PN diode in contact with the salicide layer on an active region where the salicide layer is formed; And forming a word line connected to the vertical PN diode through the salicide layer on an active region where the salicide layer is formed.

Here, before forming the salicide layer, the method may further include forming a line type first conductive impurity region in the surface of the active region.

The first conductive impurity region is formed by an N-type impurity ion implantation process.

The N-type impurity ion implantation process is performed using energy of 10 to 50 keV using P or As.

The salicide film is made of Co or Ti.

The vertical PN diode and the word line are connected through a contact plug formed on the salicide layer and the salicide layer.

As described above, the present invention provides a contact plug of a vertical PN diode and a word line by connecting a contact of a vertical PN diode and a word line through an N-type impurity region and a salicide layer formed on the N-type impurity region. It can effectively reduce the resistance between, thereby increasing the sensing margin.

According to the present invention, after forming a line-type N-type impurity region in a surface of an active region of a semiconductor substrate and forming a salicide film on the N-type impurity region, a vertical PN diode is formed on the N-type impurity region where the salicide film is formed. The contact plug of the word line is formed.

This effectively reduces the resistance between the vertical PN diode and the contact plug of the word line connected through the N-type impurity region and the salicide film formed on the N-type impurity region, and thus, the phase change memory device. Can increase the sensing margin.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1A to 1H are cross-sectional views illustrating processes for manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, an isolation layer 102 defining an active region is formed in each region of the semiconductor substrate 100 partitioned into a cell region and a ferry region. In this case, the active region of the cell region is defined as a line type. Next, a gate 110 including the gate insulating film 104, the gate conductive film 106, and the gate hard mask film 108 is formed in the ferry region.

Referring to FIG. 1B, a first insulating layer 112 and a first nitride layer 114 are sequentially deposited on respective regions of the semiconductor substrate 100 including the device isolation layer 102 and the gate 110. The first insulating film 112 and the first nitride film 114 are preferably deposited such that the thickness of the films 112 and 114 is not larger than about 500 GPa.

Subsequently, after the first mask pattern 116 is formed on the first nitride layer 114 to expose the cell region, the first nitride layer 114 of the cell region exposed by the first mask pattern 116 is formed. The portion of the first insulating layer 112 is removed. Next, an impurity, for example, an N-type impurity ion implantation process is performed on the cell region to form a line-type N-type impurity region 118 on the surface of the cell region active region.

In the N-type impurity ion implantation process, P or As is performed at an energy of about 10 to 50 keV, and the N-type impurity region 118 is formed to a shallower depth than the device isolation layer 102.

Referring to FIG. 1C, the mask pattern is removed from the resultant of the semiconductor substrate 100 having the N-type impurity region 118 formed thereon, and then a first salicide layer (ie 120). The first salicide layer 120 is made of Co or Ti.

Here, in the present invention, the salicide process may be performed on the N-type impurity region 118 to form the first salicide layer 120, thereby lowering the resistance of the N-type impurity region 118. It is possible to improve the characteristics of the vertical PN diode by reducing the resistance between the subsequently formed vertical PN diode and the contact plug of the word line. In addition, by lowering the resistance of the N-type impurity region 118, the width of the programming current required for the phase change of the phase change film may be reduced, thereby increasing the sensing margin of the phase change memory device.

Referring to FIG. 1D, a second mask pattern (not shown) covering a cell region is formed on the semiconductor substrate 100 on which the first salicide layer 120 is formed, and then exposed by the second mask pattern pattern. The first insulating layer 112 and the first nitride layer 114 of the ferry region are etched to form spacers 122 on sidewalls of the gate 110.

Subsequently, after removing the second mask pattern, a second insulating layer 124 is deposited on each region of the semiconductor substrate 100 to cover the gate 110 including the spacers 112. Then, after CMP (Chemical Mechanical Polishing) of the surface of the second insulating film 124, the N-type impurity region of the cell region by etching the CMP second insulating film 124 and the first salicide film 120 118 forms a plurality of holes H exposing portions.

Referring to FIG. 1E, after the N-type silicon epitaxial layer is grown from the portion of the N-type impurity region 118 exposed on the bottom surface of the hole H, the second insulating layer 124 may be exposed on the N-type silicon epitaxial layer. Until CMP. Subsequently, a P-type impurity ion implantation process is performed on the N-type silicon epitaxial layer, and the N-type 126 and the P-region 128 are sequentially stacked on the N-type impurity region 118 in the hole H. The vertical PN diode 130 is formed.

In this case, the concentration of the P region 128 is formed to be higher than that of the N region 126, and the concentration of the N region 126 is formed to be lower than that of the N-type impurity region 118. The breakdown voltage is increased by emitting an electric field between 118 and the P region 128.

Next, a salicide process may be performed on the vertical PN diode 130 to form a second salicide layer 132 on the P region 128. The second salicide layer 132 is formed of Co, or Ti, and serves to improve ohmic characteristics between the subsequent lower electrode and the vertical PN diode 130.

Referring to FIG. 1F, after the second nitride film 134 is deposited on the second insulating film 124 including the second salicide film 132, the second nitride film 134 and the second insulating film 124 are deposited. And etching the first salicide layer 120 to form contact holes in the cell region and the ferry region, respectively.

Then, a barrier film (not shown) is formed on the surface of the contact hole, and a conductive film is deposited to fill the contact hole on the barrier film. Subsequently, the conductive film and the barrier film are CMP to form a first contact plug 136 contacting the first salicide layer 120 in the active region of the cell region, and a second contact plug 138 in the ferry region. ).

Referring to FIG. 1G, after forming the third nitride film 140 on the second nitride film 134 including the first and second contact plugs 136 and 138, the third and second nitride films 140, 134 is etched to form a contact hole exposing the second silicide layer 132. The contact hole is preferably formed in a size of about 10 ~ 100nm or less.

Then, the contact hole is filled with a conductive film for the lower electrode to form a lower electrode 142 in contact with the vertical PN diode 130. The lower electrode 142 serves as a heater to generate Joule heat by generating a current flow in a subsequently formed phase change film, and preferably forms a small contact area with the phase change film.

Referring to FIG. 1H, a phase change material and an upper electrode conductive film are sequentially deposited on the third nitride film including the lower electrode. Thereafter, the upper electrode conductive layer and the phase change material are etched to contact the vertical PN diode 130 in the cell region of the semiconductor substrate 100, and the lower electrode 142, the phase change layer 144, and the upper electrode are etched. A phase change memory cell 148 having a structure including 146 is formed.

In this case, the phase change layer 144 and the upper electrode 146 of the phase change memory cell 148 may be formed in a line type extending in a direction perpendicular to the N-type impurity region 118. In addition, the phase change layer 144 uses a material including a chalcogen element, for example, a mixture of at least one selected from Ge, Sb, and Te, or an alloy thereof.

Thereafter, although not shown, a series of subsequent known processes are sequentially performed to complete the phase change memory device according to the embodiment of the present invention.

Specifically, a word line forming a bit line in contact with the phase change memory cell 148 and then contacting the first salicide layer 120 through the first contact plug 136 on the bit line. To form.

Here, the present invention can effectively improve the characteristics of the vertical PN diode by reducing the resistance between the vertical PN diode and the contact plug of the word line by forming a salicide film on the N-type impurity region, accordingly, the phase change The sensing margin of the memory device can be increased.

On the other hand, in the above-described embodiment of the present invention, by forming a salicide film on the N-type impurity region, the resistance between the vertical PN diode and the contact plug of the word line can be reduced, but as another embodiment of the present invention, The same effect can be obtained by forming a salicide film without forming an N-type impurity region in the.

In this case, since the salicide film is formed in the active region without performing the N-type impurity ion implantation process, damage of the active region by the N-type impurity ion implantation process does not occur, and thus, vertical PN There is an advantage that the N-type silicon epitaxial layer for forming a diode can be formed more stably.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1A to 1H are cross-sectional views of processes for explaining a method of manufacturing a phase change memory device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 device isolation film

104: gate insulating film 106: gate conductive film

108: gate hard mask film 110: gate

112: first insulating film 114: first nitride film

116: first mask pattern 118: N-type impurity region

120: first salicide film 122: spacer

124: second insulating film H: hole

126: N area 128: P area

130: vertical PN diode 132: second salicide film

134: second nitride film 136: first contact plug

138: second contact plug 140: third nitride film

142: lower electrode 144: phase change film

146: upper electrode 148: phase change memory cell

Claims (6)

Forming a salicide film on an active region of the semiconductor substrate; Forming a vertical PN diode in contact with the salicide layer on an active region where the salicide layer is formed; And Forming a word line connected to the vertical PN diode through the salicide layer on an active region where the salicide layer is formed; Method of manufacturing a phase change memory device comprising a. The method of claim 1, Before forming the salicide layer, Forming a line type first conductive impurity region in the surface of the active region; The method of manufacturing a phase change memory device, characterized in that it further comprises. The method of claim 2, And the first conductive impurity region is formed by an N-type impurity ion implantation process. The method of claim 3, wherein The N-type impurity ion implantation process is a method of manufacturing a phase change memory device, characterized in that performed using an energy of 10-50 keV using P, or As. The method of claim 1, And the salicide film is formed of Co or Ti. The method of claim 1, And the vertical PN diode and the word line are connected through a contact plug formed on the salicide layer and the salicide layer.

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