KR101085520B1 - Memory device and method of manufacturing the same - Google Patents

Abstract

The present invention discloses a memory device and a method of manufacturing the same. The present invention discloses a conductive region; A BPSG film formed over the conductive region and having a hole exposing a surface portion of the conductive region; And a conductive pattern formed in the hole in the hole and made of polysilicon having a grain boundary in a vertical direction.

Description

Memory device and method of manufacturing the same

The present invention relates to a memory device and a method of manufacturing the same, and more particularly, to a memory device capable of forming a stable vertical PN diode and a method of manufacturing the same.

In general, a memory device is classified into a volatile RAM device that loses input information when a power supply is cut off, and a nonvolatile ROM device that maintains input data storage even when a power supply is cut off. do. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include a flash memory such as EEPROM.

However, the DRAM has a higher charge storage capacity is required, for this purpose, it is difficult to high integration because the electrode surface area must be increased. In addition, the flash memory requires a higher operating voltage than a power supply voltage in connection with a structure in which two gates are stacked, and thus requires a separate boost circuit to form a voltage required for write and erase operations. Therefore, there is a difficulty in high integration.

In recent years, since the structure is simple and there is no interference problem between adjacent cells, high integration is possible, and phase change RAM (PCRAM) having a fast read speed of several tens of milliseconds and a relatively fast write speed of tens to hundreds of milliseconds is used. Research is actively being conducted.

In general, a phase change memory device employs an NMOS transistor, a bipolar junction transistor, and a vertical PN diode structure.

Among them, the vertical PN diode has a higher current flow compared to the transistor, which not only reduces the programming current but also reduces the cell size, which is advantageously applied to high integration of the phase change memory device.

Hereinafter, a method of forming a vertical PN diode according to the prior art will be briefly described with reference to FIGS. 1A and 1B.

Referring to FIG. 1A, after a plurality of gates 110 and spacers 120 are formed in the peripheral region of the silicon substrate 100 including the cell region and the peripheral region, a gate having the spacer 120 may be formed. The BPSG film 130 is formed of an insulating material on the entire surface of the silicon substrate to insulate the 110 from each other. The BPSG film 130 is a material having a reflow characteristic, and is a material that can be buried without a void phenomenon because of excellent gap-fill characteristics even in a narrow space.

Then, a portion of the BPSG film 130 in the cell region, preferably, a portion of the BPSG film 130 where a subsequent switching element is to be formed is etched to form a hole for exposing the surface portion of the silicon substrate 100. .

Referring to FIG. 1B, the silicon substrate 100 on which the hole is formed is subjected to a selective epitaxial growth (SEG) process at a high temperature of 900 ° C. or higher to form a polycrystalline silicon film in the hole. P-type impurity ion implantation is performed on the film, thereby forming a vertical PN diode 150 as a switching element in the hole of the cell region.

Meanwhile, as described above, in the conventional phase change memory device, the BPSG film 131 is used as a material that insulates the vertical PN diode 150 formed in the cell region and the gates 120 formed in the peripheral region.

The reason for this is that as the cell size of the phase change memory device is 90 nm or less, a material having excellent gap-fill characteristics is required as a material that insulates the gates between the gates in the surrounding area, and thus, high density plasma A BPSG film having a capability of suppressing void generation even in a narrow space is used rather than an HDP) insulating film.

However, as described above, when the BPSG film having excellent gap-fill characteristics is used as an insulating film to insulate the gates, the void phenomenon can be prevented in the surrounding area, but in the cell area, the vertical vertical PN is stable due to the BPSG film. Difficulty in securing a diode.

The reason is that when forming a vertical PN diode in the cell region, a high temperature SEG process of 900 ° C. or more is involved. In this case, a reflow phenomenon occurs in the BPSG film part due to high temperature heat during the SEG process. As a result, the profile of the hole in which the vertical PN diode is formed is modified.

That is, during the SEG process, the high temperature heat causes the BPSG film to flow down, and thus the hole portion does not have a stable vertical profile, and as a result, the PN diode having a stable vertical profile in the deformed hole cannot be formed. .

It is an object of the present invention to provide a memory device and a method of manufacturing the same, which can form a PN diode having a stable vertical profile.

The present invention provides a conductive region; A BPSG film formed over the conductive region and having a hole exposing a surface portion of the conductive region; And a conductive pattern formed in the hole in the hole and made of polysilicon having a grain boundary in a vertical direction.

Here, the conductive region is characterized in that the silicon substrate.

The conductive pattern is characterized in that the vertical PN diode.

The present invention also provides a memory device including a switching device, wherein the switching device is a vertical PN diode composed of polysilicon having grain boundaries in the vertical direction.

In addition, the present invention provides a method for manufacturing a memory device comprising the step of forming a switching element, wherein the step of forming the switching element, by growing a polysilicon in the hole of the insulating film to form a polysilicon film having a grain boundary in the vertical direction step; And performing impurity ion implantation on a surface of the polysilicon film.

Here, the switching device is characterized in that the vertical PN diode.

The insulating film is characterized in that the BPSG film.

The polysilicon film is formed at a low temperature of 500 to 600 ℃.

In addition, the present invention comprises the steps of forming an insulating film on a silicon substrate having an N-type impurity region; Etching the insulating film to form a hole exposing an N-type impurity region portion of the silicon substrate; Forming a polysilicon film having grain boundaries in a vertical direction in the hole; And performing impurity ion implantation on a surface portion of the polysilicon film to form a vertical PN diode which is a switching element in the hole.

The insulating film may be formed of a BPSG film.

The polysilicon film is characterized by growing at a low temperature of 500 ~ 600 ℃.

Moreover, the present invention includes a cell region and a peripheral region, comprising: forming a plurality of gates over the peripheral region of the silicon substrate; Forming an insulating film on an entire surface of the silicon substrate so as to cover the gates; Etching a portion of the insulating layer in the cell region to form a plurality of holes exposing an upper portion of the silicon substrate; Forming a polysilicon film having grain boundaries in a vertical direction in the hole; And performing impurity ion implantation on a surface portion of the polysilicon film to form a vertical PN diode which is a switching element in the hole.

The insulating film may be formed of a BPSG film.

The polysilicon film is characterized by growing at a low temperature of 500 ~ 600 ℃.

The present invention can suppress a reflow phenomenon of a BPSG film used as an insulating material by applying a polysilicon structure having a vertical grain boundary to a vertical PN diode as a switching element.

Therefore, the present invention can form a vertical PN diode having a stable vertical profile due to suppression of reflow of the BPSG film, and therefore, it is expected to improve the characteristics of the diode.

The present invention includes a vertical PN diode which is a conductive pattern contacting a silicon substrate which is a conductive region, and a BPSG film for insulating the vertical PN diodes from each other. The vertical PN diode is made of polysilicon having a grain boundary in the vertical direction. Preferably, the vertical PN diode is made of N-type polysilicon at the bottom and P-type polysilicon at the top. It is composed of polysilicon having grain boundaries in the vertical direction.

FIG. 2 is a cross-sectional view of a memory device according to the present invention. As illustrated, a vertical PN diode 250 including polysilicon having a grain boundary 241 in a vertical direction in a hole formed in a portion of a silicon substrate 200 which is a conductive region is illustrated. ) You can see the formation.

As such, according to the present invention, the vertical PN diode 250 may be formed of polysilicon having the grain boundaries 241 in the vertical direction, thereby forming a vertical PN diode having a stable vertical profile in the hole.

Preferably, the present invention has a grain boundary in the vertical direction in order to form a vertical PN diode used as an on-off switching device of the memory device in the form of a stable vertical profile in a memory device to which the switching device is applied. It is formed of polysilicon.

More preferably, the present invention provides a method of forming a vertical PN diode in a stable vertical profile in a memory device that applies a BPSG film with an insulating material that insulates the gates of a peripheral region and a vertical PN diode that is a cell region. To form polysilicon having grain boundaries in the vertical direction.

Specifically, a method of forming a vertical PN diode as the switching device will be briefly described as follows.

A polysilicon film having a grain boundary in the vertical direction in the insulating film to be formed is grown at a low temperature of 500 to 600 ° C. to form a polysilicon film, and impurities are formed on the surface of the polysilicon film having the grain boundary in the vertical direction. Ion implantation is performed, thereby forming a vertical PN diode which is a switching element applied to the memory element.

As described above, according to the present invention, since the vertical PN diode is formed by a low temperature polysilicon growth process, it is possible to suppress the reflow phenomenon of the BPSG film by the low temperature process, and thus, a vertical type having a stable vertical profile. PN diodes can be formed.

Specifically, the vertical PN diode according to the conventional process includes a high temperature SEG process. However, such a high temperature SEG process causes the vertical profile of the hole to deform into an unstable state while causing a reflow phenomenon of the BPSG film, which is the insulating film. If a vertical PN diode is formed in a hole deformed into an unstable state, since the vertical PN diode is formed in the hole of the unstable state, the vertical PN diode is also formed into a vertical profile of the unstable state.

Accordingly, in the present invention, the vertical PN diode is formed using a low temperature polysilicon growth process rather than a high temperature SEG process. On the other hand, the application of the polysilicon grown by the low temperature to the vertical PN diode may have a lower charge mobility than when applying the silicon formed by the SEG process to the vertical PN diode, Since the growth of the polysilicon is formed in a form having a grain boundary in the vertical direction, there is no need to worry about disturbance of the charge transfer path and charge dispersion by the grain boundary in the vertical direction.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3A to 3E are cross-sectional views illustrating processes of manufacturing a memory device according to an exemplary embodiment of the present invention. Preferably, each process for explaining a method of manufacturing a phase change memory device among manufacturing methods of a memory device is described. As a cross-sectional view, it will be described with reference to the following.

Referring to FIG. 3A, after forming a device isolation layer 201 insulating active regions in a peripheral region of a silicon substrate 200 including a cell region and a peripheral region, an insulating layer is formed on the peripheral region of the silicon substrate 200. After forming a plurality of gates 210 including a stacked layer of a conductive film and a hard mask film, spacers 220 are formed on both sidewalls of the gates 210.

Then, an N-type impurity region 202 is formed in the silicon substrate 200 in the cell region through an ion implantation process. The N-type impurity region 202 is in contact with a subsequent switching element and serves to flow a current to a word line.

Referring to FIG. 3B, a BPSG film 231 is deposited as a first insulating film on the entire surface of the silicon substrate to cover the gates 210. The BPSG film 231 is a material having a reflow characteristic and has excellent gap-fill characteristics. Thus, voids do not occur in the space between the gates 210 when the BPSG film 231 is deposited.

Then, the BPSG film 231 is planarized by performing a chemical mechanical polishing (CMP) process on the BPSG film 231 until the upper end of the gate 210 is exposed.

Referring to FIG. 3C, after a mask pattern (not shown) is formed on the planarized BPSG film 231 to expose a portion where a subsequent switching element is to be formed, the BPSG of the cell region exposed by the mask pattern. A portion of the film 231 is etched to form a plurality of holes H exposing the surface portion of the silicon substrate.

 Then, the mask pattern was removed according to a known process, and then polysilicon was grown at a low temperature of 600 ° C. or lower with respect to the silicon substrate on which the hole H was formed, so that the vertical profile poly was formed in the hole H of the cell region. The silicon film 240 is formed. Preferably, polysilicon having a grain boundary 242 in the vertical direction is grown at a low temperature of 500 to 600 ° C. to form an N-type polysilicon film 240 in the hole.

In the polysilicon film 240 is formed by growing polysilicon having a grain boundary in the vertical direction, a crystal seed, such as Fe, is grown in dots, and then polysilicon is grown to increase surface energy. energy) grows in a low direction and allows columnar growth over the seed. The process is possible at a low temperature of 600 ° C or lower.

In the present invention, since the process of forming the polysilicon film may be performed at a low temperature of 600 ° C. or less, a reflow phenomenon of the BPSG film 231 does not occur during the process of forming the polysilicon film 240.

The reason is that the BPSG film 231 is weak in high temperature heat and has a disadvantage in that reflow occurs. However, in the present invention, the polysilicon film forming process, which is a process of forming a subsequent vertical PN diode, is performed at 600 ° C. or less. Since it proceeds at a low temperature, the reflow phenomenon of the BPSG film can be prevented.

In addition, since the polysilicon film is formed through the growth of polysilicon having a grain boundary in the vertical direction, the charge transfer path disturbance and the charge dispersion do not need to be more concerned than in the conventional polycrystalline silicon film.

Referring to FIG. 3D, P-type impurity ion implantation is performed on the silicon substrate on which the polysilicon film 240 is formed to form an upper surface of the polysilicon film as a P-type polysilicon film, thereby forming a vertical type in the hole. PN diode 250 is formed.

Referring to FIG. 3E, after forming the second insulating layer 232 on the BPSG layer 231 including the vertical PN diode 250, the second insulating layer 232 is etched to form the vertical PN diode ( 250) form a contact hole exposing the portion.

Then, the heater material is buried in the contact hole to form the heater 260 in contact with the vertical PN diode 250. The heater 260 is in contact with a subsequent phase change film, and serves to release heat generated during phase change.

Next, the phase change film 270 and the upper electrode thin film are sequentially deposited on the second insulating film 232. The phase change layer 270 uses a chalcogenide material. Subsequently, the upper electrode thin film and the phase change layer 270 are etched to form a stacked pattern of the phase change layer 270 and the upper electrode 280 in contact with the heater 260.

Subsequently, although not shown, a subsequent known series of subsequent processes are sequentially performed to manufacture a phase change memory device according to an embodiment of the present invention.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1A and 1B are cross-sectional views for each process for explaining a method of manufacturing a phase change memory device according to the prior art.

2 is a cross-sectional view illustrating a memory device according to the present invention.

3A to 3E are cross-sectional views of processes for explaining a method of manufacturing a phase change memory device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200: silicon substrate 201: device isolation film

202: N-type impurity region 210: gate

220: spacer 231; BPSG film

232: second insulating film 240: polysilicon film

241: grain boundary in the vertical direction 250: vertical PN diode

260: heater 270: phase change film

280: upper electrode

Claims (14)

delete delete delete delete In the method of manufacturing a memory device comprising the step of forming a switching device, Forming the switching element, Growing polysilicon in the holes of the insulating film to form a polysilicon film having grain boundaries in the vertical direction; And Performing impurity ion implantation on a surface of the polysilicon film; Including, Wherein said polysilicon film is formed at a low temperature of 500 to 600 占 폚. Claim 6 was abandoned when the registration fee was paid. The method of claim 5, The switching device is a manufacturing method of a memory device, characterized in that the vertical PN diode. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 5, The insulating film is a manufacturing method of a memory device, characterized in that the BPSG film. delete Forming an insulating film on the silicon substrate having the N-type impurity region; Etching the insulating film to form a hole exposing an N-type impurity region portion of the silicon substrate; Forming a polysilicon film having grain boundaries in a vertical direction in the hole; And Performing impurity ion implantation on a surface portion of the polysilicon film to form a vertical PN diode as a switching element in the hole; Including, The polysilicon film is formed at a low temperature of 500 to 600 ℃ Method of manufacturing a memory device, characterized in that. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 9, And the insulating film is formed of a BPSG film. delete delete delete delete

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