KR20090022209A - System-on-chip having ieee 1500 wrapper and internal delay test method thereof - Google Patents

Abstract

A system-on-chip having IEEE 1500 wrapper and an internal delay test method thereof are provided to reduce the number of test pins by using a TAP controller. An IEEE 1500 wrapped core(230) comprises a core(2390) having a scan-chain(2391). The IEEE 1500 wrapper(2310~2380) provides an interface between a TAP controller and the core. A wrapper instruction register(2310) determines the action mode corresponding to the wrapper control signal(WSC) set. A wrapper bypass register(2320) is selectively operated by the wrapper instruction register. A WSC-WBC decoder(2330) converts the wrapper control signal into the test control signal for performing the test operation according to the invention. A multiplexer controller(2340) produces control signals controlling input-output wrapper border cells. A boundary test clock generator(2350) produces the input-output clock of wrapper border cells. A scan test clock generator(2360) produces the core scan-chain test clock(STCLK).

Description

System-on-chip with IEEE 1500 wrapper and its internal delay test method {SYSTEM-ON-CHIP HAVING IEEE 1500 WRAPPER AND INTERNAL Delay Test Method]

TECHNICAL FIELD The present invention relates to integrated circuits, and more particularly, to an SoC having an IEEE 1500 wrapper and an internal delay test method thereof.

Various digital information devices, such as mobile phones, PDAs, digital TVs, and smart phones, require many semiconductor chips such as microprocessors, networking chips, and memories in order to implement Internet access and computing functions smoothly. In addition, with the trend of increasingly complex diversification, convergence between components of information equipment is expected to be further developed. Therefore, more semiconductor chips will be needed in information equipment.

In this way, by integrating various components into one semiconductor chip, System on Chip (SoC) technology has emerged as a technology for one-chip not only semiconductor but also individual components in the future. SoCs integrate microprocessors, digital signal processors (DSPs), memory, and baseband chips into a single chip, allowing the chip to function as a system. For example, Intel's recently announced GSM / GPRS integrated chip solution combines a baseband chip, a DSP, a microprocessor to drive applications, and flash memory. The integrated chip solution offers features such as reduced cost, reduced size and extended battery life compared to the configuration of individual chips. Because of these advantages, SoC is expected to expand further in not only mobile phones but also digital devices such as PDAs, portable media terminals, and home network servers.

SoCs, which are expected to have significant ripple effects not only in the semiconductor industry but also throughout the IT industry, are breaking down the existing realm between chip manufacturers by consolidating the memory and non-memory required for system configuration into one. Therefore, competition in the SoC field will be more intense. In particular, for SoC development, it is essential to secure nanometer deep-submicron (DSM) circuit process technology. Therefore, large-scale investment and technology development capability are required, and the investment in SoC design field, which is focused on securing IP (Intellectual Property (hereinafter referred to as IP)) and software development, away from conventional semiconductor manufacturing process-oriented production methods It is expected to be.

While advances in semiconductor process technology have made it possible to produce high-quality IP, testing of these IPs within SoCs is increasingly time consuming. As a result, expensive test costs are incurred. This is because, due to the ultra-fine process, problems such as noise, signal delay, and interference become more important, existing failure models and associated test pattern generation tools are not suitable. In addition, poor communication of information for testing between IP providers and the IP user layer, derived from IP-based design trends, makes SoC difficult to test. In addition, the difficulty in testing the SoC is that it is not easy to obtain a contact point necessary for testing the input and output of the chip to the input and output of the core. If several cores are embedded in a chip, it is impossible to assign a test pin to each core. Therefore, the control and observation necessary for the test on cores present in each part of the chip with a minimum number of pins can be effectively made.

In the manufacturing process of the SoC, the actual test process takes place once after all systems have been configured. The core, a separate block of the SoC, is designed by the core provider and provided to the core user. Importantly, the core provided at this time is still in the technical stage and is not manufactured or tested. Therefore, when testing a system in an SoC, not only core interoperability but also internal core testing are important. Therefore, since the test vector required for testing the inside of the core is larger than the test vector required for testing the interconnects, a mechanism for applying an effective test vector in consideration of test time is required. SoC's testing also has the test challenges of traditional deep-submicron chips, such as failure detection rates, test costs and time-to-market.

Testing SoCs requires a unique test structure when compared to IEEE 1149.1 (JTEG). This is a characteristic of SoC, such as the limitation of the number of pins that cannot prepare input / output for test purpose for all cores embedded in SoC, and the limitation of core access that cannot directly access the input / output of all cores from the input / output of chip. Caused by. Test pattern source produces test vectors for embedded cores. In contrast, a test pattern sink compares test results with expected results. The test pattern source and sink can be implemented by an external Automatic Test Equipment (ATE), an on-chip built-in self test device (BIST), or a combination of the two. Can be. The choice of whether the source and sink are implemented on-chip, off-chip, or a mixture of the two is determined by considering the circuit characteristics of the core, the shape of the predefined test vector, and the test cost.

The basic structure for SoC testing is based on IEEE 1500. IEEE 1500 is described in Proceeding of 17th VLSI TEST Syposium, pp. 483-388, 1999, entitled "Preliminary Outline of the P1500 Scalable Architecture for Testing Embedded Cores", incorporated herein by reference. IEEE 1500 was proposed to perform functions similar to IEEE 1149.1 at the SoC level. To perform tests based on this standardization, the SoC needs a core test wrapper and a test access mechanism (TAM). The core test wrapper acts as an interface between the core inside the SoC and the TAM. The TAM takes test data from the outside of the chip and delivers it to the core test wrapper. Here, the core test wrapper is standardized, while the TAM is not yet standardized and is defined by the user.

FIG. 1 is a block diagram briefly illustrating an IEEE 1500 wrapper configuration for a core including two scan chains (Scan chain0, Scan chain1). Referring to FIG. 1, the IEEE 1500 wrapped core 100 has a structure similar to that of IEEE 1149.1. The IEEE 1500 wrapped core 100 consists of a core 130 including a scan chain and a wrapper around the core.

Core 130 with IEEE 1500 wrapper support includes two scan chains 131, 132. Each scan chain tests the internal operation of the core 130. SI [0] and SI [1] indicate an input port of a test pattern for scanning inside the core. Each of SO [0] and SO [1] represents an output port of each of the scan chains 131 and 132. For internal testing of the core, test data is input and output in series through the scan input / output pods SI [0], SI [1], SO [0], and SO [1]. The scan chain is controlled by the scan enable signal se and the clock clk. If the length of a scan chain is too long, it is obvious to those who have gained common knowledge in this field that test time can be saved by dividing the data into several scan chains and processing the data in parallel.

The IEEE 1500 wrapper consists of a wrapper instruction register (110, WIR), a wrapper bypass register (120, WBY), and a wrapper boundary register (WBR). have. The wrapper boundary register (WBR) may be divided into an input wrapper boundary register (140, IWBR) and an output wrapper boundary register (150, OWBR). The wrapper command register 110 decodes instructions provided from the outside (eg, WS_BYPASS, W [S, P] _EXTEST, W [S, P] _INTEST, etc.) to control an operation mode of all the registers of the wrapper. The wrapper is controlled by the test control signal WSC provided by the test access mechanism TAM.

However, the access mechanism by the wrapped serial port (WSP) is not defined in the IEEE 1500 specification. Accordingly, there is an urgent need for a test connection mechanism or test connection device (TAM) that can effectively perform tests in SoC systems composed of IP cores with IEEE 1500 wrappers.

The present invention provides an internal delay test apparatus and test method for IP cores having an IEEE 1500 wrapper through an IEEE 1149.1 TAP controller.

A system-on-chip tested according to a wrapper control signal (WSC) generated from a TAP controller of the IEEE 1149.1 standard for achieving the above object comprises: a core clock generation circuit providing one or more core driving clocks; An internal delay failure test operation including one or more IP cores of an IEEE 1500 standard having an input boundary register, an output boundary register and a scan chain for performing a test operation in response to the wrapper control signal (WSC) and the core drive clock. In response, the IP core controls an input boundary register, the scan chain, and an output boundary register to be connected in series in response to the wrapper control signal WSC and the core driving clock, and generates the clock gating method using the scan chain. A wrapper control block for providing an at-speed test clock.

The wrapper control block may include: a wrapper instruction register configured to generate an internal delay failure test signal WS_DELAYINTEST_SCAN and a test mode signal MODE and IO_FACE in response to the wrapper control signal WSC; The test clock WRCK included in the wrapper control signal WSC is converted into a first test clock GWRCK deactivated during an internal delay failure test operation, and the shift command ShftDR is updated from the wrapper control signal WSC. A decoder for generating an instruction UpDR and a capture instruction CapDR; A multiplexer controller configured to configure a serial connection by controlling multiplexers included in each of the input and output wrapper boundary registers and the scan chain in response to the test mode signal MODE, IO_FACE and a shift instruction (ShftDR); A boundary test clock generator providing the first test clock GWRCK as a driving clock of the input and output boundary registers with reference to the capture command CapDR and the update command UpDR; And a scan test clock generator for providing two consecutive pulses of the core driving clock to the at-speed test clock during an internal delay failure test.

In this embodiment, the at-speed test clock includes a launch pulse and a capture pulse provided to the scan chain.

In this embodiment, the boundary cells included in the input boundary register and the output boundary register do not include an update register.

In this embodiment, the boundary test clock generator provides an output boundary register clock for the output boundary register to perform a capture operation in response to the update command UpDR.

In this embodiment, the scan test clock generator detects the state of the update command UpDR according to the state of the capture command CapDR and the update command UpDR to generate a launch-capture clock LCCLK. A launch-capture clock generator; A calculation circuit configured to generate a clock signal DTCLK by performing an OR operation on the launch-capture clock LCCLK and the clock SftCLK provided to the input boundary register; And a selection circuit configured to provide the clock signal DTCKL to the at-speed test clock STCLK in response to the internal delay failure test command WS_DELAYINTEST_SCAN.

In this embodiment, the launch-capture clock generator is driven by the core drive clock.

In this embodiment, the launch-capture clock generator comprises: a state machine that generates an enable signal when the update command UpDR transitions to a high level while the capture command CapDR is at a low level; And a clock gating cell configured to pass only a core driving clock corresponding to a pulse period of the enable signal delayed for a predetermined time.

In this embodiment, the clock gating cell comprises: a latch circuit for latching the enable signal in synchronization with the falling edge of the core clock; And an AND operation circuit configured to perform an AND operation on the output of the latch circuit and the core driving clock to provide the launch-capture logic.

In this embodiment, the core clock generation circuit is composed of a phase locked loop circuit.

In this embodiment, the core clock generation circuit provides core driving clocks corresponding to the driving frequency of each of the plurality of IP cores.

A method for performing an internal delay failure test for an IP core of a system-on-chip having a wrapper of IEEE 1500 standard for achieving the above object is performed in a wrapper command register (WIR) through a TAP controller of IEEE 1149.1 standard. Providing a delay failure test command and providing a core drive clock via the PLL; Controlling multiplexers included in each of the input boundary register, the scan chain and the output boundary registers so that the input boundary register, the scan chain, and the output boundary registers included in the IP core are connected in series according to the internal delay failure test command. Signal (SC = se, WCI, WCO), a clock-gated launch-capture clock (LCCLK) that supports launch-capture operation of the scan chain, and clock signals (IWRTCLK) to be provided to the input and output boundary registers. OWRTCLK); And providing the control signal (SC = se, WCI, WCO) and the clock signals (IWRTCLK, OWRTCLK) to the input boundary register and the output boundary register and the launch-capture clock to the scan chain. Receiving a test result captured from.

In this embodiment, the wrapper command register WIR further generates a control signal WS_DELAYINTEST_SCAN corresponding to the internal delay failure test command.

In this embodiment, the wrapper boundary cells included in the input and output boundary registers do not have an update register.

In this embodiment, the launch-capture clock LCCK is provided to the scan chain when the update instruction UpDR is activated with the capture instruction CapDR deactivated in the wrapper instruction register WIR.

In this embodiment, the clock signal OWRTCLK is activated such that the output wrapper boundary register performs a capture operation upon activation of the updater command UpDR.

The present invention proposes a method for reducing SoC test costs by using a low cost ATE. Test cores are controlled by controlling the IEEE 1500 wrapper through the TAP controller, reducing test pin counts, and eliminating the need for additional TAMs by utilizing the TAP controller.

In addition, the at-speed launch-capture clock generator is synchronized with the operation clock of each core, so that a delay failure test of cores using different clocks can be simultaneously performed.

In addition, it takes a relatively long time to test a single SoC because all the I / O and scan chains in the SoC are organized in one path, but test time by testing multiple SoCs simultaneously through multi-site testing. Can be shortened. This can save test costs with expensive test equipment.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and that additional explanations of the claimed invention are provided. Reference numerals are shown in detail in preferred embodiments of the invention, examples of which are shown in the reference figures. In any case, like reference numerals are used in the description and the drawings to refer to the same or like parts. In the following, IEEE 1149.1 is used as an example of the SoC's TAP scheme to explain the features and functions of the present invention. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a block diagram schematically illustrating a structure of a test access device (TAM) of the SoC 200 according to the present invention. 2, the SoC 200 includes IEEE 1500 wrapped cores 230, 240, a TAP controller 210, glue logic 220, and a PLL 250. SoC 200 of the present invention including such a configuration can control the inner wrapper through a minimum number of pins and can perform a low cost test.

As is well known, the TAP controller 210 is the interface used to test the IEEE 1149.1 core. A detailed description of the TAP controller 210 is described in IEEE Standard 1149.1-1990 entitled "IEEE Standard Test Access Port and Boundary-Scan Architecture" (IEEE, June 1989), which application is incorporated by reference. The TAP controller 210 has five external sources: Test Clock Input (TCK), Test Mode Select (TMS), Test Data Input (TDI), Test Data Output (TDO), and Test Reset (TRST) for test reset. The terminal is basically included. Through these five terminals, the TAP controller 210 can input and observe the test pattern by dedicated boundary registers (WBRs) inside the chip. Here, the TAP controller 210 decodes the signals provided from the terminals described above and stores them in internal registers (not shown). According to the values set in the internal registers, the TAP controller 210 operates as a state machine having a specific state and sequentially controls the test operation.

The glue logic 220 converts the control signals provided from the TAP controller 210 into a portion of the wrapper control signal WSC provided to the IEEE 1500 core of the present invention. The glue logic 220 reproduces the IEEE 1149.1 instructions into control signals (ShiftWR, CaptureWR, UpdateWR) provided to the IEEE 1500 wrapped core according to the present invention.

The IEEE 1500 wrapped cores 230, 240 are cores with the IEEE 1500 wrapper proposed to test various embedded cores. The IEEE 1500 wrapped cores 230, 240 of the present invention are controlled by the TAP controller 210 during a test operation. The test operation is performed by the wrapper control signal WSC provided from the TAP controller 210 and the glue logic 220 and the core driving clocks CoreCLKA and CoreCLKB provided from the PLL 250. The configuration of each of the IEEE 1500 wrapped cores 230 and 240 will be described in detail later with reference to FIG. 4.

Phase locked loop 250 (hereinafter referred to as PLL) is a clock generation circuit for providing core drive clocks to each of the cores operating at different frequencies. The core driving clock provided by the PLL 250 may simultaneously perform delay failure test on cores having core clocks of different frequencies.

Through the configuration described above, the IEEE 1500 wrapped cores can be accessed by the IEEE 1149.1 TAP controller 210. Thus, low cost test equipment can be used to test cores with multiple IEEE 1500 wrappers without additional pin configuration.

3A is a circuit diagram briefly illustrating a configuration of the glue logic 220 of FIG. 2. Referring to FIG. 3A, the glue logic 220 generates ShiftWR, CaptureWR, and UpdateWR which are part of the wrapper control signal WSC according to the register values of the TAP controller 210. The wrapper shift signal ShiftWR is activated in synchronization with the rising edge of the test clock TCK in any one of the registers (Shift-IR Register and Shift-DR Register) of the TAP controller 210. That is, the logical sum of the register state values (Shift-IR, Shift-DR) input to the OR gate 221 is transferred to the flip-flop 224 in synchronization with the rising edge of the test clock and consequently the wrapper. The shift signal ShiftWR is output. The wrapper capture signal CaptureWR is activated in synchronization with the activation of any one of the registers (Capture-IR Register, Capture-DR Register) of the TAP controller 210 and the rising edge of the test clock TCK. The wrapper update signal UpdateWR is activated when any one of the registers (Update-IR Register, Update-DR Register) of the TAP controller 210 is activated. Accordingly, the wrapper update signal UpdateWR is generated without the insertion of the flip-flop FF driven by the test clock TCK.

3B is a timing diagram that briefly illustrates the operation of TAP controller 210 and glue logic 220 in accordance with the present invention. Referring to Figure 3b, the access mechanism of the IEEE 1500 wrapper is as follows. The wrapper clock signal WRCK is directly connected to the test clock TCK. The wrapper command select signal (SelectWIR) is directly connected to the select signal (Select) of the TAP controller 210, and by this value, the wrapper command register (WIR, SelectWIR = '1') or the wrapper boundary register (WBR, SelectWIR = '). 0 ') is selected. Accordingly, while the wrapper capture signal CaptureWR and the wrapper shift signal ShiftWR are kept at '1', capture and shift operations are performed on the rising edge of the wrapper clock signal WRCK. While the wrapper update signal UpdateWR is '1', an update operation will be performed on the falling edge of the wrapper clock signal WRCK.

The mechanism for selecting a core to be tested in the SoC and establishing and releasing the test data path by the TAP controller 210 and the glue logic 220 according to the present invention is simply implemented using an IEEE 1149.1 instruction decoder. Can be.

4 is a block diagram showing a core 230 having a wrapper of the IEEE 1500 standard according to the present invention shown in FIG. Referring to Figure 4, IEEE 1500 wrapped core 230 in accordance with the present invention includes a core 2390 having a scan chain 2391. And an IEEE 1500 wrapper 2310-2380 providing an interface between the core 2390 and the TAP controller 210 (see FIG. 2). According to the wrapper configuration according to the present invention, the IEEE 1500 wrapped core 230 includes a wrapper control signal (WSC) provided from the TAP controller 210 (see FIG. 2) having the IEEE 1149.1 standard and a core clock signal provided from the PLL 250. (CoreCLKA) is provided. In response to each signal, an internal test by an edge test or a scan chain and an internal delay failure test may be performed.

The wrapper instruction register 2310 determines an operation mode corresponding to the set of wrapper control signals WSC. The test mode performed in the IEEE 1500 wrapped core 230 is determined according to the wrapper control signal WSC shifted in the wrapper instruction register 2310. The wrapper bypass register 2320 is a register circuit that selectively operates by the wrapper instruction register 2310. When the bypass command WS_BYPASS is input, the wrapper command register 2310 stores the serial test input signal WSI and provides it directly as a serial test output signal WSO.

The WSC-WBC decoder 2330 converts the wrapper control signal WSC into a test control signal WBC for performing a test operation according to the present invention. That is, the WSC-WBC decoder 2330 reconstructs the wrapper control signal WSC into a control signal suitable for the wrapper boundary cell structure according to the present invention. Each of the wrapper boundary cells WBC of the wrapper boundary registers 2370 and 2380 according to the present invention does not include an update register. That is, the boundary cell of the present invention can perform a shift and capture operation using only one register. Therefore, a decoding process of a control signal for supporting a wrapper boundary register composed of such boundary cells is required, and the WSC-WBC decoder 2330 plays this role.

The multiplexer controller 2340 generates control signals SC, WCI, and WCO that control the input / output wrapper boundary cells WBC. The multiplexer controller 2340 controls the control signals SC, WCI, and WCO in response to the control signal ShiftDR from the wrapper instruction register 2310 and the mode signal MODE and control signal IO_FACE from the wrapper instruction register 2310. ) The configuration of the multiplexer controller 2340 will be described in detail later with reference to FIG. 6. The wrapper control signals SC, WCI, and WCO will be implemented as shown in Table 1 and Table 2 below. SC should be '1' when shifting and '0' when capturing. WCI and WCO should remain opposite to each other depending on the test mode.

Operation selection signal (SC) of the wrapper boundary cell Mode SC Test mode Shift operation One Capture Operation 0 Normal Mode X

Control signal of the wrapper boundary cell (WCI, WCO) Mode WCI WCO Test mode Internal test One 0 External test 0 One Bypass X X Normal Mode 0 0

The boundary test clock generator 2350 inputs and outputs the wrapper boundary cells according to control signals CapDR and UpDR transmitted from the WSC-WBC decoder 2230 and an internal delay failure test signal WS_DELAYINTEST_SCAN from the wrapper command register 2310. Generate a clock. The boundary test clock generator 2350 generates a clock signal SftCLK such that the boundary cells perform a shift operation during the internal delay failure test operation.

The scan test clock generator 2360 scans the core 2390 according to the control signals CapDR and UpDR transmitted from the WSC-WBC decoder 2230 and the internal delay failure test signal WS_DELAYINTEST_SCAN from the wrapper command register 2310. Generate a chain test clock (STCLK). The scan chain 2391 inside the core is driven by the scan chain test clock STCLK.

The input / output boundary registers 2370 and 2380 are driven in response to the wrapper control signals SC, WCI and WCO from the multiplexer controller 2340 and the clock signals IWRTCLK and OWRTCLK from the boundary test clock generator 2350. do. That is, the input boundary register 2370 includes a plurality of wrapper boundary cells (WBC). The boundary cells included in the input boundary register 2370 input or shift the test signal in response to the input control signal WCI and the operation selection signal SC provided from the multiplexer controller 2340. The boundary cells included in the output boundary register 2380 output or shift a test result in response to the output control signal WC0 and the operation selection signal SC provided from the multiplexer controller 2340.

Core 2390 is a collection of functional circuits that includes scan chain 2391. In particular, the scan operation selection signal SC output from the multiplexer controller 2340 is provided as a scan enable signal se to test the internal operation of the core. In addition, the core 2390 receives the clock signal STCLK provided from the scan test clock generator 2360 as a driving clock of the scan chain.

The IEEE 1500 wrapped core 230 according to the present invention may be accessed as a command input through the IEEE1149.1 TAP controller 210. In addition, a plurality of IEEE 1500 Wrapped cores including such components may independently perform internal delay test operations. Here, although a wrapper configuration that complies with the IEEE 1500 standard has been described with respect to the core 230, it is understood that all IP cores included in a system on chip (SoC) may be configured in the same manner as the illustrated core 230. It is self-evident to those who have acquired common knowledge.

5A and 5B illustrate each of an input wrapper boundary cell (hereinafter referred to as IWBC) and an output wrapper boundary cell (hereinafter referred to as OWBC) constituting the wrapper boundary registers 2370 and 2380 of FIG. 4. Figure showing. 5A and 5B, each of the wrapper boundary cells (WBCs) of the present invention has the same structure. The operation of the wrapper boundary cells according to each operation mode will be described in more detail as follows.

The wrapper boundary cell WBC has a test input (CTI) and a test output (CTO) and a function input (CFI) and a function output (CFO) terminal. The terminals receive control signals SC, WCI, and WCO and a clock signal CLK for shifting or capturing data. The operation selection signal SC is provided as a logic '1' during the shift operation and a logic '0' during the capture operation. The control signal WCI is provided as a logic '1' in the core test operation by the scan chain and as a logic '0' in the external test operation for testing the connection relationship between the cores. The control signal WC0 maintains a complementary relationship with the control signal WCI. As a result, the wrapper boundary cell WBC receives the test input CTI as each flip-flop FFI and FFO in the shift mode and stores it in synchronization with the clock signal CLK. In the wrapper boundary register WBR, which is a collection of respective wrapper boundary cells WBC, such a shift operation occurs at the same time to perform the same action as the shift register.

During test operation by the internal scan chain, the multiplexer of the input wrapper boundary cell (IWBC) scans the test output (CTO) provided from the flip-flop (FFI) in response to the control signal (WCI) set to logic '1'. Supply to the chain. On the other hand, the output wrapper boundary cell OWBC selects the function input CFI output from the scan chain inside the core in response to the control signal WCO set to a logic '0'. In an external test operation for testing a path between cores, wrapper boundary cells (WBCs) are controlled as opposed to an internal test operation.

According to the circuit structure described above, the wrapper boundary cell (WBC) of the present invention can perform a shift and capture operation without including an update register and including one register (or flip-flop). Thus, it is possible to support a simplified control structure.

6 is a circuit diagram briefly showing a scan chain structure according to the present invention. Referring to FIG. 6, the scan chain 2391 includes multiplexers 2392 and 2393 for selecting a scan path by the scan enable signal se between the scan flip-flops FF1 and FF2. The scan enable signal se is identical to the operation selection signal SC generated by the shift control signal ShftDR provided from the WSC-WBC decoder 2230 via the multiplexer controller 2340. Thus, the scan chain 2391 is controlled simultaneously with the wrapper boundary cells 2370 and 2380 driven by the operation selection signal SC. That is, the scan chain 2391 operates like a shift register when the scan enable signal se is a logic '1'. However, if the scan enable signal se maintains a logic '0', the scan chain 2391 will perform the capture operation by the multiplexers 2392 and 2393. The clock signal clk, which is supplied to the scan chain 2391, is provided with two launch-capture pulses for the at-speed test during the internal delay failure test.

FIG. 7 is a logic circuit diagram briefly showing an embodiment of the WSC-WBC decoder 2330 of FIG. 4 described above. Referring to FIG. 7, the WSC-WBC decoder 2330 receives the wrapper instructions (ShiftWR, CaptureWR, UpdateWR, SelectWIR) and a clock signal WRCK provided from the TAP controller 210 and the glue logic 220. In addition, the WSC-WBC decoder 2330 may refer to the input wrapper commands ShiftWR, CaptureWR, UpdateWR, and SelectWIR and the clock signal WRCK to control the wrapper boundary cells or the internal scan chains (ShiftDR, CapDR, UpDR) and a clock signal GWRCK are generated. When the capture command (CaptureWR) or the shift command (ShiftWR) is activated while the select signal (SelectWIR) for selecting the command register is set to 'LOW', the clock signal (GWRCK) for driving the boundary cells is output. On the other hand, the supply of the clock signal GWRCK for driving the boundary cells is blocked when the capture command CaptureWR or the shift command ShiftWR is both deactivated. Instructions for controlling the boundary cells or the internal scan chain (ShiftDR, CapDR, UpDR) are the wrapper control signal (WSC) provided from the TAP controller 210 when the select signal (SelectWIR) is set to the 'LOW' level as it is Delivered. In other words, commands that direct the shift, capture, and update operations are passed directly.

The test clock (TCK = WRCK) input to the TAP controller 210 through the WSC-WBC decoder 2330 is converted into the first re-shape clock signal GWRCK for the internal delay failure test of the scan chain. do.

8 is a logic circuit diagram exemplarily illustrating a configuration of the multiplexer controller 2340 of FIG. 4. Referring to FIG. 8, the multiplexer controller 2340 may include a wrapper operation selection signal SC and a boundary cell control signal WCI in response to a mode signal MODE and a control signal I0_FACE provided from the wrapper command register 2310. WCO). The control signal I0_FACE is already defined in IEEE 1500 and defines a core internal test or a connection relationship test between cores. The multiplexer controller 2340 generates a control signal WCI for activating the input boundary register 2370 in response to the control signal IO_FACE and the shift register control signal MODE. The multiplexer controller 2340 generates a control signal WCO for activating the output boundary register 2380 in response to the input / output control signal IO_FACE and the shift register control signal MODE. Here, the mode signal MODE maintains a logic '1' in the test mode and maintains a '0' in the normal mode. The control signal IO_FACE maintains logic '1' during the internal test operation of the cores and maintains logic '0' during the path test between the cores. Accordingly, output signals SC, WCI, and WCO of the multiplexer controller 2340 are as follows. The operation selection signal SC selects a shift or capture operation. The operation selection signal SC should be '1' when shifting and '0' when capturing, and the control signal ShftDR provided from the WSC-WBC decoder 2330 is directly provided. In the internal test operation, the border cell control signal WCI is set to logic '1' and the border cell control signal WCO is set to logic '0', respectively. On the other hand, in the inter-core test operation, the boundary cell control signal WCI is set to logic '0' and the boundary cell control signal WCO is set to logic '1', respectively.

9 is a timing diagram briefly showing the output of the WSC-WBC decoder 2330 and the multiplexer controller 2340 for the state of the TAP controller 210. The TAP controller 210 state of FIG. 9 shows the control signals provided for in-core testing through the scan chain 2391. Shift and Capture operations are performed simultaneously on the wrapper boundary cell and the scan chain. As a result, for the internal test command WS_INTEST using the IEEE 1500 wrapper and WS_INTEST_SCAN, the wrapper serial control signal (WSC), the test procedure is performed with only the patterns being different. In the WS_EXTEST test instruction between cores, the multiplexer excludes the scan chain path and directly connects the input wrapper boundary cell and the output wrapper boundary cell.

Through the above-described timing diagram, it can be seen that the signals controlling the scan chain and the wrapper boundary cells are all dependent on the state of the TAP controller 210. Therefore, even inexpensive automated test equipment (ATE) adopting the IEEE 1149.1 standard, the internal delay failure test of the SoC 200 of the present invention can be easily performed.

FIG. 10A is a logic circuit diagram schematically illustrating the configuration of the boundary test clock generator 2350 of FIG. 4. Referring to FIG. 10A, the boundary test clock generator 2350 may include one of clock signals IWRTCLK and OWRTCLK or shift clock SftCLK for driving boundary cells depending on whether an internal delay test operation is performed by the scan chain 2391. Which one is provided. Here, the shift clock SftCLK generated from the boundary test clock generator 2350 is provided to the scan test clock generator 2360 and used to generate the scan test clock STCLK. Here, the output boundary register 2380 must capture the delay test result at the point when the launch-capture clock is provided to the scan chain. The clock signal OWRTCLK provided to this output boundary register 2380 is provided using an updater control signal UpDR that is not used in the wrapper boundary register.

Traditionally, scan delay tests are based on launch-off-shift and broad-side approaches. The launch-off-shift method can provide wider test coverage with a smaller number of test patterns than the broad-side method. However, because of the skew of the scan enable signal se generated in the launch-off-shift method, a broad-side method is widely used. The wrapper instruction register 2310 of the present invention includes a WS_DELAYINTEST_SCAN instruction. In response to the WS_DELAYINTEST_SCAN command, test clock generation means and a test method necessary for the delay test using the scan chain 2391 are provided. Although the test chain and WBR can capture at the same time after entering the test pattern by the WS_INTEST_SCAN command, the test can be performed.However, in the delay test, the output wrapper boundary cell first before launch-capture is performed in the scan chain. You need to capture the Primary Output in. While performing capture at the output wrapper boundary cell and launch-capture in the scan chain, the input wrapper boundary cell must maintain the primary input value. Therefore, a separate test clock needs to be generated for each of the input wrapper boundary cell, the output wrapper boundary cell, and the scan chains.

10B is a timing diagram that briefly illustrates the operation of the boundary test clock generator 2350 described above. Referring to FIG. 10B, an operation of the boundary test clock generator 2350 is illustrated in an internal delay test operation in which the delay test signal WS_DELAYINTEST_SCAN maintains a high level 'H'. When the delay test signal WS_DELAYINTEST_SCAN maintains the low level 'L', the boundary test clock generator 2350 outputs the clock signal GWRCK as it is.

During the internal delay test operation, look at the output of the boundary test clocks IWRTCLK and OWRTCLK in response to the control signals CapDR and UpDR. First, when the control signal ShftDR transitions to a low level, the operation selection signal SC directly connected to the control signal ShftDR is transitioned to the same waveform. Then, the clock signal GWRCK is cut off in a section in which the control signal ShftDR and the control signal CapDR simultaneously maintain a low level. In a section in which the control signal ShftDR and the control signal CapDR simultaneously maintain a low level, the level of the control signal UpDR is provided to the test clock of the output boundary cell. Thus, the boundary cell of the output boundary register 2380 will latch test result data input in synchronization with the rising edge of the boundary test clock OWRTCLK.

The boundary register WBR of the present invention does not include an update register. Therefore, during the internal delay failure test, the capture operation of the output boundary register OWBR can be controlled through the control signal UpDR.

11A is a block diagram schematically illustrating a configuration of a scan test clock generator 2360. Referring to FIG. 11A, the scan test clock generator 2360 may perform a logical OR between the launch-capture clock LCCLK and the shift clock SftCLK to scan scan clocks used for an at-speed launch capture. STCLK).

The clock signal DTCLK is selected by the multiplexers 2363 and 2364 in the test mode (MODE = '1') and the internal delay test (WS_DELAYINTEST_SCAN = '1'). The clock signal is a clock signal in which the shift clock SftCLK and the launch-capture clock LCCLK are ORed by the OR gate 2362. Here, the launch-capture clock generator 2361 corresponds to core clock pulses corresponding to the pulse period of the control signal UpDR delayed for a predetermined time.

FIG. 11B is a timing diagram for describing an operation of the scan test clock generator 2360 described above. Referring to FIG. 11B, the clock signal GWRCK is blocked while the control signal ShftDR or the scan enable signal se is at a low level in the internal delay test mode (ie, WS_DELAYINTEST_SCAN = '1'). As a result, the shift clock SftCLK from which the test clock is removed is generated while the scan enable signal se is maintained at the low level. The launch-capture clock generator 2361 detects a case where the control signal UpDR is at a high level and delays a predetermined period to generate a launch-capture clock LCLC that is AND-operated with the core clock signal CoreCLK. do. Again, the shift clock SftCLK and the launch-capture clock LCCLK are output as the clock signal DTCLK by an OR operation by the OR gate 2322. The clock signal DTCLK is again selected by the multiplexers 2363 and 2364 in the test mode (MODE = '1') and internal delay test (WS_DELAYINTEST_SCAN = '1') and output to the scan test clock STCLK. do.

According to the scan test clock STCLK generated by the scan test clock generator 2360 described above, the test clock TCK provided from the TAP controller 210 is provided to the scan chain during the internal test operation by the scan chain. . However, during the At-speed launch-capture test (i.e. se = '0'), the clock generated from the PLL is scanned to provide accurate launch and capture pulses. To the chain. Thus, accurate at-speed test of the commercial frequency of the core is possible.

FIG. 12A is a block diagram illustrating an example of the launch-capture clock generator 2361 of FIG. 11A described above. Referring to FIG. 12A, the launch-capture clock generator 2361 includes a state machine 2362 that determines whether a launch-capture clock is generated according to control signals CapDR and UpDR and a data state of the core clock CoreCLK. Include. The launch-capture clock generator 2361 further includes a clock gating cell 2363 for generating a launch-capture clock of the same clock frequency as the core clock in response to the control signal en from the state machine 2362. . The clock gating cell 2363 includes a latch circuit that latches the control signal en output from the state machine 2362 in synchronization with the core clock CoreCLK. The latch circuit provides a value latched by the core clock CoreCLK as the gate control signal gc. As a result, the clock gate cell 2363 outputs the core clock CoreCLK corresponding to the pulse period of the gate control signal gc to the launch-capture clock LCCKL by the AND gate. According to the configuration of the clock gating cell 2363, the time difference between the launch and capture operations is synchronized with the period of the core clock. Thus, the glitches according to the clock frequency offset may be blocked.

FIG. 12B is a state diagram illustrating the operation of the state machine 2362 of FIG. 12A described above. Referring to FIG. 12B, the state machine 2362 sequentially sets the level of the control signal in synchronization with the core clock CoreCLK according to the states of the control signals CapDR and UpDR. Looking at the closed state, the state machine 2362 maintains the blocked state when the logic value of the control signal CapDR is '1', and when the level of the control signal CapDR is '0'. Transition to an idle state for detecting the level of the control signal UpDR. During the closed stage, the control signal en remains in an inactive ('0') state. Upon entering the idle state, the state machine 2362 waits for a moment when the control signal UpDR transitions to a logic value '1'. If the control signal UpDR transitions to the logic value '1', the state of the state machine 2362 moves to the launch stage. However, when the logic value of the control signal UpDR is '0', the state maintains an idle state and the control signal en maintains a logic '0'. In the launch stage, the control signal en is set to a logic '1' and unconditionally transitions to the capture state. Even in the capture state, the control signal en is set to a logic '1', and the state moves to the closed stage unconditionally in synchronization with the core clock CoreCLK. Thus, the state machine 2362 may generate the launch-capture clock LCCLK to perform the launch-capture operation in synchronization with two successive clocks of the same frequency as the core clock CoreCLK. 9C is a timing diagram illustrating operation of the launch-capture clock generator 2361 according to FIG. 9A described above.

FIG. 13 is a timing diagram illustrating an at-speed launch-capture test performed simultaneously on IEEE 1500 wrapped cores with different core clocks. Referring to FIG. 13, input / output terminals TCK, TRST, TMS, TDI, and TDO of the TAP controller 210 for the internal delay test of each core are set to the same level as shown. The control signal and the clock signal GWRCK generated from the TAP controller 210 and the glue logic 220 are provided to the cores Core A and Core B having the IEEE 1500 wrapper protocol. In this case, different core driving clocks CoreCLKA and CoreCLKB provided from the PLL 250 are provided to each core. Here, it is assumed that the test clock TCK is provided at 50 MHz, the core clock CoreCLKA is 125 MHz, and the core clock CoreCLKB is provided at 200 MHz.

By the above wrapper control signal WSC, the wrapper command register WIR activates the control signal WS_DELAYINTEST_SCAN for the internal delay test to the 'HIGH' level. In synchronization with the activation of the scan enable signal se, each of the two cores performs an at-speed launch-capture test. Each of the two cores performs an internal delay test operation on a different core clock CoreCLK. As can be seen from the timing diagram, it can be seen that the at-speed launch-capture test is smoothly performed for the respective cores while the scan enable signal se is maintained at the low level '0'.

An SoC configuration capable of effectively controlling IP cores having the IEEE 1500 wrappers described above through an IEEE 1149.1 controller is provided. This configuration can provide a SoC that can be tested at high speed using test equipment having the same control scheme as in the prior art without using a separate expensive ATE.

Table 3 below shows the pin-count savings efficiency for each SoC. Each basic table shows the basic number of pins (Basic) to be provided for testing and the number of pins implemented by the IEEE 1149.1 TAP controller of the present invention. More than 90% pin count savings for most SoCs.

Test Pin Count Comparison Table SoC Benchmarks Test pin count Reduction Rate (%) Basic Proposed u226 56 5 91.07 h953 56 5 91.07 g1023 70 5 92.86 f2126 391 5 98.72 p22810 176 5 97.16 P34392 176 5 97.16 p93791 251 5 98.01 t512505 163 5 96.93 a586710 204 5 97.55

 As described above, the present invention can reduce the SoC test cost by using the existing low-cost ATE. By controlling the IEEE 1500 wrapper through the TAP controller 210 to test cores, the test pin count is reduced, and an at-speed launch-capture clock generator is implemented to enable scan-based latency testing. I did it. The use of a TAP controller eliminates the need to add a separate test access device (TAM), and is a well-known standard that makes it easy for test engineers to access. In addition, the at-speed launch-capture clock generator is synchronized with the operation clock of each core, so that a delay failure test of cores using different clocks can be simultaneously performed. Since all I / O and scan chains in a SoC are organized in a single path, testing a single SoC takes a relatively long time, but reduces testing time by testing multiple SoCs simultaneously through multi-site testing. can do.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

1 is a block diagram showing the configuration of an IEEE 1500 wrapped core;

2 is a block diagram illustrating a test access mechanism for an IEEE 1500 wrapped core via a TAP controller in accordance with the present invention;

3A is a block diagram illustrating the configuration of the glue logic of FIG. 2.

3B is a timing diagram illustrating operation of the TAP controller and glue logic of FIG. 2;

4 is a block diagram showing an IP core having a wrapper of the IEEE 1500 standard according to the present invention;

5A and 5B are block diagrams showing the structure of the wrapper boundary cell of the present invention;

6 is a block diagram showing the structure of a scan chain according to the present invention;

7 is a logic circuit diagram showing a WSC-WBC decoder;

8 is a logic circuit diagram showing the structure of a multiplexer controller;

9 is a timing diagram showing control operations of a wrapper boundary cell and a scan chain by the above-described WSC-WBC decoder and multiplexer controller;

10A is a logic circuit diagram showing the configuration of the boundary test clock generator of FIG. 4;

10B is a timing diagram illustrating operation of the boundary test clock generator of FIG. 10A.

FIG. 11A is a logic circuit diagram illustrating the configuration of the scan test clock generator of FIG. 4; FIG.

11B is a timing diagram illustrating operation of the scan test clock generator of FIG. 11A;

12A is a logic circuit diagram showing the configuration of the launch-capture clock generator of FIG. 11A;

12B is a state transition diagram illustrating the operation of the state machine of FIG. 12A;

12C is a timing diagram illustrating the operation of the launch-capture clock generator of FIG. 12A;

FIG. 13 is a timing diagram showing at-speed test results for each IP core of the system-on-chip of FIG. 2. FIG.

* Description of the symbols for the main parts of the drawings *

110: wrapper instruction register 120: wrapper bypass register

130: core 131, 132: scan chain

140: input wrapper boundary register 150: output wrapper boundary register

210: TAP controller 220: glue logic

230, 240: IEEE 1500 wrapped core 250: Phase locked loop (PLL)

2310: wrapper instruction register 2320: wrapper bypass register

2330 WSC-WBC decoder 2340 multiplexer controller

2350: boundary test clock generator 2360: scan test clock generator

2361: Launch-Capture Clock Generator 2362: State Machine

2363: clock gating cell (CGC) 2370: input wrapper boundary register

2380 output wrapper boundary register 2390 core

2391: scan chain

Claims (16)

For a system-on-chip tested according to a wrapper control signal (WSC) generated from a tap controller of the IEEE 1149.1 standard: A core clock generation circuit for providing one or more core driving clocks; And One or more cores of the IEEE 1500 standard having an input boundary register, an output boundary register, and a scan chain for performing a test operation in response to the wrapper control signal (WSC) and the core drive clock; In an internal delay test operation, the core controls an input boundary register, the scan chain and an output boundary register to be connected in series in response to the wrapper control signal WSC and the core driving clock, and clocks into the scan chain. And a wrapper control block for providing an at-speed test clock generated in a gating manner. The method of claim 1, The wrapper control block, A wrapper instruction register configured to generate an internal delay failure test signal WS_DELAYINTEST_SCAN and a test mode signal MODE and IO_FACE in response to the wrapper control signal WSC; The test clock WRCK included in the wrapper control signal WSC is converted to the first test clock GWRCK deactivated during the internal delay failure test operation, and the shift command ShftDR is converted from the wrapper control signal WSC. A decoder for generating an update instruction UpDR and a capture instruction CapDR; A multiplexer controller configured to configure a serial connection by controlling multiplexers included in each of the input and output wrapper boundary registers and the scan chain in response to the test mode signal MODE, IO_FACE and a shift instruction (ShftDR); A boundary test clock generator providing the first test clock GWRCK as a driving clock of the input and output boundary registers with reference to the capture command CapDR and the update command UpDR; And And a scan test clock generator for providing two consecutive pulses of the core driving clock to the at-speed test clock during an internal delay failure test. -On-chip. The method of claim 2, The at-speed test clock includes a launch pulse and a capture pulse provided to the scan chain. The method of claim 2, System-on-chip, wherein the boundary cells included in the input boundary register and the output boundary register do not include an update register. The method of claim 2, And the boundary test clock generator provides an output boundary register clock for the output boundary register to perform a capture operation in response to the update command (UpDR). The method of claim 2, The scan test clock generator, A launch-capture clock generator configured to generate a launch-capture clock (LCCLK) by detecting a state of the update instruction (UpDR) according to the states of the capture command (CapDR) and the update command (UpDR); A calculation circuit configured to generate a clock signal DTCLK by performing an OR operation on the launch-capture clock LCCLK and the clock SftCLK provided to the input boundary register; And And a selection circuit to provide the clock signal DTCKL to the at-speed test clock STCLK in response to the internal delay failure test command WS_DELAYINTEST_SCAN. The method of claim 6, And the launch-capture clock generator is driven by the core drive clock. The method of claim 6, The launch-capture clock generator, A state machine generating an enable signal when the update command UpDR transitions to a high level while the capture command CapDR is at a low level; And And a clock gating cell for passing only a core driving clock corresponding to a pulse duration of the enable signal delayed by a predetermined time. The method of claim 8, The clock gating cell, A latch circuit for latching the enable signal in synchronization with the falling edge of the core clock; And And a logic product operation circuit for performing an AND operation on the output of the latch circuit and the core driving clock to provide to the launch-capture logic. The method of claim 1, And wherein said core clock generation circuit is comprised of a phase locked loop circuit. The method of claim 10, And the core clock generation circuit provides core drive clocks corresponding to a drive frequency of each of a plurality of cores. In a method for performing an internal delay failure test on a core of a system-on-chip having a wrapper of IEEE 1500 specification: Providing an internal delay failure test command to a wrapper command register (WIR) via a step controller of the IEEE 1149.1 standard and providing a core drive clock through the PLL; Controlling multiplexers included in each of the input boundary register, the scan chain and the output boundary registers so that the input boundary register, the scan chain, and the output boundary registers included in the IP core are connected in series according to the internal delay failure test command. Signal (SC = se, WCI, WCO), a clock-gated launch-capture clock (LCCLK) that supports launch-capture operation of the scan chain, and clock signals (IWRTCLK) to be provided to the input and output boundary registers. OWRTCLK); And Provide the control signal (SC = se, WCI, WCO) and the clock signals (IWRTCLK, OWRTCLK) to the input boundary register and output boundary register and the launch-capture clock to the scan chain to An internal delay failure test method comprising the step of receiving a test result that is captured. The method of claim 12, The wrapper command register (WIR) further generates a control signal (WS_DELAYINTEST_SCAN) corresponding to the internal delay failure test command. The method of claim 12, The wrapper boundary cells included in the input and output boundary registers do not have an update register. The method of claim 14, The launch-capture clock LCCK is provided to the scan chain when the update instruction UpDR is activated while the capture instruction CapDR is inactivated in the wrapper instruction register WIR. Testing method. The method of claim 15, And the clock signal (OWRTCLK) is activated such that the output wrapper boundary register performs a capture operation upon activation of the updater command (UpDR).

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