KR20090022120A - Non-volatile memory device and method of manufacturing the non-volatile memory device - Google Patents

Abstract

A non-volatile memory device and a manufacturing method thereof are provided to reduce the intensity of the electric field generated by a control gate electrode and a substrate by forming the narrower control gate electrode than the floating gate electrode. A tunnel insulating layer(102) is formed on a substrate(100). A floating gate electrode(118) is formed on the tunnel insulating layer and has a first line width. A dielectric pattern(114) is formed on the floating gate electrode and has a second line width smaller than the first line width. The control gate electrode(112) is formed on the dielectric pattern and has a third line width smaller than the first line width. The second line width is equal to the third line width. A spacer(116) is formed on the side of the control gate electrode and the dielectric pattern. The mask is formed on the control gate electrode and has the line width equal to the third line width.

Description

Non-volatile memory device and method for manufacturing the same

The present invention relates to a nonvolatile memory device and a method of manufacturing the same. More particularly, the present invention relates to a nonvolatile memory device capable of reducing the influence of an electric field between a floating gate electrode and a control gate electrode and a method of manufacturing the same.

In general, the nonvolatile memory device is a floating gate type nonvolatile memory device and a charge trap type nonvolatile memory device according to the structure of a unit cell. Can be divided into

The unit cell of the floating gate type nonvolatile memory device includes a tunnel insulating layer, a floating gate electrode, a dielectric layer pattern, and a control gate electrode.

Referring to the process of forming the floating gate type nonvolatile memory device, a tunnel insulating film and a first conductive film are first formed on a substrate, and then the first conductive film is patterned to form a first conductive pattern extending in one direction. do. A dielectric film and a second conductive film are formed on the first conductive pattern. A mask is formed on the second conductive layer, and the second conductive layer, the dielectric layer, and the first conductive pattern are etched using the mask as an etch mask to form a control gate electrode, a dielectric layer pattern, and a floating gate electrode. do. In this case, the control gate electrode, the dielectric layer pattern, and the floating gate electrode are formed to have substantially the same line width.

As the degree of integration of the nonvolatile memory device is improved, the spacing between unit cells of the nonvolatile memory device is reduced. When the unit cell spacing is reduced, interference is generated between the unit cells and the thickness of the floating gate electrode is made thin in order to suppress this.

At this time, if the thickness of the floating gate electrode is reduced, the width between the control gate electrode and the substrate is reduced. As such, when the width between the control gate electrode and the substrate is reduced, when a predetermined voltage is applied to the control gate electrode to program or erase the unit cell, a predetermined voltage is applied across the gate electrode. An electric field is generated. Such an electric field may act as a decisive factor for greatly reducing the reliability of the nonvolatile memory device.

In addition, parasitic capacitance may be generated between the control gate electrodes of adjacent unit cells. Such parasitic capacitance may affect the read operation of the nonvolatile memory device, thereby causing an error in threshold voltage sensing, which also degrades the reliability of the nonvolatile memory device.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a nonvolatile memory device capable of suppressing parasitic capacitance generated between adjacent unit cells and suppressing generation of an electric field in each unit cell. .

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device which is particularly suitable for a nonvolatile memory device having the above-described characteristics.

In order to achieve the above object of the present invention, a nonvolatile memory device according to the embodiments of the present invention, a tunnel insulating film formed on a substrate, a floating gate electrode formed on the tunnel insulating film having a first line width, A dielectric layer pattern formed on the floating gate electrode and having a second line width narrower than the first line width, and a control gate electrode formed on the dielectric layer pattern and having a third line width narrower than the first line width. Here, the second line width and the third line width may be substantially the same.

In example embodiments, the nonvolatile memory device may further include a spacer formed on side surfaces of the dielectric layer pattern and the control gate electrode.

In example embodiments, the nonvolatile memory device may further include a mask formed on the control gate electrode and having a line width substantially the same as the third line width. In this case, the nonvolatile memory device may further include a spacer formed on side surfaces of the dielectric layer pattern, the control gate electrode, and the mask.

In example embodiments, the nonvolatile memory device may further include a source / drain formed in the substrate adjacent to the floating gate electrode.

In order to achieve the above object of the present invention, in the method of manufacturing a nonvolatile memory device according to the embodiments of the present invention, after forming a tunnel insulating film on a substrate, a conductive pattern is formed on the tunnel insulating film . After forming a dielectric film and a conductive film on the conductive pattern, a mask is formed on the conductive film. The conductive layer and the dielectric layer are etched using the mask as an etch mask to form a control gate electrode having a first line width and a dielectric layer pattern having a second line width. Spacers are formed on side surfaces of the control gate electrode and the dielectric layer pattern. The conductive pattern is etched using the control gate electrode, the dielectric layer pattern, and the spacer as an etching mask to form a floating gate having a third line width that is substantially larger than the first line width and the second line width. The mask may be removed after the dielectric layer pattern and the control gate electrode are formed.

In example embodiments, a source / drain may be formed on the substrate adjacent to the floating gate electrode.

According to the present invention, by forming a control gate electrode that is substantially narrower than the floating gate electrode, it is possible to weaken the intensity of the electric field generated by the control gate electrode and the substrate, and parasitic capacitance generated between adjacent control gate electrodes. Can be suppressed. Accordingly, reliability of the nonvolatile memory device including the floating gate electrode and the control gate electrode can be improved.

Although a nonvolatile memory device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, the present invention is not limited to the following embodiments, and has ordinary skill in the art It will be apparent to those skilled in the art that the present invention may be embodied in various other forms without departing from the spirit of the invention.

In the accompanying drawings, the dimensions of the substrate, film, region, pad or patterns are shown to be larger than the actual for clarity of the invention. In the present invention, when each film, region, pad or pattern is referred to as being formed "on", "upper" or "top surface" of a substrate, each film, region or pad, each film, region, Meaning that the pad or patterns are formed directly on the substrate, each film, region, pad or patterns, or another film, another region, another pad or other patterns may be additionally formed on the substrate. In addition, where each film, region, pad, region or pattern is referred to as "first," "second," and / or "third," it is not intended to limit these members, but merely to define the cornea, region, pad, To distinguish between areas or patterns. Thus, "first", "second" and / or "third" may be used selectively or interchangeably for each film, region, pad, site or pattern, respectively.

1 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.

Referring to FIG. 1, the nonvolatile memory device may include a tunnel insulating layer 102, a floating gate electrode 118, a dielectric layer pattern 114, a control gate electrode 112, and a spacer 116 formed on a substrate 100. And source / drain 120.

The substrate 100 may include a semiconductor substrate such as a silicon substrate or a germanium substrate, or may include a silicon on insulator (SOI) substrate or a german on insulator (GOI) substrate.

A field insulating layer pattern (not shown) may be formed on the substrate 100, and the substrate 100 may be divided into an active region and a field region by the field insulating layer pattern.

The tunnel insulating layer 102 is formed on the active region of the substrate 100. The tunnel insulating layer 102 may be made of an oxide such as silicon oxide.

The floating gate electrode 118 is formed on the tunnel insulating film 102. In embodiments of the present invention, the floating gate electrode 118 has a first line width. For example, the floating gate electrode 118 may have a hexahedral structure. The floating gate electrode 118 may include silicon, metal, and / or metal compound doped with impurities.

The dielectric layer pattern 114 is formed on the floating gate electrode 118. The dielectric layer pattern 114 may have a second line width that is substantially narrower than the first line width of the floating gate electrode 118. The dielectric layer pattern 114 may include silicon oxide (SiO ₂ ), oxide / nitride / oxide, or a material having a high dielectric constant.

The high dielectric constant material included in the dielectric layer pattern 114 is a material having a higher dielectric constant than that of nitride. For example, aluminum oxide (Al ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), hafnium oxide (HfO ₂ ), Metal oxides such as zirconium oxide (ZrO ₂ ), niobium oxide (Nb ₂ O ₅ ), barium titanium oxide (BaTiO ₃ ), and strontium titanium oxide (SrTiO ₃ ) may be included. The dielectric layer pattern 114 may have a single layer structure including at least one of the above materials or a multilayer structure made of the above materials.

In this case, as an example in which the dielectric film pattern 114 has a multilayer structure, a structure including an oxide / material having a high dielectric constant, a structure including an oxide / material having a high dielectric constant, and a material / oxide having a high dielectric constant may be included. The structure etc. are mentioned.

The control gate electrode 112 is formed on the dielectric layer pattern 114. The control gate electrode 112 may have a third line width that is substantially narrower than the first line width. In addition, the control gate electrode 112 may extend in substantially the same direction as the direction in which the dielectric layer pattern 114 extends. In example embodiments, the third line width of the control gate electrode 112 may be substantially the same as the second line width of the dielectric layer pattern 114. The control gate electrode 112 may include polysilicon, a metal, and / or a metal compound doped with impurities. In addition, the control gate electrode 112 may have a single layer structure composed of at least one of the above materials or a multilayer structure including the above materials.

The spacer 116 is formed on the side surfaces of the dielectric film pattern 114 and the control gate electrode 112. The spacer 116 may be made of a nitride such as silicon nitride. The spacer 116 causes a line width difference between the floating gate electrode 118 and the control gate electrode 112. That is, when the floating gate electrode 118 has a first line width and the control gate electrode 112 has a third line width that is narrower than the first line width, the difference between the first line width and the third line width is the spacer 116. It can be substantially the same as the line width.

As described above, when the line width of the control gate electrode 112 is smaller than the line width of the floating gate electrode 118, parasitic capacitance between neighboring control gate electrodes 112 may be reduced. In addition, it is possible to reduce the electric field strength generated across the substrate 100 and the control gate electrode 112 in each unit cell.

The source / drain 120 is formed in predetermined regions of the substrate 100 adjacent to the floating gate electrode 118, the dielectric layer pattern 114, the control gate electrode 112, and the spacer 116.

2 is a cross-sectional view illustrating a nonvolatile memory device in accordance with some example embodiments of the present invention. In the nonvolatile memory device illustrated in FIG. 2, components except for the mask 206 and the spacer 212 are substantially the same as those of the nonvolatile memory device described with reference to FIG. 1, and thus a detailed description thereof is omitted. do.

Referring to FIG. 2, the nonvolatile memory device may include a tunnel insulating film 202, a floating gate electrode 214, a dielectric film pattern 210, a control gate electrode 208, and a mask 206 formed on a substrate 200. ), A spacer 212 and a source / drain 216.

The tunnel insulating layer 202 is formed on the substrate 200, and the floating gate electrode 214 positioned on the tunnel insulating layer 202 may have a first line width.

The dielectric layer pattern 210 formed on the floating gate electrode 214 may have a second line width narrower than the first line width, and the control gate electrode 208 formed on the dielectric layer pattern 210 may have the first line width. It may have a narrower third line width.

The mask 206 is formed on the control gate electrode 208 and may have a line width that is substantially the same as the third line width of the control gate electrode 208. Mask 206 may comprise a nitride, such as silicon nitride, and functions as an etch mask.

The spacer 212 is formed on the side surfaces of the dielectric film pattern 210, the control gate electrode 208, and the mask 206. Spacer 212 may include a nitride, such as silicon nitride. The spacer 212 generates a line width difference between the floating gate electrode 214 and the control gate electrode 208. For example, when the floating gate electrode 214 has a first line width and the control gate electrode 208 has a third line width narrower than the first line width, the line width of the spacer 212 is the first line width and the first line width. It is substantially the same as the difference in the three line widths.

The source / drain 216 may be a substrate 200 under the tunnel insulating layer 202 exposed by the floating gate electrode 214, the dielectric layer pattern 210, the control gate electrode 208, the mask 206, and the spacer 212. Are formed in certain portions of the < RTI ID = 0.0 >

3 through 9 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with example embodiments of the inventive concept.

Referring to FIG. 3, a tunnel insulating layer 102 is formed on the substrate 100. The substrate 100 may include a semiconductor substrate including silicon or germanium, an SOI substrate, or a GOI substrate. The tunnel insulating layer 102 may be formed using an oxide such as silicon oxide. The tunnel insulating layer 102 may be formed using a chemical vapor deposition process or a thermal oxidation process.

Referring to FIG. 4, a first conductive film (not shown) is formed on the tunnel insulating film 102. The first conductive layer may be formed by depositing polysilicon, a metal, and / or a metal compound doped with impurities by a chemical vapor deposition process or a physical vapor deposition process. The first conductive layer functions as the floating gate electrode 114 (see FIG. 9) of the nonvolatile memory device.

A first mask (not shown) is formed on the first conductive layer. The first mask may be formed using a nitride such as silicon nitride, and extends along a predetermined direction on the substrate 100. The first conductive layer is etched using the first mask as an etch mask to form a first conductive pattern 104 extending in the substantially same direction as the first mask on the tunnel insulating layer 102. After forming the first conductive pattern 104, the first mask is removed.

Referring to FIG. 5, a dielectric film 106 is formed on the first conductive pattern 104. The dielectric layer 106 may include silicon oxide (SiO ₂ ), oxide / nitride / oxide, or a material having a high dielectric constant.

The high dielectric constant material included in the dielectric film 106 is a material having a higher dielectric constant than that of nitride. For example, aluminum oxide (Al ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), hafnium oxide (HfO ₂ ), and zirconium Metal oxides such as oxide (ZrO ₂ ), niobium oxide (Nb ₂ O ₅ ), barium titanium oxide (BaTiO ₃ ), and strontium titanium oxide (SrTiO ₃ ) may be included. The dielectric layer 106 may have a single layer structure including at least one of the above materials or a multilayer structure made of the above materials.

In this case, the dielectric film 106 may include a structure including a material having an oxide / high dielectric constant, a structure including a material / oxide having a high dielectric constant, and a structure including a material / oxide having a high dielectric constant. Etc. can be mentioned.

The dielectric film 106 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

Referring to FIG. 6, a second conductive layer 108 is formed on the dielectric layer 106. The second conductive layer 108 may be formed using polysilicon, a metal, and / or a metal compound doped with impurities. The second conductive layer 108 may be formed on the dielectric layer 106 by a chemical vapor deposition process or a physical vapor deposition process. The second conductive layer 108 may function as the control gate electrode 112 (see FIG. 7) of the nonvolatile memory device.

Referring to FIG. 7, a second mask 110 is formed on the second conductive layer 108. The second mask 110 may extend in a direction different from the direction in which the first mask extends. For example, the second mask 110 may extend in a direction substantially perpendicular to the first mask.

The second conductive layer 108 and the dielectric layer 106 are etched through an etching process using the second mask 110 as an etching mask, and the dielectric layer pattern 114 and the control gate electrode (eg, the first conductive pattern 104) are etched on the first conductive pattern 104. 112). The dielectric layer pattern 114 formed by the etching process may have a first line width, and the control gate electrode 112 may have a second line width. In this case, since the dielectric layer pattern 114 and the control gate electrode 112 are patterned using the second mask 110, the first line width and the second line width may be substantially the same.

Referring to FIG. 8, the second mask 110 is removed to expose the control gate electrode 112, and then a spacer 116 is formed on the dielectric layer pattern 114 and the side surfaces of the control gate electrode 112. Spacer 116 may be formed using a nitride, such as silicon nitride.

In the process of forming the spacer 116, the surface profile of the dielectric layer pattern 114 and the control gate electrode 112 may be formed on the first conductive pattern 104 and the tunnel insulating layer 102. Accordingly, nitride is used to form a thin film. Such a thin film may be formed by a chemical vapor deposition process or the like. The thin film is etched through an anisotropic etching process to form spacers 116 on side surfaces of the dielectric film pattern 114 and the control gate electrode 112.

Referring to FIG. 9, the first conductive pattern 104 is etched through an etching process using the dielectric layer pattern 114, the control gate electrode 112, and the spacer 116 as etching masks. By the etching process, the floating gate electrode 118, the dielectric layer pattern 114, the control gate electrode 112, and the spacer 116 are formed on the tunnel insulating layer 102. Here, the floating gate electrode 118 may have a third line width, and the third line width may be substantially wider than the first line width and the second line width. The difference between the third line width and the first line width (or the second line width) may correspond to the line width of the spacer 116.

As described above, since the line width of the control gate electrode 112 is smaller than the line width of the floating gate electrode 118, parasitic capacitance generated between adjacent control gate electrodes 112 can be suppressed. In addition, the strength of the electric field generated between the substrate 100 and the floating gate electrode 118 in the unit cell of each nonvolatile memory device may be reduced.

Subsequently, as shown in FIG. 1, using the floating gate electrode 118, the dielectric layer pattern 114, the control gate electrode 112, and the spacer 116 as ion implantation masks, under the tunnel insulating layer 102. Impurities are implanted into predetermined portions of the substrate 100 through an ion implantation process. After performing the ion implantation process, a diffusion process is performed to diffuse the implanted impurities to form the source / drain 120 in predetermined portions of the substrate 100 adjacent to the floating gate electrode 118. Accordingly, the unit cell of the nonvolatile memory device including the floating gate electrode 118, the dielectric layer pattern 114, the control gate electrode 112, the spacer 116, and the source / drain 120 is formed.

10 and 11 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with some example embodiments of the present invention.

Referring to FIG. 10, the tunnel insulating film 202, the first conductive pattern 204, and the dielectric film pattern (not shown) may be performed on the substrate 200 by performing substantially the same processes as those described with reference to FIGS. 3 to 7. 210, a control gate electrode 208, and a second mask 206 are formed.

Spacers 212 are formed on side surfaces of the dielectric layer pattern 210, the control gate electrode 208, and the second mask 206. Spacer 212 may be formed using a nitride, such as silicon nitride.

Referring to FIG. 11, the first conductive pattern 204 is etched through an etching process using the dielectric layer pattern 210, the control gate electrode 208, the second mask 206, and the spacer 212 as etching masks. . By the etching process, the floating gate electrode 214 is formed on the tunnel insulating film 202. That is, the floating gate electrode 214, the dielectric layer pattern 210, the control gate electrode 208, the second mask 206, and the spacer 212 are formed on the tunnel insulating layer 202.

In some example embodiments, the floating gate electrode 214 may have a third line width, which is greater than the first line width of the dielectric layer pattern 210 and the second line width of the control gate electrode 208. Can be substantially wide. In addition, the difference between the third line width and the first line width (or the second line width) may correspond to the line width of the spacer 212.

As described above, since the line width of the control gate electrode 208 is narrower than the line width of the floating gate electrode 214, parasitic capacitance occurring between adjacent control gate electrodes 208 can be suppressed. In addition, the intensity of the electric field generated between both ends of the control gate electrode 208 and the substrate 200 in the unit cell of each nonvolatile memory device may be reduced.

Subsequently, as shown in FIG. 2, the floating gate electrode 214, the dielectric layer pattern 210, the control gate electrode 208, the second mask 206 and the spacer 212 are used as ion implantation masks. The ion implantation process may be performed to implant impurities into predetermined portions of the substrate 200 adjacent to the floating gate electrode 214 through the tunnel insulating layer 202. Next, a diffusion process is performed to form the source / drain 216 on the substrate 200. Accordingly, the unit cell of the nonvolatile memory device including the floating gate electrode 214, the dielectric layer pattern 210, the control gate electrode 208, the second mask 206, the spacer 212, and the source / drain 216. To form.

According to the present invention, the parasitic capacitance generated between adjacent control gate electrodes can be suppressed by implementing a nonvolatile memory device having a narrower line width than the floating gate electrode. In addition, the strength of the electric field generated at both ends of the substrate and the floating gate electrode in each unit cell of the nonvolatile memory device may be reduced. Accordingly, the reliability of the read operation and the program operation of the nonvolatile memory device can be improved.

As described above, the present invention has been described with reference to the embodiments of the present invention, but those skilled in the art may variously change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that modifications and variations can be made.

1 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.

2 is a cross-sectional view illustrating a nonvolatile memory device in accordance with some example embodiments of the present invention.

3 through 9 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with example embodiments of the inventive concept.

10 and 11 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with some example embodiments of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 substrate 102 tunnel insulating film

112: control gate electrode 114: dielectric film pattern

116: spacer 118: floating gate electrode

120: source / drain

Claims (9)

A tunnel insulating film formed on the substrate; A floating gate electrode formed on the tunnel insulating layer and having a first line width; A dielectric layer pattern formed on the floating gate electrode and having a second line width smaller than the first line width; And And a control gate electrode formed on the dielectric layer pattern, the control gate electrode having a third line width smaller than the first line width. The nonvolatile memory device of claim 1, wherein the second line width and the third line width are the same. The nonvolatile memory device of claim 1, further comprising a spacer formed on side surfaces of the dielectric layer pattern and the control gate electrode. The nonvolatile memory device of claim 1, further comprising a mask formed on the control gate electrode and having a line width equal to the third line width. The nonvolatile memory device of claim 4, further comprising a spacer formed on side surfaces of the dielectric layer pattern, the control gate electrode, and the mask. The nonvolatile memory device of claim 1, further comprising a source / drain formed in the substrate adjacent to the floating gate electrode. Forming a tunnel insulating film on the substrate; Forming a conductive pattern on the tunnel insulating film; Forming a dielectric film and a conductive film on the conductive pattern; Forming a mask on the conductive film; Etching the conductive layer and the dielectric layer using the mask as an etch mask to form a control gate electrode having a first line width and a dielectric layer pattern having a second line width; Forming a spacer on side surfaces of the control gate electrode and the dielectric layer pattern; And Etching the conductive pattern using the control gate electrode, the dielectric layer pattern, and the spacer as an etch mask to form a floating gate having a third line width wider than the first line width and the second line width. Method of manufacturing a memory device. The method of claim 7, further comprising removing the mask after forming the dielectric layer pattern and the control gate electrode. The method of claim 7, further comprising forming a source / drain on the substrate adjacent to the floating gate electrode.

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