KR20090021465A - Producing method of non-silicide - Google Patents

Producing method of non-silicide Download PDF

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KR20090021465A
KR20090021465A KR1020070086002A KR20070086002A KR20090021465A KR 20090021465 A KR20090021465 A KR 20090021465A KR 1020070086002 A KR1020070086002 A KR 1020070086002A KR 20070086002 A KR20070086002 A KR 20070086002A KR 20090021465 A KR20090021465 A KR 20090021465A
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film
sab
oxide film
silicide
gate
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KR1020070086002A
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Korean (ko)
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변동일
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주식회사 동부하이텍
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Publication of KR20090021465A publication Critical patent/KR20090021465A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Abstract

A producing method of non-silicide is provided to minimize the loss of the oxide film and diode leakage fail by using the SAB(saliside blocking) oxide thin film having the selection ratio which is higher than that of the field oxide film. A field oxide film(12) is formed on a semiconductor substrate(10). A gate(18) is formed on the semiconductor substrate in which the field oxide film is formed. The LDD(Lightly Doped Drain) ion is injected into the front side of the semiconductor substrate by using the gate as a mask. A spacer(22) is formed at the lateral side of the gate. A source/drain(24) is formed at the both sides of gate on the semiconductor substrate. The SAB film is evaporated by using the thin film in which the etch selectivity is higher than the field oxide film. The SAB film is formed on the region on which non-silicide is formed by the photograph/etching process. After evaporating the metal with the sputtering, the silicide(28) is formed by the annealing. The nitride film is used as the SAB film.

Description

선택적 난-실리사이드 형성방법{Producing method of non-silicide}Producing method of non-silicide

본 발명은 선택적 난-실리사이드 형성 방법에 관한 것으로서, 상세하게는 반도체 기판에서 선택적 난-실리사이드 형성시 SAB산화막을 식각하는 과정에서 필드 산화막도 부분적으로 식각되어서 필드산화막이 모트영역보다 높이가 낮아져서 발생하는 문제점을 해결하기 위하여, 종래의 SAB 산화막 대신에 필드산화막보다 높은 식각선택도를 가지는 재질의 막을 SAB막으로 사용하여 누설전류를 감소시킬 수 있는 선택적 난-실리사이드 형성방법에 관한 것이다.The present invention relates to a method for forming a selective non-silicide, and in particular, a field oxide film is partially etched in the process of etching an SAB oxide film during the formation of a selective non-silicide in a semiconductor substrate. In order to solve the problem, the present invention relates to a selective non-silicide forming method that can reduce the leakage current by using a film having a higher etching selectivity than the field oxide film as a SAB film instead of the conventional SAB oxide film.

도 1a 내지 도 1h는 종래 기술에 의한 선택적 난-실리사이드 형성방법을 도시한 도면이다.1A to 1H illustrate a method of forming a selective non-silicide according to the prior art.

종래 기술에 의한 선택적 난-실리사이드(non-siliside)를 형성하는 위해서 반도체 기판(10)에 필드 산화막(12)을 형성하여 도 1a와 같은 형상을 만든다. 필드 산화막(12)은 공지의 기술인 LOSOS(local oxidation of silicon) 소자 분리 방법 또는 STI(shallow trench isolation) 소자 분리 방법에 의하여 형성될 수 있다. In order to form a selective non-silicide according to the prior art, a field oxide film 12 is formed on the semiconductor substrate 10 to form a shape as shown in FIG. 1A. The field oxide film 12 may be formed by a known technique of local oxidation of silicon (LOSOS) device isolation or shallow trench isolation (STI) device isolation.

도 1b를 참조하면, 상기 소자분리막(12)이 형성된 웨이퍼의 상면에 산화막(14) 및 폴리실리콘(16)을 순차적으로 증착시킨다. 즉, 게이트 절연막으로 사용되는 산화막(14)을 형성한 후 게이트로 사용될 폴리실리콘(16)을 증착하는 것이다. 다음으로 사진/식각 공정을 진행하여 게이트(18)를 형성한다. 여기서는 포포레지스트를 도포한 후에 게이트가 형성될 부위에 감광막을 페터닝한 후 공지의 식각 방식으로 식각 공정을 진행하여 게이트(18)를 형성한다.Referring to FIG. 1B, the oxide layer 14 and the polysilicon 16 are sequentially deposited on the upper surface of the wafer on which the device isolation layer 12 is formed. That is, after forming the oxide film 14 to be used as the gate insulating film, the polysilicon 16 to be used as the gate is deposited. Next, a photo / etch process is performed to form the gate 18. In this case, after the photoresist is applied, the photoresist is patterned on a portion where the gate is to be formed, and then the etching process is performed by a known etching method to form the gate 18.

도 1c를 참조하면, 반도체 기판상의 게이트(18)를 마스크로 이용하여서 반도체 기판의 전면에 LDD(lightly doped drain) 이온을 주입하여 게이트(18)의 양 측면에 LDD 영역(20)을 형성한다.Referring to FIG. 1C, LDD (lightly doped drain) ions are implanted into the entire surface of the semiconductor substrate using the gate 18 on the semiconductor substrate as a mask to form LDD regions 20 on both sides of the gate 18.

도 1d를 참조하면, 게이트(18)의 양 측면에 스페이서(22)를 형성한다. 이를 위하여 반도체 기판의 전면에 걸쳐서 산화막을 CVD 방법으로 증착시킨 후에, 건식 플라스마 식각에 의해 스페이서(22)를 제외한 산화막을 제거하여 게이트(18)의 측면에 스페이서(22)를 형성한다.Referring to FIG. 1D, spacers 22 are formed on both sides of the gate 18. To this end, after the oxide film is deposited over the entire surface of the semiconductor substrate by the CVD method, the oxide film except for the spacer 22 is removed by dry plasma etching to form the spacer 22 on the side of the gate 18.

도 1e를 참조하면, 다음으로 상기 게이트(18)과 스페이서(22)를 마스크로 사용하여 소스/드레인(24) 형성을 위한 이온주입공정을 진행한다. LDD 형성단계보다는 높은 에너지를 이용하여 이온을 주입한다. 이온주입이 끝나면 어닐링(annealing)을 진행한다.Referring to FIG. 1E, an ion implantation process for forming a source / drain 24 is performed using the gate 18 and the spacer 22 as a mask. The ion is implanted using higher energy than LDD formation step. After ion implantation, annealing is performed.

도 1f를 참조하면,난-실리사이드 영역을 형성하기 위하여 SAB(saliside blocking) 산화막을 증착시키고, 사진/식각공정을 거쳐서 난-실리사이드 영역의 상부의 SAB 산화막(26)만 남게 한다.Referring to FIG. 1F, a SAB (saliside blocking) oxide film is deposited to form an egg silicide region, and only the SAB oxide layer 26 on the egg silicide region is left through a photo / etch process.

도 1g를 참조하면, 실리사이드를 형성될 부분에 실리사이드를 형성하기 위하여 금속을 반도체상에 스퍼터링등의 방법으로 증착시킨 후에 어닐링을 진행하여 실리사이드(28)를 형성한다. 이 때 난-실리사이드 영역은 상부의 SAB 산화막에 의해 실리사이드가 형성되지 않는다.Referring to FIG. 1G, in order to form silicide in a portion where silicide is to be formed, a metal is deposited on a semiconductor by a method such as sputtering, followed by annealing to form silicide 28. At this time, the silicide is not formed in the non-silicide region by the SAB oxide layer on the upper portion.

마지막으로 SAB 산화막을 제거하여 도 1h와 같은 형상이 된다.Finally, the SAB oxide film is removed to have a shape as shown in FIG. 1H.

상기된 공정을 진행하게 되면, SAB 산화막을 증착시킨 후에 난-실리사이드 형성을 위하여 상기된 SAB산화막을 식각하는 과정에서 필드 산화막도 부분적으로 식각되어서, 도 1g의 A부분과 같이 필드산화막이 모트영역(moat area)보다 높이가 낮아질 수 있다. 필드산화막이 모트영역보다 낮아지면, 실리사이드 형성후에 모트영역의 측면에 실리사이드가 형성되어 다이오드 리키지 페일(diode leakage fail) 및 IDDQ(드레인간 정지 전류:drain to drain quiescent current) 페일의 근원이 될 수 있다. When the above-described process is performed, the field oxide film is partially etched in the process of etching the SAB oxide film to form the non-silicide after depositing the SAB oxide film. The height may be lower than the moat area. If the field oxide film is lower than the mote region, silicide may form on the side of the mote region after silicide formation, and may be a source of diode leakage fail and drain to drain quiescent current fail. have.

본 발명은 상기된 문제점을 해결하기 위하여 발명된 것으로서, SAB 산화막의 재질을 필드산화막보다 높은 선택비를 가지는 막질로 바꾸어서 모트영역의 높이가 필드 산화막의 높이보다 낮아지는 현상을 방지할 수 있는 선택적 난-실리사이드 형성방법을 제공함에 그 목적이 있다.The present invention has been invented to solve the above-mentioned problems, and it is possible to change the material of the SAB oxide film into a film having a higher selectivity than the field oxide film so that the height of the mote region is lower than the height of the field oxide film. The object is to provide a method for forming silicide.

본 발명에 의한 선택적 난-실리사이드 형성방법은 반도체 기판위에 필드산화막를 형성하는 단계; 상기 필드산화막이 형성된 반도체 기판위에 게이트를 형성하는 단계; 상기 게이트을 마스크로 이용하여 반도체 기판의 전면에 LDD 이온을 주입하는 단계; 상기 게이트의 측면에 스페이서를 형성하는 단계; 상기 게이트 양측 반도체 기판에 소스/드레인을 형성하고 어닐링하는 단계; 상기 필드산화막보다 식각선택도가 높은 막질을 이용하여 SAB막을 증착시킨후에 사진/식각공정을 거쳐서 난-실리사이드가 형성될 영역의 상부에만 SAB막을 형성하는 단계; 스퍼터링에 의해 금속을 증착시킨 후에 어닐링을 실시하여 상기 SAB막이 형성되지 않은 영역에 실리사이드를 형성하는 단계;를 포함한다.Selective non-silicide forming method according to the present invention comprises the steps of forming a field oxide film on a semiconductor substrate; Forming a gate on the semiconductor substrate on which the field oxide film is formed; Implanting LDD ions into the entire surface of the semiconductor substrate using the gate as a mask; Forming a spacer on a side of the gate; Forming and annealing a source / drain on both of the gate semiconductor substrates; Forming a SAB film only on the region where the non-silicide is to be formed by performing a photo / etch process after depositing an SAB film using a film having a higher etching selectivity than the field oxide film; And depositing a metal by sputtering followed by annealing to form silicide in a region where the SAB film is not formed.

본 발명의 다른 바람직한 특징에 의하면, 상기 SAB막의 재질은 질화막이다.According to another preferred feature of the present invention, the material of the SAB film is a nitride film.

본 발명의 다른 바람직한 특징에 의하면, 상기 질화막을 사용한 SAB막의 식각은 CH2F3 가스를 이용한 건식식각으로 실시한다. According to another preferred feature of the present invention, the etching of the SAB film using the nitride film is performed by dry etching using a CH 2 F 3 gas.

본 발명에 의하여, 기존의 SAB 산화막의 식각시 필드 산화막에서 낮아진 산화막의 단차 때문에 모트영역의 측면에 실리사이드가 형성되어 IDDQ 페일등의 누설전류에 의한 수율 저하 및 소자 성능 저하의 가능성을 보완하기 위하여 SAB 산화막 대신 필드 산화막보다 높은 선택비를 가지는 막질을 사용하여 SAB 식각시 발생 가능한 산화막 손실을 최소화하여, 실리사이드가 정션 이하의 영역에서는 형성되지 않도록 하여 누설 전류의 증가를 예방할 수 있다.According to the present invention, silicide is formed on the side of the mote region due to the step difference of the oxide film lowered in the field oxide film during etching of the conventional SAB oxide film, so that the SAB may be compensated for the possibility of lowering the yield and device performance due to leakage current such as IDDQ fail. By using a film quality having a higher selectivity than the field oxide film instead of the oxide film, an oxide film loss that can occur during SAB etching is minimized, so that silicide is not formed in the region below the junction, thereby preventing an increase in leakage current.

도 2a 내지 도 2c는 본 발명에 의한 선택적 난-실리사이드 형성방법을 도시한 도면이다.2A to 2C are diagrams illustrating a method for forming a selective non-silicide according to the present invention.

이하 예시도면에 의거하여 본 발명의 일실시예에 대한 구성 및 작용을 상세히 설명한다. 다만, 아래의 실시예는 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 충분히 이해할 수 있도록 제공되는 것이지, 본 발명의 범위가 다음에 기술되는 실시예에 의해 한정되는 것은 아니다.Hereinafter, the configuration and operation of an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the following examples are provided to enable those skilled in the art to fully understand the present invention, but the scope of the present invention is not limited by the embodiments described below.

상기된 종래기술 중에서 도 1a 내지 도 1e를 참조한 부분은 본 발명과 동일하므로 이 부분에 대해서는 추가적인 설명을 생략한다. 즉, 상기된 도 1a 내지 도 1e와 동일한 절차를 거쳐서 도 1e와 같은 형상이 되도록 한다.1A to 1E of the above-described prior art are the same as the present invention, and further description will be omitted. That is, through the same procedure as in FIGS. 1A to 1E described above, the shape is the same as that of FIG. 1E.

다음으로 도 2a를 참조하면, 난-실리사이드 영역을 형성하기 위하여 SAB(saiiside blocking)막(100)을 증착시키고, 사진/식각공정을 거쳐서 난-실리사이드 영역의 상부의 SAB막(100)만 남게 한다.Next, referring to FIG. 2A, a SAB (saiiside blocking) film 100 is deposited to form a non-silicide region, and only the SAB film 100 on the non-silicide region is left through a photo / etch process. .

본 발명에서 사용되는 SAB막은 필드산화막(12)과 비교했을 때, 식각 선택비가 높은 막질을 사용하여야 한다. 식각 선택도(etch selectivity)란 동일한 식각조건에서 다른 막보다 하나의 막이 얼마나 빠르게 식각되느지를 나타내는 지표이다. 따라서 필드 산화막보다 식각 선택도가 높은 막질을 SAB 막질로 사용함으로서, 필드산화막은 식각시키지 않고, SAB 막질만 식각할 수 있게 된다. 결국 종래기술에서의 SAB산화막 식각시에 필드산화막도 동시에 식각됨으로 발생하는 상기된 문제점이 본 발명 에서는 발생하지 않게 된다.As the SAB film used in the present invention, when compared to the field oxide film 12, a film quality having a high etching selectivity must be used. Etch selectivity is an index indicating how quickly one layer is etched than another layer under the same etching conditions. Therefore, by using the film having a higher etching selectivity than the field oxide film as the SAB film, only the SAB film can be etched without etching the field oxide film. As a result, the above-described problem caused by etching the field oxide film at the same time during the SAB oxide film etching in the prior art does not occur in the present invention.

본 발명에서는 SAB막질(100)의 재질로는 질화막을 사용하는 것이 바람직하다. 또한 질화막을 SAB막질로 사용할 경우에는 이의 식각은 건식식각을 이용하는 것이 바람직하다. 이 경우에 식각가스는 CH2F3를 사용하는 것이 바람직하다. 식각가스로서 CH2F3를 사용하여 건식식각을 하게 되면, 필드산화막(12)과 질화막을 사용한 SAB막질(100)과의 식각선택도가 차이가 나서 도 2b의 B부분에서 보는 바와 같이 필드산화막(12)이 원래의 높이를 유지하고 있게 된다.In the present invention, it is preferable to use a nitride film as the material of the SAB film quality (100). In addition, when the nitride film is used as the SAB film quality, the etching thereof is preferably dry etching. In this case, it is preferable to use CH 2 F 3 as an etching gas. When dry etching is performed using CH 2 F 3 as an etching gas, the etching selectivity between the field oxide film 12 and the SAB film quality 100 using the nitride film is different, and as shown in part B of FIG. (12) maintains the original height.

이후의 공정은 상기된 종래 기술과 동일하게 된다. 즉 도 2b와 도 2c를 참조하면, 실리사이드를 형성될 부분에 실리사이드를 형성하기 위하여 금속을 반도체상에 스퍼터링등의 방법으로 증착시킨 후에 어닐링을 진행하여 실리사이드(28)를 형성한다. 이후 SAB 산화막을 제거하여 도 2c와 같은 형상이 된다. The subsequent process is the same as the prior art described above. 2B and 2C, the silicide 28 is formed by annealing after depositing a metal on the semiconductor by sputtering or the like to form the silicide in the silicide formation portion. After that, the SAB oxide film is removed to have a shape as shown in FIG. 2C.

결과적으로 도 2c에서 보는 바와 같이, 필드산화막(12)의 높이가 모트영역보다 높게 되어, 모트 영역의 측면에서 실리사이드가 형성되어 발생하는 종래기술의 문제점이 발생하지 않게 된다.As a result, as shown in FIG. 2C, the height of the field oxide film 12 is higher than that of the mote region, so that the problem of the prior art caused by the formation of silicide on the side of the mote region does not occur.

도 1a 내지 도 1h는 종래 기술에 의한 선택적 난-실리사이드 형성방법을 도시한 도면,1a to 1h is a view showing a method for forming a selective non-silicide according to the prior art,

도 2a 내지 도 2c는 본 발명에 의한 선택적 난-실리사이드 형성방법을 도시한 도면이다.2A to 2C are diagrams illustrating a method for forming a selective non-silicide according to the present invention.

<도면의 주요부분에 대한 주요부호의 설명><Description of the major symbols for the main parts of the drawings>

12:필드산화막 18:게이트12: field oxide film 18: gate

22:스페이서 26:SAB 산화막22: spacer 26: SAB oxide film

24:소스/드레인 28:실리사이드24: source / drain 28: silicide

100:필드산화막보다 높은 식각선택도를 가지는 재질의 SAB막100: SAB film of material having higher etching selectivity than field oxide film

Claims (3)

반도체 기판위에 필드산화막를 형성하는 단계;Forming a field oxide film on the semiconductor substrate; 상기 필드산화막이 형성된 반도체 기판위에 게이트를 형성하는 단계;Forming a gate on the semiconductor substrate on which the field oxide film is formed; 상기 게이트을 마스크로 이용하여 반도체 기판의 전면에 LDD 이온을 주입하는 단계;Implanting LDD ions into the entire surface of the semiconductor substrate using the gate as a mask; 상기 게이트의 측면에 스페이서를 형성하는 단계;Forming a spacer on a side of the gate; 상기 게이트 양측 반도체 기판에 소스/드레인을 형성하고 어닐링하는 단계;Forming and annealing a source / drain on both of the gate semiconductor substrates; 상기 필드산화막보다 식각선택도가 높은 막질을 이용하여 SAB막을 증착시킨후에 사진/식각공정을 거쳐서 난-실리사이드가 형성될 영역의 상부에만 SAB막을 형성하는 단계;Forming a SAB film only on the region where the non-silicide is to be formed by performing a photo / etch process after depositing an SAB film using a film having a higher etching selectivity than the field oxide film; 스퍼터링에 의해 금속을 증착시킨 후에 어닐링을 실시하여 상기 SAB막이 형성되지 않은 영역에 실리사이드를 형성하는 단계;를 포함하는 선택적 난-실리사이드 형성방법.And annealing after depositing the metal by sputtering to form silicide in the region where the SAB film is not formed. 제1항에 있어서, 상기 SAB막이 질화막인 것을 특징으로 하는 선택적 난-실리사이드 형성방법.The method of claim 1, wherein the SAB film is a nitride film. 제2항에 있어서, 상기 SAB막의 식각은 CH2F3 가스를 이용한 건식식각으로 실시되는 것을 특징으로 하는 선택적 난-실리사이드 형성방법.The method of claim 2, wherein the SAB film is etched by dry etching using a CH 2 F 3 gas.
KR1020070086002A 2007-08-27 2007-08-27 Producing method of non-silicide KR20090021465A (en)

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