KR20090020826A - Method of manufacturing phase change memory device - Google Patents

Abstract

A manufacturing method of a phase change memory device is provided to prevent the damage of the phase changing film which is vulnerable to a patterning process by omitting the patterning process by forming a phase change film inside a hole. A semiconductor substrate(100) comprises a contact plug(108) formed on a bottom electrode(104). An insulating film including the contact plug is formed in on the semiconductor substrate. A hole is built up in the insulating film and exposes the contact plug. A phase changing film(114) is formed on the contact plug and the insulating film so that the hole inside is filled. Polishing is performed and the phase changing film is left inside the hole. The upper electrode is formed on the top of the phase changing film.

Description

Method of manufacturing phase change memory device

The present invention relates to a method of manufacturing a phase change memory device, and more particularly, to a method of manufacturing a phase change memory device capable of improving electrical characteristics by preventing defects of a phase change material.

Among semiconductor memory devices, nonvolatile memory devices that receive stored data are not lost even when power supply is interrupted. Among the nonvolatile memory devices, a flash memory device may be referred to as a typical device.

The flash memory device includes a charge trap layer, which distinguishes an erase cell or a program cell according to the presence / absence of charges from the charge trap layer, and reads a commonly referred to as "0" or "1". (read) In addition, although the above-described memory device distinguishes only an erase state or a program state, recently, a multi level chip (MLC) type device capable of distinguishing a plurality of program states has been developed.

However, as the degree of integration of semiconductor memory devices increases, such devices increase interference characteristics that may occur between neighboring devices, and it is very difficult to increase the degree of integration due to the limitation of micropatterns.

Accordingly, a phase change memory device has been proposed as a new memory device.

The phase change memory device does not determine the presence / absence of electric charges, but distinguishes the “0” or “1” states by the amount of current passing through the phase change film. Specifically, the phase change film is phase-transformed to a crystalline or amorphous state depending on temperature, thereby changing its physical properties. At this time, when the phase change film is in the crystalline state, the amount of current flowing increases, and in the amorphous state, the amount of current decreases, so that the amount of current can be sensed to distinguish the "0" or "1" state.

The phase change layer may be formed of an alloy thin film called chalcogenide (Ge _x Sb _y Te _z ; hereinafter GST). The chalcogenide (GST) layer is antimony contained in the chalcogenide (GST) layer when patterned. Sb is easily diffused into the surrounding layer, and the physical properties of the phase change film are changed, so that the phase change property is easily reduced. In addition, since the chalcogenide (GST) film is vulnerable to the etching process, cracks or voids are likely to occur during the etching process, which may make it difficult to proceed with subsequent processes. It is easy to wear, and therefore, the electrical characteristics may be degraded.

The problem to be solved by the present invention, after forming the insulating film, to form a hole to form a phase change film in the insulating film, and to form a capping film in the hole to prevent the subsequent diffusion of the phase change film, the phase change film is inside the hole Since the patterning process of the phase change film can be omitted, the damage to the phase change film vulnerable to the patterning process can be prevented, thereby improving the reliability of the device.

The present invention relates to a method of manufacturing a phase change memory device, and a semiconductor substrate having a contact plug formed on a lower electrode is provided. An insulating film is formed on a semiconductor substrate including a contact plug. Holes are formed in the insulating film to expose the contact plugs. A phase change film is formed on the contact plug and the insulating film to fill the inside of the hole. The polishing process is carried out so that the phase change film remains only inside the hole. A method of manufacturing a phase change memory device including forming an upper electrode on an upper portion of a phase change film.

The phase change film is formed of a phase change material that is converted into a crystalline or amorphous state by heat, and the phase change material is formed of GST. GST is a compound of germanium (Ge), antimony (Sb) and tellurium (Te), and GST is Ge ₂ Sb ₂ Te ₅ .

 Prior to forming the phase change film, a capping film is formed along the surface of the hole. And performing an ion implantation process on the capping film. The capping film is formed of a nitride film, and the ion implantation process injects antimony (Sb) as impurities.

The contact plug is formed of a conductive material, and the conductive material is formed of a polysilicon film, a silicon film (epitaxial growth Si), or a tungsten film.

According to the present invention, after forming the insulating film, a hole in which the phase change film is to be formed is formed in the insulating film, and a capping film is formed in the hole to prevent subsequent diffusion of the phase change film, and the patterning process is formed since the phase change film is formed inside the hole. Since it is possible to omit the damage to the phase change film vulnerable to the patterning process.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1A to 1D are cross-sectional views illustrating a method of manufacturing a phase change memory device according to the present invention.

Referring to FIG. 1A, a semiconductor substrate 100 including a lower electrode 104 is provided. Specifically, the first insulating film 102 for the interlayer insulating film is formed on the semiconductor substrate 100, and the first insulating film 102 is patterned to expose the semiconductor substrate 100. After forming the lower electrode 104 by filling a metal film on the exposed semiconductor substrate 100, a chemical mechanical polishing (CMP) process is performed to form an upper portion of the first insulating layer 102 and the lower electrode 104. Planarize. The first insulating film 102 may be formed of an oxide film, and the lower electrode 104 may be formed of a metal film.

Subsequently, a second insulating film 106 for interlayer insulating film is formed on the first insulating film 102 and the lower electrode 104. The second insulating film 106 can be formed of an oxide film. A hard mask pattern (not shown) having an open contact hole 107 region is formed on the second insulating layer 106, and an etching process is performed on the second insulating layer 106 by performing an etching process according to the hard mask pattern (not shown). A contact hole 107 exposing a portion of the lower electrode 104 is formed.

Referring to FIG. 1B, a contact plug 108 is formed in the contact hole 107. The contact plug 108 may be formed of a conductive material as a heating element. For example, a polysilicon film, an epitaxial growth Si, or a tungsten film may be formed of a material for the contact plug 108. Specifically, the conductive material is formed in the contact hole 107, but the second insulating film 106 is preferably covered to completely fill the contact hole 107. The chemical mechanical polishing (CMP) process is performed to expose the upper portion of the second insulating layer 106 so that the contact plug 108 is formed in the contact hole 107. At this time, the hard mask pattern (not shown) formed in FIG. 1A is also removed. As such, the contact plug 108 may be electrically connected to contact the lower electrode 104, and the exothermic temperature of the contact plug 108 is changed by a voltage transferred to the subsequent lower electrode.

Subsequently, a third insulating film 110 for an interlayer insulating film is formed on the second insulating film 106 and the contact plug 108. The third insulating film 110 may be formed of an oxide film. A hard mask pattern (not shown) in which a region where a subsequent phase change film is to be formed is opened is formed on the third insulating layer 110, and an etching process is performed according to the hard mask pattern (not shown) to form the third insulating layer 110. The hole 111 is formed to expose the contact plug 108. The hard mask pattern (not shown) is removed.

Referring to FIG. 1C, the capping layer 112 is formed along the surface of the hole 111 of FIG. 1B to prevent impurity diffusion of the phase change layer 114 to be formed in a subsequent process. The capping film 112 may be formed of a nitride film, and preferably formed in a thickness of 5 nm to 20 nm in consideration of the width of the hole (111 in FIG. 1B). Subsequently, an ion implantation process is performed on the capping film 112 to further prevent diffusion of impurities from the phase change film 114. In the ion implantation process, it is preferable that the impurity uses ions in which diffusion occurs in the phase change film 114. For example, since antimony (Sb) ions mainly diffuse in the phase change film 114, it is preferable to use antimony (Sb) as an impurity in the ion implantation process. In addition, after the ion implantation process, an etch back process, which is a dry etching process, is performed to remove the capping layer 112 formed on the contact plug 108 and formed on the sidewalls of the third insulating layer 110. The capping film 112 may be left.

Next, a phase change film 114 is formed on the capping film 112. Preferably, the phase change film 114 is formed to be filled in the hole (111 of FIG. 1B). Specifically, it is as follows.

The phase change film 114 is formed of a phase change material. The phase change material refers to a material having two stable states, an amorphous state and a crystalline state, which can be converted into any one of these states. In general, the material in the crystalline state has a lower resistivity than the material in the amorphous state. Accordingly, the difference in the amount of current between the phase change material in the crystalline state and the phase change material in the amorphous state may be detected and determined by logic (for example, “0” or “1”). A widely known phase change material is GST (Ge _x Sb _y Te _z , for example Ge ₂ Sb ₂ Te ₅ ), a compound of germanium (Ge), antimony (Sb) and tellurium (Te). Phase change materials such as GST can be converted to crystalline or amorphous states by heat. When the voltage is transmitted through the lower electrode 104, the contact plug 108 generates heat by the resistance in the contact plug 108, thereby changing the state of the phase change film 114.

Referring to FIG. 1D, a planarization process is performed to expose the third insulating layer 110 to remove a portion of the phase change layer 114 and the capping layer 112. The phase change layer 114 is very vulnerable to a wet or dry etching process due to the nature of the phase change material, but as described above, the phase change layer 114 may be formed in an open pattern of the third insulating layer 110. By filling, the patterning process of the phase change film 114 is not performed. As a result, damage to the phase change film 114 can be reduced.

Subsequently, an upper electrode 118 is formed on the phase change film 114. For example, after the fourth insulating film 116 for the interlayer insulating film is formed on the third insulating film 110, the capping film 112, and the phase change film 114, the phase change film 114 is exposed. 4 The insulating film 116 is patterned. The upper electrode 118 may be formed by forming a metal layer on the exposed phase change layer 114.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1D are cross-sectional views illustrating a method of manufacturing a phase change memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 102 first insulating film

104: lower electrode 106: second insulating film

108: contact plug 110: third insulating film

112: capping film 114: phase change film

116: fourth insulating film 118: upper electrode

Claims (10)

Providing a semiconductor substrate having a contact plug formed on the lower electrode; Forming an insulating film on the semiconductor substrate including the contact plug; Forming holes in the insulating layer to expose the contact plugs; Forming a phase change layer on the contact plug and the insulating layer to fill the hole; Performing a polishing process such that a phase change film remains only inside the hole; And And forming an upper electrode on the phase change layer. The method of claim 1, And the phase change film is formed of a phase change material that is converted into a crystalline or amorphous state by heat. The method of claim 2, And the phase change material is formed of GST. The method of claim 3, wherein The GST is a method of manufacturing a phase change memory device is a compound of germanium (Ge), antimony (Sb) and tellurium (Te). The method of claim 3, wherein The GST is Ge ₂ Sb ₂ Te _{5 A} method for manufacturing a phase change memory device. The method of claim 1, wherein before the forming of the phase change film, Forming a capping film along the surface of the hole; And And performing an ion implantation process on the capping layer. The method of claim 6, And the capping layer is formed of a nitride film. The method of claim 6, The ion implantation process is a method of manufacturing a phase change memory device injecting antimony (Sb) as impurities. The method of claim 1, The method of claim 1, wherein the contact plug is formed of a conductive material. The method of claim 9, The conductive material is a polysilicon film, a silicon film (epitaxial growth Si) or a tungsten film manufacturing method of manufacturing a phase change memory device.

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