KR20090016851A - Delay circuit for reset terminal of ic - Google Patents

Delay circuit for reset terminal of ic Download PDF

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Publication number
KR20090016851A
KR20090016851A KR1020070081134A KR20070081134A KR20090016851A KR 20090016851 A KR20090016851 A KR 20090016851A KR 1020070081134 A KR1020070081134 A KR 1020070081134A KR 20070081134 A KR20070081134 A KR 20070081134A KR 20090016851 A KR20090016851 A KR 20090016851A
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KR
South Korea
Prior art keywords
signal
terminal
input voltage
time constant
reset
Prior art date
Application number
KR1020070081134A
Other languages
Korean (ko)
Inventor
이가영
Original Assignee
엘지이노텍 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지이노텍 주식회사 filed Critical 엘지이노텍 주식회사
Priority to KR1020070081134A priority Critical patent/KR20090016851A/en
Publication of KR20090016851A publication Critical patent/KR20090016851A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

A delay circuit for reset terminal of IC including reset terminal for delayed input voltage is provided to reduce error generating rate of an IC(Integrated Circuit) by inputting a signal delaying an input voltage to a reset terminal of the IC. A signal delaying part(100) delays an input voltage during predetermined time. An IC(200) includes a VCC terminal and a reset terminal. The input voltage is inputted to the VCC terminal. An output signal of the signal delaying part is inputted to the reset terminal. The signal delaying part includes a time constant generating part and a comparing part. The time constant generating part generates a signal having rising time of predetermined time from the input voltage, and outputs a generated signal. The comparing part(120) compares a signal outputted in the time constant generating part with a reference voltage. When the signal outputted in the time constant generating part is larger than the reference voltage, the comparing part delays the input voltage during a predetermined time. The time constant generating part includes a resistor and a capacitor. One terminal of the resistor(R1) is connected to the input voltage. One terminal of the capacitor(C) is connected to the other terminal of the resistor. The other terminal of the capacitor is connected to a ground.

Description

IC reset stage delay circuit {Delay circuit for reset terminal of IC}

1 is a view showing a state of a conventional IC.

2 is a view illustrating signal waveforms of a VCC stage and a reset stage in a conventional IC.

3 illustrates a reset stage delay circuit of an IC according to an exemplary embodiment of the present invention.

4 is a view illustrating signal waveforms of a VCC terminal and a reset terminal in an IC according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100 signal delay 200 IC

110 Time constant generator 120 Comparator

R1 first resistor R2 second resistor

C capacitor

The present invention relates to a reset stage delay circuit of an IC.

1 is a view showing a state of a conventional IC.

As shown in FIG. 1, the conventional IC 10 has a structure in which an input voltage Vin is simultaneously applied to a VCC terminal and a reset terminal.

2 is a view illustrating signal waveforms of a VCC stage and a reset stage in a conventional IC.

As shown in FIG. 2, in the conventional IC 10, the input voltage Vin is simultaneously applied to the VCC terminal and the reset terminal. The IC 10 must first operate in the order that the VCC stage is activated, and then the reset stage is activated. When the input voltage is applied to the VCC stage and the reset stage at the same time, an error occurs because the VCC stage and the reset stage are simultaneously activated. However, as shown in FIG. 2, since the input voltage Vin is simultaneously applied to the VCC terminal and the reset terminal in the conventional IC 10, the normal operation is not performed in the IC 10, and an error is likely to occur. There is a problem.

The present invention can reduce the error occurrence rate of the IC.

The present invention includes an IC including a signal delay unit for outputting a signal delaying an input voltage by a predetermined time, a VCC terminal for inputting an input voltage, and a reset terminal for inputting a signal output from the signal delay unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

3 illustrates a reset stage delay circuit of an IC according to an exemplary embodiment of the present invention.

The signal delay unit 100 outputs a signal obtained by delaying the input voltage Vin by a predetermined time.

The IC 200 includes a VCC terminal to which an input voltage Vin is input and a reset terminal to which a signal output from the signal delay unit 100 is input.

In FIG. 3, the signal delay unit 100 outputs a signal having a rising time for a predetermined time when the input voltage Vin is applied, and the time constant generator 110. And a comparator 120 for comparing the signal output from the reference voltage with the reference voltage and outputting a signal of delaying the input voltage Vin by a predetermined time when the output signal becomes greater than or equal to the reference voltage.

The time constant generator 110 includes a first resistor R1 having one side connected to an input voltage, and a capacitor C having one side connected to the other side of the first resistor R1 and the other side connected to the ground. .

Comparator 120 has a non-inverting terminal (+) is connected between the first resistor (R1) and the capacitor (C), a reference voltage is input to the inverting terminal (-), the output terminal is a reset terminal of the IC (200) It can be configured as an op amp connected to.

4 is a view illustrating signal waveforms of a VCC terminal and a reset terminal in the IC 200 according to an exemplary embodiment of the present invention. 4 (a) is a waveform of a signal input to the VCC terminal of the IC, Figure 4 (b) is a waveform of the signal coming out of the municipality generating unit 110, Figure 4 (c) is coming out of the comparator 120 The waveform of the signal.

In the present invention, the input voltage Vin becomes a signal having a rising time of a predetermined value while passing through the time constant generator 110. The signal waveform at this time is shown in Fig. 4B. In the embodiment of FIG. 3, the signal from the time constant generator 110 has a rising time of R1 * C [s].

In FIG. 3, the signal output from the time constant generator 110 is input to the non-inverting terminal (+), and the reference voltage Vref is input to the inverting terminal (−) of the OP amplifier. The OP amplifier compares the signal output from the time constant generator 110 with the reference voltage and outputs a signal obtained by delaying the input voltage Vin by a predetermined time when the output signal becomes equal to or greater than the reference voltage Vref. The signal waveform at this time is shown in Fig. 4C. In the embodiment of FIG. 3, the signal input to the reset terminal of the IC 200 is input by a signal delayed by R1 * C [s] than the signal input to the VCC terminal.

As described above, a signal delayed by a predetermined time is input to the reset terminal of the IC 200 by a signal input to the VCC terminal, and the reset terminal becomes a high state later than the VCC terminal. Therefore, the error rate occurring in the IC 200 can be reduced.

While the invention has been described using some preferred embodiments, these embodiments are illustrative and not restrictive. Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the invention and the scope of the rights set forth in the appended claims.

As described above, according to the present invention, since a signal delayed by a predetermined time is input to the reset terminal of the IC by a signal input to the VCC terminal, the error occurrence rate of the IC can be reduced.

Claims (4)

A signal delay unit for outputting a signal delaying the input voltage by a predetermined time; An IC including a VCC terminal to which an input voltage is input and a reset terminal to which a signal output from the signal delay unit is input Reset stage delay circuit of the IC comprising a. The method of claim 1, The signal delay unit includes a time constant generator for outputting a signal having a rising time for a predetermined time when an input voltage is applied, and compares the signal output from the time constant generator with a reference voltage so that the output signal is equal to or greater than the reference voltage. And a comparator for outputting a signal in which the input voltage is delayed by a predetermined time when the reset voltage is delayed. The method of claim 2, And the time constant generator comprises a first resistor having one side connected to an input voltage, and a capacitor connected at one side to the other side of the first resistor and the other side connected to the ground. The method of claim 3, And the comparator is an op amp in which a non-inverting terminal is connected between the first resistor and a capacitor, a reference voltage is input to the half-shear terminal, and an output terminal is connected to a reset terminal of the IC.
KR1020070081134A 2007-08-13 2007-08-13 Delay circuit for reset terminal of ic KR20090016851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070081134A KR20090016851A (en) 2007-08-13 2007-08-13 Delay circuit for reset terminal of ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070081134A KR20090016851A (en) 2007-08-13 2007-08-13 Delay circuit for reset terminal of ic

Publications (1)

Publication Number Publication Date
KR20090016851A true KR20090016851A (en) 2009-02-18

Family

ID=40685759

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070081134A KR20090016851A (en) 2007-08-13 2007-08-13 Delay circuit for reset terminal of ic

Country Status (1)

Country Link
KR (1) KR20090016851A (en)

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