KR20090016243A - Driving apparatus of plasma display panel - Google Patents

Abstract

A drive apparatus of plasma display panel is provided to express the image gradation in PDP in a high speed by not generating the time required to read the video data in the memory. A driving apparatus of the plasma display panel comprises a memory(306), a timing controller(308) and a data arranger(302). The memory stores the video data for driving the subfield of the plasma display panel to each address electrode. The timing control part generates the strobe signal for applying the address data pulse with the address electrodes of the plasma display panel. The data arranger provides the video data stored in the buffer to the address electrode driver(100), in the number of the address electrode, at the case when the strobe signal is generated in the timing control part. The address electrode driver drives the address electrode of the plasma display panel.

Description

Driving device of plasma display panel {DRIVING APPARATUS OF PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device of a plasma display panel, and more particularly, to a driving device capable of operating a plasma display panel at high speed in order to provide high quality.

Recently, as a flat panel display device, a plasma display panel (hereinafter referred to as 'PDP'), which is easy to manufacture large panels, has been attracting attention. PDP has high brightness and wide viewing angle, so it is widely applicable as a large, thin display such as an outdoor advertising tower, wall-mounted TV, or theater display.

FIG. 1 is a diagram illustrating a general PDP. A PDP is a display device using visible light emitted by irradiating ultraviolet light generated by a discharge of an inert gas enclosed in a discharge cell to a phosphor.

Referring to FIG. 1, the PDP drives an address electrode driver 100 for driving an address electrode X disposed in a vertical direction on a glass substrate, and a scan / hold electrode Y disposed in a horizontal direction on a glass substrate. The scan / hold electrode driver 102 and the common sustain driver 104 for driving the common sustain electrode Z arranged alternately with the scan / hold electrode Y are provided.

The PDP 106 has the scan / hold electrode Y and the common sustain electrode Z alternately arranged with each other, and the address electrode X disposed orthogonal to the scan / hold electrode Y and the common sustain electrode Z. ) Is composed of an M × N pixel matrix.

The address electrode driver 100 is connected to the address electrodes X1, X2, ..., XN-1, XN, and the scan / sustain electrode driver 102 is connected to the M scan / sustain electrodes Y1, Y2 ..., YM. The voltage is selectively supplied to the electrodes to be connected and displayed. The common sustain electrode driver 104 is commonly connected to the M common sustain electrodes Z1, Z2,..., ZM to supply voltages having the same level to all common sustain electrodes.

FIG. 2 is a diagram illustrating a method of implementing a gray scale of a general PDP. As shown in FIG. 2, a frame image display period is divided into a plurality of subfields having different emission counts. The image is divided to implement image gradation.

As an example, one frame is composed of eight subfields. Each subfield is composed of a reset section for uniformly generating a discharge, an address section for selecting a discharge cell, and a sustain section for implementing gradation according to the number of discharges.

First, in each subfield, the reset period is a period for slightly retaining wall charges in the entire cell for stable operation of the cell. To this end, a relatively high front writing voltage pulse is applied between the scan / sustain electrode Y and the common sustain electrode Z to form wall charges in the dielectric layer inside the cell. Subsequently, a sustain voltage, an erase voltage pulse, or the like is applied between the scan / sustain electrode Y and the common sustain electrode Z to cause a plurality of discharges so that uniform wall charge remains in the cell.

Next, the address section in each subfield is a section for accumulating wall charges such that the next sustain discharge is possible for the pixels to be lit in accordance with the address discharge. To this end, an address discharge is generated by an image data pulse applied to the address electrode X of the PDP and a scan pulse applied to the scan / sustain electrode Y so that wall charges are formed inside the cell to be lit.

Finally, the sustain period in each subfield raises a sustain pulse to the wall charge to generate sustain discharge only for cells in which address discharge has occurred. To this end, a sustain voltage pulse applied between the scan / sustain electrode Y and the common sustain electrode Z of the PDP is added to the wall charges formed inside the lit cell in the address section to generate a sustain discharge, thereby causing a relative value of luminance. Will be decided.

The image gray scale implementation of the PDP realigns the data to represent the image processing process for performing the image correction process on the input image data and to divide the frame into several subfields with different number of emission times in order to express the degree of brightness of the image. Requires a course. The data rearranged through the data realignment process is stored in a predetermined memory, and is read from the memory and provided to the PDP address electrodes X1, X2, ..., XN-1, and XN in response to an image data pulse request. Accordingly, in providing the image data pulse to the PDP address electrode in response to the image data pulse request, there is always a certain time delay due to the time for reading the image data from the memory.

On the other hand, the time required for displaying an image of one frame is usually about 16.67ms to 20ms. Assuming 10 subfield driving structures, an operation time given to one subfield is 1.667ms to 2ms. If this time is divided by the number of PDP electrodes, the display time for one electrode is calculated.

Therefore, the lower the resolution of the image, the higher quality performance can be realized by driving a plurality of subfields. However, the higher the resolution, the lower the number of displayable subfields.

Therefore, the problem solving means which concerns on this invention is providing the drive apparatus of the plasma display panel which can operate a plasma display panel at high speed in order to provide high quality.

In order to achieve the above problem solving means, the driving apparatus of the plasma display panel according to the present invention includes a memory for storing the image data for each address electrode for the sub-field driving of the plasma display panel; A timing controller configured to generate a strobe signal for applying an address data pulse to address electrodes of the plasma display panel; And read the image data stored in the memory as much as a preset data size and store the image data in a buffer provided therein, and store the image data stored in the buffer whenever the strobe signal is generated by the timing controller. And a data alignment unit provided to an address electrode driver for driving the address electrodes of the plasma display panel.

The data alignment unit sequentially generates an address electrode number and a subfield number from which an image data is to be read from the memory for sub-drive of the plasma display panel from an initial value, and generates the address electrode number and the subfield number. The mapped image data is read from the memory and stored in the internally provided buffer.

According to the present invention, it is possible to express the image gray level on the PDP at high speed by preventing the time for reading the image data from the memory, which is a time required to provide the image data pulse to the PDP address electrode in response to the image data pulse request. To be.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail. However, in describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

3 is a diagram illustrating a driving apparatus of the plasma display panel according to the present invention, and shows a configuration of a driving apparatus of the plasma display panel which enables the plasma display panel to be operated at high speed.

Looking at the configuration thereof, each of the electrodes of the image processor 300, the data alignment unit 302 including the internal buffer 304, the memory 306, the timing controller 308, and the PDP 106 are driven. The address electrode driver 100, the scan / sustain electrode driver 102, and the common sustain electrode driver 104.

The image processor 300 performs image correction on the input image data.

In addition, the data aligning unit 302 uses the values for each subfield to express the image data corrected by the image processing unit 300 on the PDP 106 according to the subfield driving, which is a screen driving method inherent to the PDP 106. Performs a process of converting the image data.

Here, FIG. 4 illustrates a state in which image data is converted for each subfield so that the image data input from the data aligning unit 302 is represented in accordance with the subfield driving of the PDP 106. Thus, when there are eight subfields, image data having a value of 0 to 255 is converted into a value for each subfield in the form as shown in FIG.

The data alignment unit 302 stores the image data converted into values for each subfield in the memory 306.

The timing controller 308 generates control signals Y_Ctl and Z_Ctl for controlling the driving of the scan / sustain electrode driver 102 and the common sustain electrode driver 104 to operate the PDP 106, while the data alignment unit generates a control signal. In step 302, the address electrode driver 100 generates a control signal for controlling the operation of the data alignment unit 302 to provide image data for each address electrode.

In the conventional configuration, there are three signals that the timing controller 308 provides to the data alignment unit 305 to provide the image data from the data alignment unit 302 to the address electrode driver 100. The first is a signal containing the number of subfields to express the current gray level, the second is a signal containing the address electrode number to be expressed, and the third is a strobe signal indicating the validity of the two signals.

Thus, the existing data aligner 302 receives a signal including the number of the subfield and the address electrode number transmitted together with the strobe signal from the timing controller 308, and among the image data of the corresponding address electrode in the memory 306. Data mapped to the number of the corresponding subfield was read and provided to the address electrode driver 100.

Therefore, providing the image data for each address electrode from the data alignment unit 302 to the address electrode driver 100 is a subfield in which the three signals are received from the timing controller 308 and the image data is read from the memory 306. The subfield image data of the address electrode was read from the memory 306 and provided to the address electrode driver 100 in response thereto.

As a result, how quickly the data alignment unit 302 can provide the image data to the address electrode driver 100 in response to the timing controller 308 is an important factor in enabling the driving of the PDP 106 at high speed. do.

However, in order to provide image data to the address electrode driver 100, the data aligner 302 may use the memory 306 using the information on the address of the subfield and the number of the subfield obtained from the timing controller 308. Since the operation of reading the image data from the memory 306 needs to be performed, a method for reducing the time taken to read the image data from the memory 306 needs to be sought.

In the conventionally sought solutions, the memory bandwidth is increased by increasing the memory speed or increasing the number of memories. Of course, this could shorten the image data providing time of the data alignment unit 302. However, this inevitably leads to parts increase and manufacturing difficulties, resulting in an increase in price and an increase in defective rate.

Therefore, the timing controller 308 and the data aligner 302 may be provided so that the data aligner 302 may provide the image data to the address electrode driver 100 more quickly in response to the timing controller 308 without the difficulty described above. It is a technical feature which the drive apparatus of the plasma display panel which concerns on this invention has.

Conventionally, since the data aligning unit 302 receives a signal including a subfield number and an address electrode number from the timing controller 308, a sequential process is required, until a single image data reading process is completed. The next reading process cannot begin.

According to the present invention, the data alignment unit 302 has an internal buffer 304 of a predetermined size. The data aligning unit 302 does not read the image data from the memory 306 through the received information after receiving the signal containing the subfield number and the address electrode number from the timing controller 308. The image data for each address electrode to be provided to the address electrode driver 100 by itself is read from the memory 306 and prestored in the buffer 304 provided therein.

Accordingly, the data aligning unit 302 generates the information on the subfield number and the address electrode number previously provided by the timing controller 308 by itself and uses the generated subfield number and the address electrode number to store the memory ( The subfield image data for several address electrodes is read in advance from 306 and stored in the internal buffer 304. Whenever the strobe signal is input from the timing controller 308, the corresponding subfield image data is sequentially provided to the address electrode driver 100 for each address electrode in the internal buffer 304.

Here, when the data alignment unit 302 generates information on the subfield number and the address electrode number in order to read the image data from the memory 306, first, the data alignment unit 302 initializes the subfield number and the address electrode number. The address electrode number is increased by one from the initial value, and image data corresponding thereto is read from the memory 306. Then, when the address electrode number exceeds the last address electrode number provided in the PDP, the subfield number is increased by one and the address is increased. Reset the electrode number again.

The data aligning unit 302 repeats the above process to generate a subfield number and an address electrode number to read image data from the memory 306. If the subfield number exceeds the last subfield number, the subfield number is again generated. And the value of the address electrode number are initialized.

Accordingly, as described above, the data alignment unit 302 sequentially reads image data stored in the memory 306 in advance in the order of the address electrode number and the subfield number without the help of the timing controller 308. It can be stored in the buffer (304). Therefore, the data aligning unit 302 stores the image data in the internal buffer 304 as described above, and whenever the strobe signal is input from the timing control unit 308, the internal buffer 304 immediately without time delay. The image data stored in the order of the address electrode number and the sub field number are sequentially provided to the address electrode driver 100.

According to the present invention, the data alignment unit 302 has image data to be provided to the address electrode driver 100 before the strobe signal of the timing controller 308 is input. It is provided to the drive unit 100. Therefore, the time required to drive one subfield in the PDP 106 is shortened, thereby enabling more subfields to be driven than before.

Such a driving device configuration of the plasma display panel according to the present invention does not cause component increase and manufacturing difficulties, and enables the plasma display panel to be driven at high speed.

Although the present invention has been described in detail with reference to exemplary embodiments above, those skilled in the art to which the present invention pertains can make various modifications to the above-described embodiments without departing from the scope of the present invention. I will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.

1 is a view illustrating a general PDP;

2 is a diagram illustrating a method for implementing gray scale of a general PDP;

3 is a view showing a driving device of a plasma display panel according to the present invention; and

4 is a diagram illustrating a state in which image data is converted for each subfield.

* Explanation of symbols on the main parts of the drawing

100: address electrode driver 102: scan / sustain electrode driver

104: common sustain electrode driver 106: plasma display panel

300: image processing unit 302: data alignment unit

304: Internal buffer 306: Memory

308; Timing control

Claims (2)

A memory for storing image data for driving a subfield of the plasma display panel for each address electrode; A timing controller configured to generate a strobe signal for applying an address data pulse to address electrodes of the plasma display panel; And The image data stored in the memory is read as much as a preset data size and stored in a buffer provided therein, and whenever the strobe signal is generated by the timing controller, the image data stored in the buffer is stored in order of the number of the address electrodes. And a data alignment unit provided to an address electrode driver for driving the address electrode of the plasma display panel. According to claim 1, The data sorting unit, Address electrode numbers and subfield numbers for reading image data from the memory are sequentially generated from initial values for sub-drive of the plasma display panel, and the image data mapped to the generated address electrode numbers and subfield numbers are stored in the memory. The apparatus of claim 1, wherein the plasma display panel is stored in the internally provided buffer.

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