KR20090015403A - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device is provided to prevent the distortion of common voltage which may be caused by the data voltage supplied to data lines by arranging common lines and the data lines so that they cannot be crossed, thereby improving the image quality. A liquid crystal display device comprises the followings: the first pixel region column(PX1) which includes a plurality of the first pixel regions(P1) and is arranged in the first direction; the second pixel region column(PX2) which includes a plurality of second pixel regions(P2) and is arranged in the first direction; a plurality of gate lines which are arranged in the second direction between adjacent pixel regions within each pixel region column; the first data line(23) which is arranged in the first direction at one side of the first pixel region column; the second data line(25) which is arranged in the first direction at one side of the second pixel region column; and a common line which is arranged in the first direction between the other sides of each pixel region column.

Description

Liquid crystal display device

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality.

As the information society develops, the demand for display devices is increasing in various forms. In response, various flat panel display devices including liquid crystal display devices, plasma display panels, and electro-luminescent display devices have been studied. It is widely used.

Among these, the liquid crystal display device is currently excellent in image quality and has advantages such as light weight, thinness, and low power consumption, thereby rapidly replacing CRTs. BACKGROUND OF THE INVENTION Liquid crystal display devices have been developed in various ways such as laptop monitors, television display panels, and the like.

In the conventional liquid crystal display, as shown in FIG. 1, a plurality of gate lines 101 and a plurality of data lines 103 intersect with each other, and a thin film transistor 107 is disposed at an intersection thereof, such a thin film transistor. The pixel electrode 109 is disposed at 107. A pixel region P may be defined by the intersection of each gate line 101 and each data line 103, and a thin film transistor 107 and a pixel electrode 109 may be disposed in each pixel region P. FIG.

In addition, a common line 105 is disposed parallel to each gate line 101 and across each pixel electrode 109. Accordingly, the common line 105 is disposed to cross each data line 103.

As the common line 105 and each pixel electrode 109 overlap each other to form a storage capacitor, the data voltage applied to the pixel electrode 109 is maintained for one frame. The common voltage is applied to a common electrode (not shown) via the common line 105.

The gate signal is applied to the gate line 101, and the thin film transistor 107 is turned on by the gate signal. The data voltage is applied to the data line 103 and is applied to the pixel electrode 109 via the turned on thin film transistor 107.

Therefore, an electric field is generated by the data voltage applied to the pixel electrode 109 and the common voltage applied to the common electrode, and the arrangement of the liquid crystal molecules is controlled by the electric field to display an image.

However, in the conventional liquid crystal display device, since the common line is disposed to cross each data line, the common voltage applied to the common line is affected by the data voltage applied to each data line. have. This problem is particularly aggravated in areas where data lines and common lines intersect.

That is, the data line is periodically supplied with the positive data voltage and the negative data voltage, and the common voltage supplied to the common line is affected by the data voltage which is periodically converted and supplied in this manner to generate ripples. The ripple prevents the common voltage from being maintained at the desired voltage, resulting in a problem of deterioration in image quality.

It is an object of the present invention to provide a liquid crystal display device which can improve image quality by arranging common lines not to intersect with data lines.

Another object of the present invention is to provide a liquid crystal display device capable of improving image quality by sharing a common line in common to adjacent pixel areas.

According to a first embodiment of the present invention for achieving the above object, a liquid crystal display device comprises: a first pixel region column including a plurality of first pixel regions and disposed along a first direction; A second pixel region column including a plurality of second pixel regions and disposed along the first direction; A plurality of gate lines disposed along a second direction between adjacent pixel regions in each of the pixel region columns; First data lines disposed along one side of the first pixel area column in the first direction; A second data line disposed along one side of the second pixel area column in the first direction; And a common line disposed along the first direction between the other sides of each pixel region column.

According to a second embodiment of the present invention, a liquid crystal display includes: a first pixel region row including a plurality of first pixel regions and disposed along a first direction; A second pixel area row including a plurality of second pixel areas and disposed along the first direction; A first gate line disposed along one side of the first pixel area row in the first direction; A second gate line disposed along one side of the second pixel area row in the first direction; A plurality of data lines disposed along a second direction between adjacent pixel regions in each of the pixel region rows; And a common line disposed along the first direction between the other sides of each pixel region column.

As described above, according to the present invention, the common line may be formed not to cross the data line, thereby improving image quality.

According to the present invention, the first and second common electrodes for supplying the common voltage from one common line to the first and second pixel regions are formed, and for the first and second pixel regions overlapping one common line. By forming the first and second storage capacitors, the image quality can be improved by minimizing the influence of the common voltage by the data voltage.

According to the present invention, an aperture ratio may be improved by arranging one common line between adjacent pixel region columns or pixel region rows.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a diagram schematically illustrating a liquid crystal display according to a first embodiment of the present invention.

Referring to FIG. 2, a plurality of gate lines 1 are disposed, and a plurality of data lines 23 and 25 are disposed to cross each gate line 1. The pixel regions P1 and P2 are defined by each gate line 1 and each data line 23 and 25. For convenience of description, the plurality of pixel areas P1 and P2 defined along the length direction of each data line 23 and 25 will be referred to as pixel area columns PX1 and PX2. Therefore, a plurality of pixel region columns PX1 and PX2 may be defined along the length direction of the data lines 23 and 25.

For example, the first data line 23 is disposed along the length direction of the first pixel region column PX1 on the left side of the first pixel region column PX1, and the second data line 25 is arranged in the second pixel region column. It is disposed along the longitudinal direction of the second pixel region column PX2 on the right side of PX2.

The common line 27 is disposed along each length direction of the first pixel region column PX1 or the second pixel region column PX2 between the first pixel region column PX1 and the second pixel region column PX2. .

Although not shown, a common line may be arranged between the third and fourth pixel region columns. In this case, a third data line may be disposed on the left side of the third pixel region column, and a fourth data line may be disposed on the right side of the fourth pixel region column.

Accordingly, second and third data lines may be disposed between the second and third pixel region columns.

Since the common line 27 is disposed along the length direction of each of the pixel region columns PX1 and PX2, the common line 27 may be disposed in parallel with each of the data lines 23 and 25. Accordingly, the common line 27 may be disposed not to intersect the data lines 23 and 25. Therefore, the data lines 23 and 25 and the common line 27 are disposed to be spaced apart from each other by the pixel region columns PX1 and PX2, and therefore, the common lines may be formed by any data voltage applied to each of the data lines 23 and 25. Since the common voltage applied to (27) is not affected, the common voltage applied to the common line 27 can maintain a desired voltage as it is, and thus the image quality can be improved.

In the pixel areas P1 and P2, the thin film transistors 19 and 21 connected to the gate lines 1 and the data lines 23 and 25, and the pixel electrodes connected to the thin film transistors 19 and 21, respectively. 31 and 33 may be disposed.

Hereinafter, the present invention will be described based on the IPS mode for the convenience of description, but the present invention can be applied to any mode including the TN mode, the VA mode, etc. as well as the IPS mode.

3 is a plan view illustrating an IPS mode liquid crystal display device according to a first embodiment of the present invention, and FIG. 4 is a cross-sectional view illustrating the IPS mode liquid crystal display device of FIG. 3. 3 and 4 are diagrams illustrating that a common line is formed together with a data line. In addition, the common line may be formed together with the gate line, which will be described later. 3 and 4, not only the structure of the IPS mode liquid crystal display but also a manufacturing method will be described.

2 to 4, a gate is formed by depositing and patterning a first metal material on a substrate 3 to form a plurality of gate lines 1 along a first direction and extending to each gate line 1. Electrodes 5 and 7 are formed. The gate electrodes 5 and 7 are components for forming the thin film transistors 19 and 21. When the thin film transistors 19 and 21 are directly formed on the gate line 1, the gate electrodes 5 and 7 are formed. May not be formed.

The gate insulating layer 9 is formed by depositing a first insulating material on the entire surface of the substrate 3 including the gate lines 1. The first insulating material may be an organic insulating material or an inorganic insulating material.

A semiconductor layer 11 and 13 including an active layer and an ohmic contact layer is formed by continuously depositing and patterning a silicon material and a silicon material doped with impurities on the substrate 3 including the gate insulating layer 9. Form.

Depositing and patterning a second metal material on the substrate 3 including the semiconductor layers 11 and 13 to the left of the first pixel region column PX1 for every two pixel region columns PX1 and PX2. The first data line 23 is formed, and the second data line 25 is formed to the right of the second pixel region column PX2, and the common line between the first and second pixel region columns PX1 and PX2 is formed. 27). In this manner, a plurality of data lines 23 and 25 and a plurality of common lines 27 may be formed. Each of the data lines 23 and 25 and each of the common lines 27 may be formed in a second direction to intersect the gate lines 1.

In addition, source electrodes 15a and 17a extend from the respective data lines 23 and 25, and drain electrodes 15b and 17b are formed to be spaced apart from the source electrodes 15a and 17a.

Accordingly, since each common line 27 is formed to be parallel to each data line 23 and 25, each common line 27 does not intersect any data lines 23 and 25, and thus each common line 27. Since the common voltage applied to) is not affected by the data voltages applied to each of the data lines 23 and 25, the image quality may be improved.

In this case, each of the data lines 23 and 25 may be bent so as not to overlap the pixel electrodes 31 and 33 and the common electrodes 35 and 37 to be bent later. As described above, the pixel electrodes 31 and 33 and the common electrodes 35 and 37 are bent and formed to facilitate the control of the liquid crystal, thereby improving the response speed of the liquid crystal.

The thin film transistors 19 and 21 may be formed by the gate electrodes 5 and 7, the semiconductor layers 11 and 13, and the source / drain electrodes 15a, 17a, 15b, and 17b.

The drain contact hole 32 and the common line 27 patterned to deposit a second insulating material on the substrate 3 including the data lines 23 and 25 and to expose the drain electrodes 15b and 17b. ) To form a protective layer 29 including a common line contact hole 36 is patterned to expose. The second insulating material may be an organic insulating material or an inorganic insulating material.

A transparent conductive material is deposited and patterned on the substrate 3 including the protective layer 29 to form the pixel electrodes 31 and 33 and the common electrodes 35 and 37. The pixel electrodes 31 and 33 are electrically connected to the drain electrodes 15b and 17b through the drain contact hole 32, and the common electrodes 35 and 37 connect the common line contact hole 36. It may be electrically connected to the common line 27 through.

When the first and second pixel regions P1 and P2 are defined, the first pixel electrode 31 is formed in the first pixel region P1, and the second pixel electrode 33 is formed in the second pixel region P2. ) Is formed. In addition, a first common electrode 35 is formed in the first pixel region P1, and a second common electrode 37 is formed in the second pixel region P2. The first and second common electrodes 35 and 37 may be integrally formed. That is, the first and second common electrodes 35 and 37 may be formed in the first and second pixel regions P1 and P2 as well as integrally formed in the common line contact hole 36. Therefore, the common voltage supplied to the common line 27 is applied to the first common electrode 35 formed in the first pixel region P1 and the second common electrode 37 formed in the second pixel region P2. Can be applied at the same time.

Meanwhile, a plurality of first pixel electrode bars 31a extending from the first pixel electrode 31 are formed in the first pixel region P1 and a plurality of second pixel electrodes extending from the second pixel electrode 33. Bars 33a are formed in the second pixel region P2. Each of the pixel electrode bars 31a and 33a may be formed to be parallel to the data lines 23 and 25 and the common line 27.

A plurality of first common electrode bars 35a extending from the first common electrode 35 are formed to be alternately parallel to the first pixel electrode bars 31a and alternately parallel to the second pixel electrode bars 33a. A plurality of second common electrode bars 37a extending from the second common electrode 37 may be formed.

One pixel electrode bar of the first pixel electrode bars 31a is formed to partially overlap the common line 27 to form a first storage capacitor Cst1 for the first pixel region P1. do. In addition, one pixel electrode bar of the second pixel electrode bars 33a may be partially overlapped along the common line 27 to form a second storage capacitor Cst2 for the second pixel region P2. Form.

As such, by forming the storage capacitors Cst1 and Cst2 for the two pixel regions P1 and P2 in one common line 27, it is conventional to form the storage capacitor in the common line provided for each pixel region. In comparison, the occupancy area of the storage capacitor can be reduced, and the aperture ratio can be improved.

As described above, the present invention arranges the common line 27 so as not to intersect the data lines 23 and 25, thereby causing signal distortion due to coupling between the common line 27 and the data lines 23 and 25. The image quality can be improved by removing the.

In addition, the present invention can be easily manufactured by forming the common line 27 and the same material as the data lines 23 and 25 at the same time.

In addition, the present invention can form two storage capacitors for the adjacent pixel areas P1 and P2 from one common line 27, so that the aperture ratio can be improved.

FIG. 5 is an enlarged plan view of an 'X region' in FIG. 3, and FIG. 6 is an enlarged cross-sectional view of an 'X region'. 5 and 6 illustrate that a common line is formed together with a gate line. Since other regions except for 'X region' are the same as those of FIGS. 3 and 4, the 'X region' will be described below.

2, 5, and 6, a gate line 1 is formed on a substrate 3 along a first direction, and the gate line 1 is formed in a second direction at an intersection area of the gate line 1. The first common line 27a and the second common line 27b are formed to be spaced apart from each other. The gate line 1 and the first and second common lines 27a and 27b may be simultaneously formed of the same material. Therefore, since the first and second common lines 27a and 27b are formed on the same layer as the gate line 1, the first and second common lines 27a and 27b are electrically insulated from the gate line 1. First and second common lines 27a and 27b may be formed to be spaced apart from the gate line 1 so as to be spaced apart from each other.

A gate insulating layer 9 is formed on the substrate 3 including the first and second common lines 27a and 27b, and a portion of the first and second common lines 27a and 27b is formed. First and second common line contact holes 41 and 43 are formed to be exposed.

Using the same material as the data lines 23 and 25, the first common line contact hole 41 is electrically connected to the first common line 27a and the second common line contact hole 43 is connected to the second material. The connection electrode 39 is formed to be electrically connected to the common line 27b.

Accordingly, the first and second common lines 27a and 27b may be electrically insulated from the gate line 1 and electrically connected to each other by the connection electrode 39. Therefore, the common voltage supplied to the first common line 27a may be applied to the second common line 27b via the connection electrode 39.

7 is a schematic view of a liquid crystal display according to a second embodiment of the present invention.

Referring to FIG. 7, a plurality of gate lines 51 and 53 are disposed, and a plurality of data lines 77 are disposed to intersect the gate lines 51 and 53. The pixel regions P1 and P2 are defined by the gate lines 51 and 53 and the data lines 77. For convenience of description, the plurality of pixel areas P1 and P2 defined along the length direction of each gate line 51 and 53 will be referred to as pixel area rows PY1 and PY2. Accordingly, a plurality of pixel region rows PY1 and PY2 may be defined along the length direction of the gate lines 51 and 53.

For example, the first gate line 51 is disposed along the length direction of the first pixel region row PY1 above the first pixel region row PY1, and the second gate line 53 is the second pixel region row. It is disposed below (PY2) along the longitudinal direction of the second pixel region row PX2.

The common line 55 is disposed along each length direction of the first pixel region row PY1 or the second pixel region row PY2 between the first pixel region row PY1 and the second pixel region row PY2. .

Although not shown, a common line may be disposed between the third and fourth pixel region rows. In this case, a third gate line may be disposed above the third pixel region row, and a fourth gate line may be disposed below the fourth pixel region row.

Accordingly, second and third gate lines may be disposed between the second and third pixel region rows.

Since the common line 55 is disposed along the length direction of each of the pixel region rows PY1 and PY2, the common line 55 may be disposed parallel to the gate lines 51 and 53.

The common line 55 is disposed in parallel with the gate lines 51 and 53, but intersects with the data line 77. Accordingly, the common voltage supplied to the common line 55 may still be affected by the data voltage supplied to the data line 77.

However, in the present invention, although not shown in FIG. 7 (to be described in detail later), the common voltage is distributed to the first and second common electrodes connected to one common line 55, and one common line 55 is divided. By forming the first and second storage capacitors for the shared first and second pixel regions P1 and P2, the influence of the common voltage by the data voltage supplied to the data line 77 may be minimized.

In the pixel areas P1 and P2, the thin film transistors 73 and 75 connected to the gate lines 51 and 53 and the data lines 77, and the pixel electrodes connected to the thin film transistors 73 and 75. 81 and 83 may be disposed.

Hereinafter, the present invention will be described based on the IPS mode for the convenience of description, but the present invention can be applied to any mode including the TN mode, the VA mode, etc. as well as the IPS mode.

8 is a plan view illustrating an IPS mode liquid crystal display device according to a second exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view illustrating the IPS mode liquid crystal display device of FIG. 8. 8 and 9 illustrate that a common line is formed together with a gate line. In addition, the common line may be formed together with the data line, which will be described later. 8 and 9 will be described together with the manufacturing method as well as the structure of the IPS mode liquid crystal display.

7 to 9, a first metal material is deposited and patterned on the substrate 57 to form a plurality of gate lines 51 and 53 along the first direction, and each gate line 51 and 53. A plurality of common lines 55 are formed in parallel to each other, and gate electrodes 59 and 61 extending to the respective gate lines 51 and 53 are formed. The gate electrodes 59 and 61 are components for forming the thin film transistors 73 and 75, and when the thin film transistors 73 and 75 are directly formed on the gate lines 51 and 53, the gate electrodes 59 and 61 are formed. 61 may not be formed.

Each common line 55 forms a first gate line 51 above the first pixel region row PY1 for each of the two pixel region rows PY1 and PY2 and a lower side of the second pixel region row PY2. The second gate line 53 is formed, and the common line 55 is formed between the first and second pixel region rows PY1 and PY2. In this manner, a plurality of gate lines 51 and 53 and a plurality of common lines 55 may be formed.

The first insulating material is deposited on the entire surface of the substrate 57 including the gate lines 51 and 53 to form the gate insulating layer 63. The first insulating material may be an organic insulating material or an inorganic insulating material.

The semiconductor layers 65 and 67 including the active layer and the ohmic contact layer are successively deposited and patterned on the substrate 57 including the gate insulating layer 63 and silicon material doped with impurities. Form.

Depositing and patterning a second metal material on the substrate 57 including the semiconductor layers 65 and 67 to form a plurality of data lines along a second direction crossing the gate lines 51 and 53. 77).

In addition, source electrodes 69a and 71a are formed to extend from the data lines 77, and drain electrodes 69b and 71b are formed to be spaced apart from the source electrodes 69a and 71a.

In this case, each data line 77 may be formed to be bent so as not to overlap the pixel electrodes 81 and 83 and the common electrodes 85 and 87 to be bent later. As such, the pixel electrodes 81 and 83 and the common electrodes 85 and 87 are bent and formed to facilitate the control of the liquid crystal, thereby improving the response speed of the liquid crystal.

The thin film transistors 73 and 75 may be formed by the gate electrodes 59 and 61, the semiconductor layers 65 and 67, and the source / drain electrodes 69a, 71a, 69b and 71b.

A drain contact hole 82 and the common line 55 patterned to deposit a second insulating material on the substrate 57 including each data line 77 and expose the drain electrodes 69b and 71b are formed. A protective layer 79 including a common line contact hole 86 patterned to be exposed is formed. The second insulating material may be an organic insulating material or an inorganic insulating material.

A transparent conductive material is deposited and patterned on the substrate 57 including the protective layer 79 to form pixel electrodes 81 and 83 and common electrodes 85 and 87. The pixel electrodes 81 and 83 are electrically connected to the drain electrodes 69b and 71b through the drain contact hole 82, and the common electrode 55 is connected through the common line contact hole 86. The common line 55 may be electrically connected to the common line 55.

When the first and second pixel regions P1 and P2 are defined, the first pixel electrode 81 is formed in the first pixel region P1, and the second pixel electrode 83 is formed in the second pixel region P2. ) Is formed. In addition, a first common electrode 85 is formed in the first pixel region P1, and a second common electrode 87 is formed in the second pixel region P2. The first and second common electrodes 85 and 87 may be integrally formed. That is, the first and second common electrodes 85 and 87 may be formed in the first and second pixel regions P1 and P2 as well as integrally formed in the common line contact hole 86. Accordingly, the common voltage supplied to the common line 55 is applied to the first common electrode 85 formed in the first pixel region P1 and the second common electrode 87 formed in the second pixel region P2. Can be applied at the same time.

Meanwhile, a plurality of first pixel electrode bars 81a extending from the first pixel electrode 81 are formed in the first pixel region P1 and a plurality of second pixel electrodes extending from the second pixel electrode 83. Bars 83a are formed in the second pixel region P2. Each of the pixel electrode bars 81a and 83a may be formed to be parallel to the data lines 77 and the common line 55.

A plurality of first common electrode bars 85a extending from the first common electrode 85 are formed to be alternately parallel to the first pixel electrode bars 81a and alternately parallel to the second pixel electrode bars 83a. A plurality of second common electrode bars 87a extending from the second common electrode 87 may be formed.

The first capacitor electrode 81b is formed to extend from one of the first pixel electrode bars 81a and partially overlap the common line 55. Therefore, the first storage capacitor Cst1 for the first pixel region P1 is formed by the common line 55 and the first capacitor electrode 81b.

A second capacitor electrode 83b is formed to extend from one of the second pixel electrode bars 83a and partially overlap the common line 55. Accordingly, the second storage capacitor Cst2 for the second pixel region P2 is formed by the common line 55 and the second capacitor electrode 83b.

As described above, by forming the storage capacitors Cst1 and Cst2 for the two pixel regions P1 and P2 in one common line 55, it is conventional to form the storage capacitor in the common line provided for each pixel region. In comparison, the occupancy area of the storage capacitor can be reduced, and the aperture ratio can be improved.

In addition, a common voltage is applied to the first common electrode 85 for the first pixel region P1 and the second common electrode 87 for the second pixel region P2 electrically connected to one common line 55. The first storage capacitor Cst1 for the first pixel region P1 and the second storage capacitor Cst2 for the second pixel region P2 sharing one common line 55. By forming, the influence of the common voltage by the data voltage supplied to the data line 77 can be minimized. In other words, even though the common voltage is affected by the data voltage, the common voltage is applied to the first and second pixel areas P1 and P2, thereby minimizing the influence of the data voltage, thereby improving image quality.

In addition, according to the present invention, the common line 55 may be simultaneously formed of the same material as the gate lines 51 and 53, thereby facilitating manufacture.

In addition, the present invention can form two storage capacitors Cst1 and Cst2 for the adjacent pixel areas P1 and P2 from one common line 55, so that the aperture ratio can be improved.

FIG. 10 is an enlarged plan view of the 'Y region' in FIG. 8, and FIG. 11 is an enlarged cross-sectional view of the 'Y region'. 10 and 11 illustrate a common line formed with a data line. Since other regions except for 'Y region' are the same as those of FIGS. 8 and 9, the 'Y region' will be described below.

7, 10, and 11, the gate lines 51 and 53 are formed on the substrate 57 along the first direction, and the connection electrode 95 is formed in the Y region. The gate lines 51 and 53 and the connection electrode 95 may be simultaneously formed of the same material.

The gate insulating layer 63 is formed on the substrate 57 including the gate lines 51 and 53, and the first and second common line contact holes are exposed so that partial regions of both ends of the connection electrode 95 are exposed. (91, 93) are formed.

The first common line 55a and the second common line contact hole 93 electrically connected to the connection electrode 95 through the first common line contact hole 91 using the same material as the data line 77. The second common line 55b is formed to be electrically connected to the connection electrode 95 through the? The data line 77 and the first and second common lines 55a and 55b may be formed of the same material on the same layer. The first and second common lines 55a and 55b may be formed to be parallel to the gate lines 51 and 53. The first and second common lines 551 and 55b are formed on the same layer as the data line 77 and are spaced apart from the data line 77 for electrical insulation. The first and second common lines 55a and 55b may be electrically connected to each other by a connection electrode 95 formed on the same layer as the gate lines 51 and 53. Therefore, the common voltage supplied to the first common line 55a may be applied to the second common line 55b via the connection electrode 95.

1 is a view schematically showing a conventional liquid crystal display device.

2 is a schematic view of a liquid crystal display according to a first embodiment of the present invention.

3 is a plan view showing an IPS mode liquid crystal display device according to a first embodiment of the present invention;

4 is a cross-sectional view of the IPS mode liquid crystal display of FIG. 3.

FIG. 5 is an enlarged plan view of the area 'X' in FIG. 3. FIG.

6 is an enlarged cross-sectional view of a region 'X'.

7 is a schematic view of a liquid crystal display according to a second embodiment of the present invention.

8 is a plan view showing an IPS mode liquid crystal display device according to a second embodiment of the present invention;

FIG. 9 is a sectional view of the IPS mode liquid crystal display of FIG. 8; FIG.

FIG. 10 is an enlarged plan view of the region 'Y' in FIG. 8. FIG.

11 is an enlarged cross-sectional view of a 'Y area'.

<Explanation of symbols for the main parts of the drawings>

1, 51, 53: gate line 3, 57: substrate

5, 7, 59, 61: gate electrode 9, 63: gate insulating layer

11, 13, 65, 67: semiconductor layers 15a, 17a, 69a, 71a: source electrode

15b, 17b69b, 71b: drain electrodes 19, 21, 73, 75: thin film transistor

23, 25, 77: data line 27, 27a, 27b, 55: common line

29, 79: protective layers 31, 33, 81, 83: pixel electrodes

31a, 33a, 81a, 83a: pixel electrode bars

35, 37, 85, 87: common electrode 35a, 37a, 85a, 87a: common electrode bars

39, 95: connection electrode P1, P2: pixel area

PX1, PX2: pixel region columns PY1, PY2: pixel region rows

Claims (13)

A first pixel region column including a plurality of first pixel regions and disposed along a first direction; A second pixel region column including a plurality of second pixel regions and disposed along the first direction; A plurality of gate lines disposed along a second direction between adjacent pixel regions in each of the pixel region columns; First data lines disposed along one side of the first pixel area column in the first direction; A second data line disposed along one side of the second pixel area column in the first direction; And And a common line disposed along the first direction between the other sides of the pixel region columns. The semiconductor device of claim 1, further comprising: thin film transistors connected to the data lines and the gate lines; Pixel electrodes connected to the thin film transistors; A plurality of pixel electrode bars extending from the pixel electrodes; First and second common electrodes electrically connected to the common line; First common electrode bars extending from the first common electrode and alternately arranged with the pixel electrode bars disposed in the first pixel area; And And second common electrode bars extending from the second common electrode and alternately arranged with the pixel electrode bars arranged in the second pixel area. The liquid crystal display of claim 2, wherein the first and second common electrodes are integrally formed. The liquid crystal of claim 2, wherein the common line is disposed to overlap at least one pixel electrode bar disposed in each of the first pixel areas, and at least one pixel electrode bar disposed in each of the second pixel areas. Display. The liquid crystal display of claim 1, wherein the common line is formed on the same layer as the same material as each of the data lines. The liquid crystal display of claim 1, wherein the common line is formed on the same layer as the gate line. The method of claim 6, wherein in the region where the common line and the gate line cross each other, First and second common lines spaced apart from the gate lines; And And a connection electrode disposed on the same layer as each of the data lines and electrically connected to the first and second common lines. A first pixel region row including a plurality of first pixel regions and disposed along a first direction; A second pixel area row including a plurality of second pixel areas and disposed along the first direction; A first gate line disposed along one side of the first pixel area row in the first direction; A second gate line disposed along one side of the second pixel area row in the first direction; A plurality of data lines disposed along a second direction between adjacent pixel regions in each of the pixel region rows; And And a common line disposed along the first direction between the other sides of the pixel region columns. 9. The semiconductor device of claim 8, further comprising: thin film transistors connected to the gate lines and the data lines; Pixel electrodes connected to the thin film transistors; A plurality of pixel electrode bars extending from the pixel electrodes; A first electrode extending from at least one of the pixel electrode bars arranged in each of the first pixel areas to overlap the common line; A second electrode extending from at least one of the appeal electrode bars disposed in each of the second pixel areas and overlapping the common line; First and second common electrodes electrically connected to the common line; First common electrode bars extending from the first common electrode and alternately arranged with the pixel electrode bars disposed in the first pixel area; And And second common electrode bars extending from the second common electrode and alternately arranged with the pixel electrode bars arranged in the second pixel area. The liquid crystal display of claim 9, wherein the first and second common electrodes are integrally formed. The liquid crystal display of claim 8, wherein the common line is formed on the same layer as the gate line. The liquid crystal display of claim 8, wherein the common line is formed on the same layer as the same material as each of the data lines. The method of claim 12, wherein in the area where the common line and the data line cross each other, A connection electrode disposed on the same layer as each of the gate lines and disposed in the cross region; And And first and second common lines disposed to be spaced apart from each of the data lines and electrically connected to the connection electrodes.

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