KR20090011564A - Method for fabricating of semiconductor package - Google Patents

Method for fabricating of semiconductor package Download PDF

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Publication number
KR20090011564A
KR20090011564A KR1020070075261A KR20070075261A KR20090011564A KR 20090011564 A KR20090011564 A KR 20090011564A KR 1020070075261 A KR1020070075261 A KR 1020070075261A KR 20070075261 A KR20070075261 A KR 20070075261A KR 20090011564 A KR20090011564 A KR 20090011564A
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South Korea
Prior art keywords
bump
capillary
bonding
metal wire
substrate
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KR1020070075261A
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Korean (ko)
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이찬선
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주식회사 하이닉스반도체
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Priority to KR1020070075261A priority Critical patent/KR20090011564A/en
Publication of KR20090011564A publication Critical patent/KR20090011564A/en

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

A method for manufacturing a semiconductor package is provided to reduce a loop height of a metal wire in a package by forming the metal wire in a reverse bonding method after flattening a protrusive part of a bump by using a press capillary. A first bump(222) is formed on a bonding pad(242) of a semiconductor chip attached on the substrate by a bond capillary(270). A first bump has a protrusive structure. The first bump is flattened and pressed by a compression capillary(280). A second bump is formed on a connection pad of the substrate. The first bump and the second bump are connected by a metal wire(224).

Description

반도체 패키지 제조 방법{Method for fabricating of semiconductor package}Method for fabricating a semiconductor package

본 발명은 반도체 패키지의 제조 방법에 관한 것으로서, 보다 상세하게는, 두께가 얇은 다단 멀티 칩 패키지를 구현할 수 있는 반도체 패키지의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor package, and more particularly, to a method of manufacturing a semiconductor package that can implement a thin multi-stage multi-chip package.

전기·전자 제품이 고성능화되고 전자기기들이 경박단소화됨에 따라 핵심 소자인 패키지의 고밀도, 고실장화가 중요한 문제로 대두되고 있다. 또한, 컴퓨터의 경우 기억 용량의 증가에 따라 대용량의 램(Random Access Memory) 및 플래쉬 메모리(Flash Memory)와 같이 칩의 용량은 증대되지만, 패키지는 소형화되는 경향으로 연구되고 있어 한정된 크기의 기판에 더 많은 수의 패키지를 실장하기 위한 여러 가지 기술들이 제안·연구되고 있다. As electrical and electronic products are getting higher performance and electronic devices are lighter and shorter, the high density and high mounting of the package, which is a key element, is becoming an important problem. In addition, in the case of a computer, as the storage capacity increases, the chip capacity increases, such as a large amount of random access memory (RAM) and flash memory (Flash memory), but the package is tended to be smaller, and thus the size of the chip is limited to a limited size substrate. Various techniques have been proposed and studied to implement a large number of packages.

이러한 패키지의 크기를 줄이기 위해 제안된 방법들은 복수개의 칩 또는 패키지가 실장된 멀티 칩 패키지(Multi Chip Package) 또는 멀티 칩 모듈 패키지(Multi Chip Module Package)등이 제안되었으며, 주로 반도체 칩 및 패키지가 기판 상에 평면적인 배열 방법으로 실장되기 때문에 제작에 한계가 있었다. Proposed methods for reducing the size of such a package have been proposed such as a multi chip package or a multi chip module package in which a plurality of chips or packages are mounted. The manufacturing was limited because it is mounted in a planar arrangement method.

이러한 한계를 극복하기 위하여 다수의 반도체 칩을 일체적으로 복수개 적층한 적층 칩 패키지와 같은 다단 멀티 칩 패키지 기술이 제안되었으며, 최근에는 상기 다단 멀티 칩 패키지 형태의 반도체 패키지 수요가 급증하고 있다. In order to overcome this limitation, a multi-stage multi-chip package technology, such as a multilayer chip package in which a plurality of semiconductor chips are integrally stacked, has been proposed. Recently, the demand for semiconductor packages in the form of the multi-stage multi-chip package has increased rapidly.

도 1은 종래 멀티 칩 패키지를 도시한 도면이고, 도 2는 상기 도 1의 금속 와이어 연결 부분을 설명하기 위하여 도시한 도면이다. 1 is a diagram illustrating a conventional multi-chip package, and FIG. 2 is a diagram illustrating the metal wire connection part of FIG. 1.

도 1을 참조하면, 기판(110)상에 다수의 반도체 칩(120, 130, 140)이 적층되고, 상기 기판(100)과 각 반도체 칩들(120, 130, 140)은 금속 와이어(124, 134, 144)에 의해 전기적으로 연결된다. Referring to FIG. 1, a plurality of semiconductor chips 120, 130, and 140 are stacked on a substrate 110, and the substrate 100 and the semiconductor chips 120, 130, and 140 are metal wires 124 and 134. 144).

상기 기판(110)의 상면에는 상기 반도체 칩(120, 130, 140)을 덮도록 봉지부(150)가 형성되며, 상기 기판(110)의 하면에는 외부접속단자인 솔더볼(160)이 부착된다.An encapsulation part 150 is formed on an upper surface of the substrate 110 to cover the semiconductor chips 120, 130, and 140, and a solder ball 160, which is an external connection terminal, is attached to the lower surface of the substrate 110.

도 2를 참조하면, 종래 금속 와이어 형성 공정은, 우선, 상기 반도체 칩(120)의 본딩 패드(122) 상에 본딩 캐필러리(Bonding capillary) 장치로 제1범프(124)를 형성한다. Referring to FIG. 2, in the conventional metal wire forming process, first bumps 124 are formed on a bonding pad 122 of the semiconductor chip 120 by a bonding capillary device.

그런 다음, 본딩 캐필러리 장치를 이용하여 상기 기판(110)의 접속 패드(112) 상에 제2범프(114)를 형성함과 아울러 상기 제1범프(124) 및 제2범프(114) 간에 스티피(Stitch) 본딩을 수행하는 리버스 본딩(Reverse bonding) 공정으로 금속 와이어(124)를 형성한다.Then, a second bump 114 is formed on the connection pad 112 of the substrate 110 by using a bonding capillary device, and between the first bump 124 and the second bump 114. The metal wire 124 is formed by a reverse bonding process that performs stitch bonding.

상기 제1범프(124)는 본딩 캐필러리 장치를 이용하여 상기 반도체 칩(120) 제1범프(124)를 형성한 후, 상기 제1범프(124)를 형성하는 금속 물질을 절단하는 공정 상의 이유로 인하여 상부가 일정 높이(H2)로 돌출되는 구조를 갖는다.The first bump 124 is formed by using the bonding capillary device to form the first bump 124 of the semiconductor chip 120, and then cuts a metal material forming the first bump 124. For the reason, the upper portion has a structure protruding to a predetermined height (H2).

따라서, 상기 금속 와이어(124)의 형성시 상기 제1범프(124)의 돌출된 구조로 인하여 상기 금속 와이어(124)의 루프 높이(Loop heigh : H1)가 높아지고, 이에 따라, 두께가 얇은 멀티 칩 패키지를 구현하기 힘들어, 많은 반도체 칩이 스택된 멀티 칩 패키지를 형성하기 어렵다. Accordingly, when the metal wire 124 is formed, the loop height H1 of the metal wire 124 is increased due to the protruding structure of the first bump 124. Accordingly, the thin chip is thin. As the package is difficult to implement, it is difficult to form a multi-chip package in which many semiconductor chips are stacked.

본 발명은 두께가 얇은 다단 멀티 칩 패키지를 구현할 수 있는 반도체 패키지의 제조 방법을 제공한다.The present invention provides a method of manufacturing a semiconductor package that can implement a thin multi-stage multi-chip package.

본 발명에 따른 반도체 패키지의 제조 방법은, 반도체 칩의 본딩 패드와 기판의 접속 패드 사이를 전기적으로 연결하는 금속 와이어 형성 공정을 포함하는 반도체 패키지의 제조 방법에 있어서, 상기 기판의 상면에 부착된 반도체 칩의 본딩 패드 상에 본드 캐필러리를 사용하여 제1범프를 형성하는 단계; 상기 제1범프를 압축 캐필러리로 눌러 평평하게 만드는 단계; 및 상기 기판의 접속 패드 상에 제2범프를 형성함과 아울러 상기 제1 및 제2범프를 연결하는 금속 와이어를 형성하는 단계;를 포함하는 것을 특징으로 한다.A method for manufacturing a semiconductor package according to the present invention includes a metal wire forming step of electrically connecting a bonding pad of a semiconductor chip and a connection pad of a substrate, wherein the semiconductor package is attached to an upper surface of the substrate. Forming a first bump using a bond capillary on a bonding pad of the chip; Pressing the first bump into a compression capillary to flatten the first bump; And forming a second bump on the connection pad of the substrate and forming a metal wire connecting the first and second bumps.

본 발명은 두께가 얇은 다단 멀티 칩 패키지를 구현하기 위하여 반도체 칩 상에 본딩 캐필러리를 이용하여 제1범프를 형성한 후, 프레스 캐필러리(Press capillary)로 제1범프의 돌출된 부분을 눌러 상기 제1범프를 평평하게 만든다.The present invention is to form a first bump using a bonding capillary on a semiconductor chip to implement a thin multi-stage multi-chip package, and then press the projecting portion of the first bump with a press capillary (Press capillary). Press to flatten the first bump.

그런 다음, 기판 상에 제2범프를 형성함과 아울러 스티치 본딩 공정을 수행하여 상기 제1 및 제2범프간을 전기적으로 연결하는 금속 와이어를 형성한다.Then, a second bump is formed on the substrate, and a stitch bonding process is performed to form a metal wire electrically connecting the first and second bumps.

따라서, 종래 제1범프의 돌출된 구조에 의해 상기 금속 와이어의 높은 루프 높이를 낮출 수 있어, 두께가 얇은 멀티 칩 패키지를 구현함과 아울러 많은 반도체 칩이 스택된 멀티 칩 패키지를 형성할 수 있다. Therefore, the high loop height of the metal wire can be lowered by the protruding structure of the conventional first bump, thereby realizing a thin multi-chip package and forming a multi-chip package in which many semiconductor chips are stacked.

일반적으로, 와이어 본딩은 반도체 칩의 본딩 패드와 리드 프레임 또는 인쇄 회로 기판과 같은 실장 부재간을 금(Au), 알루미늄(Al) 등과 같은 금속 와이어를 사용하여 전기적으로 연결하는 기술을 일컫는다. In general, wire bonding refers to a technique for electrically connecting a bonding pad of a semiconductor chip and a mounting member such as a lead frame or a printed circuit board using metal wires such as gold (Au) and aluminum (Al).

상기 와이어 본딩은 플립 칩 패키지를 형성하기 위한 스터드 범프와 같은 미세 본딩용 범프의 형성에도 사용되며, 전자회로의 조립 실장에 없어서는 안될 기술로서 현재까지 전기적 연결 기술에 주류를 이루고 있다. The wire bonding is also used to form fine bonding bumps, such as stud bumps for forming flip chip packages, and is indispensable in assembly of electronic circuits.

현재 반도체 소자의 공정 기술이 미세 피치를 구현하는 방향으로 발전하고 있으나, 상기 와이어 본딩 기술은 본딩 방법이 포인드에서 포인트로 연결하는 방법이기 때문에 정밀도가 높지 않은 저렴한 제품에 계속적으로 사용되고 있다.Currently, the process technology of the semiconductor device is evolving toward realizing a fine pitch. However, the wire bonding technology is continuously used in low-cost products with high precision because the bonding method is a method of connecting from a point to a point.

아울러, 상기 와이어 본딩 기술은 설계 변경에 대한 유연성이 있고, 입체적인 2단 이상의 본딩도 수행할 수 있다는 장점이 있다. In addition, the wire bonding technology has the advantage of flexibility in design changes, and can perform two-dimensional or more two-step bonding.

상기 와이어 본딩 기술은 초음파 진동을 이용한 초음파 열압착 방식(ultrasonic thermocompression type)으로 공정이 진행된다.The wire bonding technology is an ultrasonic thermocompression type using ultrasonic vibration.

상기 초음파 열압착 방식에 의한 와이어 본딩 방법은, 먼저 캐필러리를 관통 하는 와이어 선단에 접착 볼을 형성한 후, 접착 볼이 본딩 패드 상에 위치하도록 캐필러리를 이동시킨 다음, 상기 캐필러리에 소정의 힘(force)과 초음파 진동(혹은 파워) 및 열을 가하여 상기 와이어의 접착 볼을 상기 반도체 칩의 본딩 패드에 초음파 열압착시켜 범프를 형성시킨다.In the wire bonding method according to the ultrasonic thermocompression method, first, an adhesive ball is formed at a wire tip passing through the capillary, and then the capillary is moved to position the adhesive ball on the bonding pad, and then the capillary is moved to the capillary. By applying a predetermined force, ultrasonic vibration (or power) and heat, the adhesive ball of the wire is subjected to ultrasonic thermocompression bonding to a bonding pad of the semiconductor chip to form a bump.

그런 다음, 캐필러리를 실장 부재의 전극 상부로 이동시킨 다음, 상기 와이어와 실장 부재간을 재차 초음파 열압착시킨 후, 캐필러리에 소정의 장력을 가하여 와이어를 절단하는 방식으로 수행된다. Then, the capillary is moved to the upper portion of the electrode of the mounting member, and then ultrasonically thermocompression-bonded between the wire and the mounting member, and then the wire is cut by applying a predetermined tension to the capillary.

그러나, 상기 본딩 패드 상에 형성되는 범프는 상기 절단 공정에 의한 구조적인 문제로 상부로 돌출되는 형태를 가지며, 이로 인해 금속 와이어의 루프 높이가 높아지는 문제가 계속 발생한다.However, the bumps formed on the bonding pads have a shape that protrudes upward due to structural problems caused by the cutting process, thereby causing a problem that the loop height of the metal wire is increased.

이에 따라, 상기 루프 높이에 의하여 두께가 얇은 멀티 칩 패키지를 구현하기 힘들고, 많은 반도체 칩이 스택된 멀티 칩 패키지를 형성하기 어렵다. Accordingly, it is difficult to implement a thin multi-chip package due to the loop height, and it is difficult to form a multi-chip package in which many semiconductor chips are stacked.

이하에서는 도 3a 내지 도 3c를 참조하여 본 발명의 실시예에 따른 반도체 패키지의 제조 방법을 상세히 설명하도록 한다.Hereinafter, a method of manufacturing a semiconductor package according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3C.

도 3a를 참조하면, 상면에 다수의 접속 패드(212)를 구비한 기판(210) 상에 페이스 업(Face up) 타입으로 상면에 다수의 본딩 패드(242)를 구비한 반도체 칩(240)을 부착한다. Referring to FIG. 3A, a semiconductor chip 240 including a plurality of bonding pads 242 may be formed on a top surface of a substrate 210 having a plurality of connection pads 212 on an upper surface thereof. Attach.

그런 다음, 상기 반도체 칩(240)의 본딩 패드(242) 상에 본딩 캐필러리(270)를 이용하여 제1범프(222)를 형성한다. Then, the first bump 222 is formed on the bonding pad 242 of the semiconductor chip 240 using the bonding capillary 270.

상기 제1범프(222)는 본딩 캐필러리(270) 내부에 구비되어 있는 금(Au)과 같 은 금속 와이어 형성 물질을 열 및 압력을 가하여 상기 본딩 패드(242) 상에 부착한 후 절단하여 형성한다. The first bump 222 is attached to the bonding pad 242 by applying heat and pressure to a metal wire forming material such as gold (Au) provided in the bonding capillary 270 and then cutting Form.

이때, 상기 제1범프(222)는 금속 와이어 절단 공정에 의해 일정 높이(H2)로 돌출된 부분을 포함하는 구조를 갖는다. In this case, the first bump 222 has a structure including a portion protruding to a predetermined height (H2) by a metal wire cutting process.

도 3b를 참조하면, 상기 반도체 칩(240)의 본딩 패드(242) 상에 형성되고, 돌출된 부분을 포함하는 구조를 갖는 제1범프(222)를 압축 캐필러리(280)로 눌러 평평한 구조로 만든다. Referring to FIG. 3B, a flat structure is formed on the bonding pad 242 of the semiconductor chip 240 by pressing the first bump 222 having the structure including the protruding portion with the compression capillary 280. Make it.

도 3c를 참조하면, 상기 기판(210)의 접속 패드(212) 상에 본딩 캐필러리(270)를 이용하여 제2범프(224)를 형성함과 아울러 평평한 구조를 갖는 상기 제1범프(224)와 전기적으로 연결하는 금속 와이어(224)를 리버스 본딩 방식으로 형성한다. Referring to FIG. 3C, a first bump 224 having a flat structure and a second bump 224 are formed using a bonding capillary 270 on the connection pad 212 of the substrate 210. ) And a metal wire 224 electrically connected to each other is formed by a reverse bonding method.

이상에서와 같이, 본 발명은 반도체 칩 상에 제1범프를 형성하고ㅡ 프레스 캐필러리(Press capillary)로 제1범프의 돌출된 부분을 눌러 상기 제1범프를 평평하게 만든 후, 리버스 본딩 방식으로 금속 와이어를 형성함으로써 금속 와이어의 루프 높이를 낮출 수 있어, 두께가 얇은 멀티 칩 패키지를 구현함과 아울러 많은 반도체 칩이 스택된 멀티 칩 패키지를 형성할 수 있다. As described above, the present invention forms a first bump on the semiconductor chip-press the protruding portion of the first bump with a press capillary (flat) to make the first bump, then reverse bonding method By forming the metal wires, the loop height of the metal wires can be lowered, thereby realizing a thin multi-chip package and forming a multi-chip package in which many semiconductor chips are stacked.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자가 용이하게 알 수 있 다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

도 1은 종래 멀티 칩 패키지를 도시한 단면도.1 is a cross-sectional view showing a conventional multi-chip package.

도 2는 상기 도 1의 금속 와이어 연결 부분을 설명하기 위하여 도시한 도면.FIG. 2 is a view illustrating the metal wire connection part of FIG. 1. FIG.

도 3a 내지 도 3c는 본 발명의 실시예에 따른 금속 와이어 형성 공정을 설명하기 위한 공정별 단면도.3A to 3C are cross-sectional views of processes for explaining a metal wire forming process according to an embodiment of the present invention.

Claims (1)

반도체 칩의 본딩 패드와 기판의 접속 패드 사이를 전기적으로 연결하는 금속 와이어 형성 공정을 포함하는 반도체 패키지의 제조 방법에 있어서,In the manufacturing method of a semiconductor package including the metal wire formation process of electrically connecting between the bonding pad of a semiconductor chip, and the connection pad of a board | substrate, 상기 기판의 상면에 부착된 반도체 칩의 본딩 패드 상에 본드 캐필러리를 사용하여 돌출된 구조를 갖는 제1범프를 형성하는 단계;Forming a first bump having a protruding structure using a bond capillary on a bonding pad of a semiconductor chip attached to an upper surface of the substrate; 상기 제1범프를 압축 캐필러리로 눌러 평평하게 만드는 단계; 및Pressing the first bump into a compression capillary to flatten the first bump; And 상기 기판의 접속 패드 상에 제2범프를 형성함과 아울러 상기 제1 및 제2범프를 연결하는 금속 와이어를 형성하는 단계;를 Forming a second bump on the connection pad of the substrate and forming a metal wire connecting the first and second bumps; 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.Method for producing a semiconductor package comprising a.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160021675A (en) * 2014-08-18 2016-02-26 삼성전자주식회사 Method of manufacturing a semiconductor package and apparatus for performing the same
WO2017166308A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Wire bond connection with intermediate contact structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160021675A (en) * 2014-08-18 2016-02-26 삼성전자주식회사 Method of manufacturing a semiconductor package and apparatus for performing the same
WO2017166308A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Wire bond connection with intermediate contact structure
US10438916B2 (en) 2016-04-01 2019-10-08 Intel Corporation Wire bond connection with intermediate contact structure

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