KR20090011094A - Current source having a high tolerance for changing environmental condition - Google Patents

Abstract

A current source is provided to supply stable currents insensitively to environmental change while obtaining wide output ranges even at low power supply voltage, thereby preventing excessive power consumption. A voltage regulator determines an output voltage by using an input voltage. A plurality of transistors(40) is connected in parallel between the output terminal of the voltage regulator and a ground. A detecting unit(30) selects any one of the plurality of transistors on the basis of phase changes in the delayed clock. The selected transistor is operated.

Description

Current source insensitive to environmental changes {CURRENT SOURCE HAVING A HIGH TOLERANCE FOR CHANGING ENVIRONMENTAL CONDITION}

The present invention relates to a current source insensitive to environmental changes, and more particularly to a low power current source insensitive to changes in process, power supply voltage and temperature and having a wide output voltage range.

The rapid development of semiconductor manufacturing process technology enables more accurate wiring and circuit integration, and the development of various portable devices has tended to lower the power supply voltage to reduce power consumption as much as possible. This reduction in supply voltage inevitably leads to degradation of analog circuit performance, which adds to the design difficulty.

Current sources are the most fundamentally necessary circuits in analog circuit design. The currents generated by these current sources allow current to flow through all analog circuits through current repeaters. Therefore, the importance of the entire circuit is needless to say, because errors in this current source affect the entire analog circuit. However, such a current source is also difficult to design by reducing the power supply voltage, and becomes sensitive to environmental changes such as process variations due to miniaturized circuit components and wiring, or changes in power supply voltage and temperature.

However, in the case of a current source that must always make a constant current irrespective of the changes in the various environments, its implementation has not been established yet.

1 to 3 show the configuration of a current source generally used.

The most basic current source is the type shown in FIG. 1, and FIG. 2 is a current source made in the form of a cascode, a method of increasing the output resistance seen at the output in order to reduce the effective channel length variation. And, Figure 3 is a current source having a wide output range made to compensate for the disadvantage that the output voltage range is reduced when the cascode form. In the above circuits, node A is made from the bandgap reference circuit, so it is less sensitive to changes in P (process), V (power supply voltage), and T (temperature).

Typically, there are three current sources shown in Figs. 1 to 3, but in the case of Fig. 1, the output resistance is small, so that the effective channel length fluctuates largely, and an error occurs in the current value set as the target value. In this case, the node B has a small output voltage range of about V _DD (supply voltage) -V _{D , sat} -Vth (threshold voltage), V _DD -2V _{D , and sat , respectively} . As a result, the current sources shown in FIGS. 2 and 3 do not maintain linearity over a wide output range, which means that due to the development of the process, it is a structure that is difficult to use in the current trend of decreasing power supply voltage.

In addition, the node A voltage is not sensitive to P (process), V (power supply voltage), and T (temperature) change (hereinafter referred to as PVT change), but the MOS device characteristic is sensitive to PVT change, thereby causing an error in a desired target current. Will occur.

In order to solve the above-mentioned problems, an improved current source as shown in FIG. 4 is constructed. The node A voltage is made in the bandgap reference circuit as described above, and is connected with negative feedback through the voltage regulator 10 so that the voltages of the node A and the node C become equal, where voltage and resistance R are equal. The current flows through the resistor by the relation This circuit has the advantage that the Node B because it has an output voltage range of up to a maximum of V _DD -V _A V _A If the day can have a wide output voltage range almost close to V _DD.

However, since the resistance (R) generally has a basic change rate of about 20%, the current also changes by about 20% based on the relationship of I (current) = V (voltage) / R (resistance). Since the worst case should always be considered in the circuit design, design the circuit considering the loss of -20% of the current, so that the power is also about 20% in the relationship of P (power) = V (voltage) × I (current). You should have a lot of room. This causes unnecessary power waste in the whole system. Therefore, it is essential to make an effort to reduce power consumption by reducing the change rate of the resistance to PVT change and thereby also generate heat.

U.S. Patent No. 5,774,013 "Dual source for constant and PTAT current" uses resistance change rate compensation with temperature. There is a limit that power is wasted because it is impossible to compensate by diversity, and it is necessary to design the power margin according to the change.

The object of the embodiments of the present invention is to provide a stable current insensitive to external environmental changes while having a wide output range even at a low power supply voltage, and to digitally process compensation for such environmental changes, thereby maximizing power consumption required for compensation. It provides a current source that is insensitive to environmental changes to prevent excessive power waste due to unnecessary design margins.

Another object of the embodiments of the present invention is to apply a plurality of transistor resistors having different characteristics, rather than passive elements, with a large variation in external environment change, and after detecting the external environment change through digital detection, among the transistor resistors. By holding the current in such a way as to select one, it provides a current source insensitive to external environmental changes.

Another object of the embodiments of the present invention is to provide a current source insensitive to external environmental changes by quantifying the external environmental change through a plurality of delay stages to compensate for the resistance change to a value suitable for the corresponding environmental change.

In order to achieve the above object, a current source insensitive to changes in the external environment according to an embodiment of the present invention includes a voltage regulator for determining the output voltage by the input voltage; A plurality of transistors connected in parallel between the output of the voltage regulator and ground; And a detector configured to select one of the plurality of transistors to operate based on the phase change of the delayed clock, wherein the plurality of transistors each have a different width.

Here, the plurality of transistors are preferably MOS transistors each having a sequentially increasing width or a sequentially decreasing length.

The detector includes a delay unit for generating a multi-phase clock signal having a constant phase difference through delay stages of the same structure, a quantizer for quantizing the multi-phase clock signals of the delay unit, and a falling edge of the signal among the outputs of the quantizer. It includes an identification unit for identifying the corresponding delay stage.

The delay stage and the transistor correspond to 1: 1 or n: 1, and the detector selects and operates a transistor corresponding to the delay stage identified through the identification unit.

According to another embodiment of the present invention, the current source insensitive to changes in the external environment is provided with an output voltage obtained by subtracting the first input node voltage from a reference voltage according to the voltage of the first node, and the second input node has a negative feedback configuration. A voltage regulator, a transistor resistor unit arranged in parallel between MOS transistors whose widths or lengths vary sequentially between an output of the voltage regulator and ground, and an operation of the plurality of transistors based on a phase change of a delayed clock. It comprises a detection unit for selecting one to be made.

The detection unit includes a plurality of unit delay stages, and the plurality of transistors are based on the number of delay stages delayed for one cycle through a change in the delay time of the unit delay stage according to at least one of a process, a power supply voltage, and a temperature. It is configured to select one of these to operate.

The current source insensitive to environmental changes according to the embodiment of the present invention has a wide output range even at a low power supply voltage, and provides a stable current insensitive to external environmental changes, and digitally processes compensation for such environmental changes. The power consumption required for compensation can be minimized to prevent excessive power waste due to unnecessary design margin.

The current source insensitive to environmental changes according to an embodiment of the present invention is to apply a resistor having a large fluctuation to the external environmental change instead of a passive element, a plurality of transistor resistors having different characteristics, and to detect the external environmental change through digital detection. Thereafter, the current is maintained by selecting one of the transistor resistors, thereby providing a stable fixed current.

The current source insensitive to environmental changes according to an embodiment of the present invention is to determine the external environmental change as the phase change of the clock passing through a plurality of delay stages to compensate for the resistance change to a value suitable for the corresponding environmental change, and also By processing digitally, there is an effect of minimizing power consumption to cope with changes in the external environment.

The present invention as described above will be described in detail with reference to the accompanying drawings and embodiments.

FIG. 5 is a conceptual view showing the configuration of an embodiment of the present invention. As shown in FIG. 4, the overall configuration method is similar to that of the current source of FIG. 4, but instead of using a resistor as shown in FIG. NMOSs are connected in parallel (M0 to M14) 40, and each gate of the plurality of NMOSs is connected to the output of the PVT change detector 30 to control on / off of each NMOS.

The operation method of the entire circuit is as follows. First, the degree of PVT change is output as a digital code from the P (process), V (power supply voltage), and T (temperature) change detector 30 based on an externally applied clock. The output code is a 1-of-N digital code, in which only one of the N digital codes is 1, and a power supply voltage is applied to only one MOS gate among several NMOS devices. At this time, when applying a drain voltage of the MOS in a very small voltage is very small the voltage V _DS between the drain and the source, Morse deep tree odd region (Deep Triod Region) current operation, so passing through the V _DS and moss in the I _D Has a linear characteristic. This linear characteristic can be used as a resistance, and can represent a resistance value as shown in Equation 1 below.

μ _n is the mobility characteristic of MOS and Cox is the capacitor value of oxide. W and L are the width and length of MOS. V _GS is the voltage between the gate and the source of the MOS, and Vth is the threshold voltage of the MOS. The values that can be adjusted in Equation 1 are W, L, and V _GS . Since V _GS applies a supply voltage to the gate, the supply voltage is always applied, and the L value is preferably fixed for easy design. Therefore, the resistance value can be adjusted by adjusting the W value. Of course, you can also fix the W value and change the L value.

Referring to Equation 1, the higher the process P, the lower the temperature T, the greater the mobility (μ _n ) characteristic of the MOS, and the greater the power supply voltage V, the greater the V _GS and the greater W. If the same, the resistance can be seen to be small. Therefore, if the above-described case is detected by the PVT change detector 30 and a power supply voltage is applied to the gate of the MOS of which W is small among several NMOS, it is possible to maintain almost constant resistance even if the PVT changes. The same applies to the reverse case.

In Equation 1, it can be seen that the proportional relationship between the resistance value and the PVT is equal to the proportional relationship between the operating speed and the PVT in the inverter. The PVT change detector 30 is configured as shown in FIG. 6 using this. 7 is a timing diagram of a PVT detector.

The detailed operation of FIG. 6 is as follows.

The input clock signal passes through the delay line with a different delay depending on the PVT. In the delay line, a multi-phase clock signal having a constant phase difference τ is output through the delay stage 80 having the same structure, and these signals are applied to an N-bit quantizer 70. The quantizer 70 is configured as a D-flip flop as shown, and the multi-phase clock signals through the delay stage 80 are applied to the data input. Then, the sample is sampled using an input clock that does not go through the delay stage 80, and the point of the delay stage 80 transitioning from 1 to 0 is found through the identifier unit 60 block. This indicates the position of the delay stage 80 in which the delay time of the input clock corresponding to the PVT change corresponds to one period. The switching detector outputs a digital output code (for example, 0000111000111) of the quantizer as 1 and only a section that transitions from 1 to 0 and all remaining sections as 0 so that the 1-of-N digital code (in the illustrated example) Send D <1:14>) as output. The quantization unit 70 and the identification unit 60 may be regarded as the transition detection unit 50.

If the PVT change is the worst case, since the delay time of the delay stage is small, there is a delay by one cycle even through a small number of delay stages. Therefore, the switching detector outputs 1 from the digital code at the front of the block, for example, D <1> to D <2>. On the contrary, if the PVT change is the best case, the delay time of the delay stage is shortened so that the input clock signal has to go through a large number of delay stages in order to be delayed by one cycle. Therefore, in the digital code behind the switching detector, for example, 1 is output from D <13> to D <14>.

The delay stage can be implemented with a static inverter to minimize power.

The PVT change detector 30 applied in this embodiment has all blocks digitally configured to eliminate the static power consumption, thereby minimizing the overall power consumption. It can also operate under low supply voltages, while minimizing footprint.

As described above, the PVT detector 30 outputs a digital code of 1 at the leading bit as the worst case of PVT and at the trailing bit as the best case. With this output code, the NMOSs connected in parallel in the current source are arranged in order of the order of the largest W, so that the supply voltage is applied only to the gate of the NMOS with the largest PVT and the gate of the small NMOS with the best PVT. Configured to be authorized. If L is used, the same effect can be obtained by arranging L in small order.

Through the above method, it is possible to implement a current source that always generates a constant current by maintaining a constant resistance value even when PVT changes.

8 is a simulation result diagram of a current source configured in one embodiment of the present invention.

As a target value, the current value is 100 uA, and as shown, it can be seen that the maximum error is ± 2% depending on the PVT situation. This value is reduced to one tenth of that of conventional resistors, and is equivalent to 14 NMOS parallel connections. If the number is further increased, the error can be further reduced.

1 to 3 are exemplary views of a general current source.

4 is a schematic diagram of an improved current source.

5 is a block diagram of an embodiment of the present invention.

6 is a P (process), V (power supply voltage), T (temperature) change detector applied to an embodiment of the present invention.

7 is a timing diagram of a PVT detector.

8 is a simulation result of the current source used in the present invention.

** Description of symbols for the main parts of the drawing **

20: amplifier 30: PVT detector

40: parallel transistor group 50: transition detector

60: quantization unit 70: identification unit

80: delay stage

Claims (9)

A voltage regulator whose output voltage is determined by an input voltage; A plurality of transistors connected in parallel between the output of the voltage regulator and ground; And a detector configured to select one of the plurality of transistors to operate based on a phase change of a delayed clock. The current source insensitive to environmental changes according to claim 1, wherein the plurality of transistors each have a different width. 3. The current source insensitive to environmental changes according to claim 2, wherein the plurality of transistors are MOS transistors each having a sequentially increasing width or a sequentially decreasing length. The method of claim 1, wherein the detection unit A delay unit for generating a multi-phase clock signal having a constant phase difference through delay stages of the same structure; A quantizer for quantizing the multi-phase clock signals of the delay unit; And an identification unit for identifying a delay end point corresponding to a falling edge of the signal among the outputs of the quantizer. The environment of claim 4, wherein the delay stage and the transistor correspond to 1: 1 or n: 1, and the detector selects and operates a transistor corresponding to the delay stage identified through the identification unit. Insensitive to current sources. 6. The current source insensitive to environmental changes according to claim 5, wherein the delay stage operates a transistor having a larger width as the delay stage identified by the identification unit is faster. An output voltage obtained by subtracting the first node voltage from a reference voltage according to a voltage of a first input node, and the second input node includes a voltage regulator having a negative feedback configuration; A transistor resistor unit arranged in parallel between MOS transistors whose width or length thereof is sequentially changed between an output of the voltage regulator and a ground; And a detector configured to select one of the plurality of transistors to operate based on a phase change of a delayed clock. The method of claim 7, wherein the detection unit comprises a plurality of unit delay stages, and the number of delay stages delayed for one cycle by changing the delay time of the unit delay stages according to at least one of process, power supply voltage, and temperature changes. And select one of the plurality of transistors to be operated on the basis of the current. The method of claim 8, wherein the delay stage and the transistor correspond to 1: 1 or n: 1, and the detector selects a transistor corresponding to a delay stage at a position corresponding to the number of delay stages delayed during the one period. Current source insensitive to environmental changes, characterized in that.

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