KR101006697B1 - Bandgap reference voltage genaerating circuit for generating bandgap reference voltage satable regardless of deviation in fabrication condition - Google Patents

Abstract

A bandgap reference voltage generation circuit for generating a stable bandgap reference voltage in response to changes in process conditions is disclosed. The bandgap reference voltage generation circuit of the present invention includes a bandgap voltage generator for generating a bandgap reference voltage, wherein the level of the bandgap reference voltage is adjusted by level control data; A charge monitoring unit configured to perform level adjustment monitoring according to capacitance of a capacitor group controlled by capacitance setting data and to generate a monitoring signal indicating a result of the level adjustment monitoring; And a continuous data storage unit generating the level adjustment data and the capacitance setting data in response to the clock signal group, wherein the level adjustment data corresponds to the capacitance setting data in which a one-way transition of a logic state of the monitoring signal occurs. And a continuous information storage section having a data value. According to the bandgap reference voltage generating circuit of the present invention, a bandgap reference voltage VBGR is provided which is stable to changes in process conditions.

Description

BANDGAP REFERENCE VOLTAGE GENAERATING CIRCUIT FOR GENERATING BANDGAP REFERENCE VOLTAGE SATABLE REGARDLESS OF DEVIATION IN FABRICATION CONDITION}

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a bandgap reference voltage generation circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating the bandgap voltage generator 100 of FIG. 1 in detail.

3 is a view showing in detail the charge monitoring unit 300 of FIG.

4 to 6 are timing diagrams for explaining an example of the level adjustment monitoring operation in the bandgap reference voltage generation circuit of FIG. 1, respectively.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic circuits, and more particularly to a bandgap reference voltage generating circuit.

In a device such as a semiconductor integrated circuit, a reference voltage is provided for which a stable level is required to stably control the operation of internal components such as an analog-to-digital converter, a digital-to-analog converter, and the like. The bandgap reference voltage generator is widely used as a circuit for generating such a reference voltage. The bandgap reference voltage provided in the bandgap reference voltage generator circuit is known to have a relatively stable voltage level against temperature changes in the device.

However, the existing bandgap reference voltage generation circuit has a problem that the generated bandgap reference voltage is considerably unstable with changing conditions of the manufacturing process of the device.

Accordingly, an object of the present invention is to provide a bandgap reference voltage generation circuit for generating a bandgap reference voltage having a stable voltage level in response to changes in process conditions.

One aspect of the present invention for achieving the above technical problem relates to a bandgap reference voltage generation circuit. The bandgap reference voltage generation circuit of the present invention includes a bandgap voltage generator for generating a bandgap reference voltage, wherein the level of the bandgap reference voltage is adjusted by level control data; A clock generator generating a clock signal group having a predetermined clock period; In each of the plurality of unit monitoring intervals, the level adjustment monitoring according to the capacitance of the capacitor group controlled by the capacitance setting data is performed, and generates a monitoring signal indicating the result of the level adjustment monitoring, the timing of each unit monitoring interval A width monitoring unit corresponding to a clock period of the clock signal group; And a continuous data storage unit configured to generate the level adjustment data and the capacitance setting data in response to the clock signal group, wherein the capacitance setting data is generated for each unit monitoring period, and sequentially controls the capacitance of the capacitor group. The continuous information storage unit having a data value, wherein the level adjustment data includes the continuous information storage unit having a data value corresponding to the capacitance setting data at which one-way transition of a logic state of the monitoring signal occurs.

Preferably, the charge monitoring unit includes the capacitor group, the charge level generating means for generating a charge signal, the capacitor group is charged in response to a charge clock signal included in the clock signal group, the clock signal group A charge level generating means for discharging in response to a reset clock signal included in the charge signal, wherein the charge signal is increased in voltage level according to the charging of the capacitor group and resets the voltage level in response to the discharge of the capacitor group; And comparison latch means for generating the monitoring signal by comparing the level of the charging signal at the time of charging the capacitor group with a predetermined set level voltage, wherein the comparison latch means latches a one-way transition state of the monitoring signal. do.

More preferably, the charging level generating means includes a charging node for providing the charging signal; A predetermined current receiving node; A current supply unit supplying a current to the current receiving node in response to the charging clock signal; An inverting and amplifying unit driving the charging node by inverting and amplifying a signal of the current receiving node with respect to a predetermined bias voltage; And a capacitor group formed between the charging node and the current receiving node and electrically connecting the charging node and the current receiving node in response to the reset clock signal.

For a better understanding of the present invention and its operational advantages, and the objects attained by the practice of the present invention, reference should be made to the accompanying drawings, which illustrate preferred embodiments of the invention, and the accompanying drawings. In understanding each of the figures, it should be noted that like parts are denoted by the same reference numerals whenever possible. Incidentally, detailed descriptions of well-known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention are omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a bandgap reference voltage generation circuit according to an embodiment of the present invention. Referring to FIG. 1, the bandgap reference voltage generator circuit of the present invention includes a bandgap voltage generator 100, a clock generator 200, a charge monitoring unit 300, and a continuous information storage unit 400.

The bandgap voltage generator 100 generates a bandgap reference voltage VBGR. At this time, the level of the bandgap reference voltage VBGR is adjusted by the data value of the received level control data DLCN.

FIG. 2 is a diagram illustrating the bandgap voltage generator 100 of FIG. 1 in detail. Referring to FIG. 2, the configuration of the bandgap voltage generator 100 is as follows.

The bandgap voltage generator 100 may include an output node NOUT, a first spare node NPRE1, a second spare node NPRE2, an output comparator 110, a first resistor 130, and a second resistor 140. ), A first diode 150, a variable resistor 160, and a second diode 170.

The output node NOUT generates the bandgap reference voltage VBGR.

The output comparator 110 receives a signal of the first preliminary node NPRE1 to a negative input terminal and receives a signal of the second preliminary node NPRE2 to a positive input terminal. The output comparator 110 compares the voltage level of the negative input terminal with the voltage level of the positive input terminal to drive the output node NOUT.

The first resistor 130 is formed between the output node NOUT and the first preliminary node NPRE1, and the second resistor 140 is the output node NOUT and the second preliminary node. (NPRE2) is formed between.

One end of the first diode 150 is connected to a ground voltage VSS, and the variable resistor 160 is disposed between the first preliminary node NPRE1 and the other end N151 of the first diode 150. Is formed. The resistance value Rv of the variable resistor 160 is adjusted by the level control data DLN. Since the variable resistor 160 as described above can be easily implemented by those skilled in the art, for the sake of simplicity, a detailed description thereof will be omitted.

The second diode 170 is formed between the ground voltage VSS and the second preliminary node NPRE2. In this embodiment, the amount of current flowing through the first diode 150 is designed to be n times the amount of current flowing through the second diode 170.

Meanwhile, the voltage level Vout of the bandgap reference voltage VBGR generated in the bandgap reference voltage generator 100 having the configuration as shown in FIG. 2 is expressed by Equation 1 below.

[Equation 1]

Vout = V _BE1 + (V _T ln n) (1 + R1 / Rv)

Here, V _BE1 is a voltage level of the base terminal with respect to the voltage of the emitter terminal of the first diode 150, it can be seen that it can be changed according to the change of the process conditions. And V _T is (kT / q), where k is a constant, q represents a unit charge, and T represents a temperature. R1 represents a resistance value of the first resistor 130.

Referring to Equation 1, the voltage level Vout of the bandgap reference voltage VBGR may be adjusted by controlling the resistance value Rv of the variable resistor 150.

That is, even when the V _BE1 changes according to the change of the process condition, if the level control data DLCN is determined to reflect the change of the process condition, the band gap reference voltage VBGR is stabilized regardless of the process condition. It means to be.

Referring back to FIG. 1, the clock generator 200 generates a clock signal group GCLK having a predetermined clock period Tc.

The charge monitoring unit 300 includes a capacitor group GCP, in which the capacitance of the capacitor group GCP is controlled by the capacitance setting data DCST provided from the continuous information storage unit 400. do. In addition, the charge monitoring unit 300 performs 'level adjustment monitoring' according to the capacitance of the capacitor group GCP controlled by the capacitance setting data DCST in each of the plurality of unit monitoring sections P-UM. To perform. The charge monitoring unit 300 generates a monitoring signal XMIT indicating a result of the level control monitoring.

In the present specification, the 'level adjustment monitoring' refers to 'monitoring whether a level of a preset signal according to the capacitance of the capacitor group GCP rises above a predetermined level, and of the monitoring signal XMIT. The logic state represents the result of the 'level adjustment monitoring'.

The timing width of the unit monitoring period P-UM corresponds to the clock period Tc of the clock signal group GCLK. Preferably, the timing width of the unit monitoring period P-UM is equal to the clock period Tc of the clock signal group GCLK.

3 is a view showing in detail the charge monitoring unit 300 of FIG. Referring to FIG. 3, the charge monitoring unit 300 includes a charge level generating unit 310 and a comparison latch unit 360.

The charge level generating means 310 includes the capacitor group GCP and generates a charge signal XCP. In this case, the capacitor group GCP is charged in response to the charging clock signal CCLK included in the clock signal group GCLK, and also responds to the reset clock signal RCLK included in the clock signal group GCLK. Discharged. In addition, the charging signal XCP increases in voltage level as the capacitor group GCP is charged, and resets the voltage level in response to the discharge of the capacitor group GCP.

Specifically, the charging level generating unit 310 includes a charging node NCP, a receiving node NRP, a current supply unit 311, an inverting amplifier unit 313, and a capacitor group RCP.

Through the charging node NCP, the charging signal XCP is provided. The current supply unit 311 supplies a current to the current receiving node NRP in response to the charging clock signal CCLK.

The inversion amplification unit 313 inverts and amplifies the signal of the current receiving node NRP with respect to the bias voltage VBIAS to drive the charging node NRP.

In addition, the capacitor group GCP is formed between the charging node NCP and the current receiving node NRP. The charging node NCP and the current receiving node NRP are electrically connected in response to the reset clock signal RCLK.

In a preferred embodiment, the capacitor group GCP includes a first capacitor 315a, a second capacitor 315b, a third capacitor 315c, and a reset switch 315d.

The first capacitor 315a is formed between the charging node NCP and the current receiving node NRP to couple the charging node NCP to the current receiving node NRP. In the present embodiment, the capacitance of the first capacitor 315a is Cm.

The second capacitor 315b is formed in parallel with the first capacitor 315a between the charging node NCP and the current receiving node NRP. The second capacitor 315b couples the charging node NCP and the current receiving node NRP in response to the first setting bit data DCST <1> included in the capacitance setting data DCST. Let's do it. In the present embodiment, the capacitance of the second capacitor 315b is Cm.

The third capacitor 315c is formed in parallel with the first capacitor 315a and the second capacitor 315b between the charging node NCP and the current receiving node NRP. The third capacitor 315c couples the charging node NCP and the current receiving node NRP in response to the second setting bit data DCST <2> included in the capacitance setting data DCST. Let's do it. In this embodiment, the capacitance of the third capacitor 315c is 2Cm.

The reset switch 315d electrically connects the charging node NCP and the current receiving node NRP in response to the reset clock signal RCLK. That is, the reset switch 315d discharges the charges charged in the first capacitor 315a, the second capacitor 315b, and the third capacitor 315c in response to the reset clock signal RCLK.

3, the comparison latch means 360 compares a voltage level of the charging signal XCP at the time of charging the capacitor group GCP with a predetermined set voltage level VSL, and compares the result. The monitoring signal XMIT having a logic state according to the above is generated. In addition, the comparison latch means 360 latches the monitoring signal (XMIT) that is shifted in one direction. In the present embodiment, the comparison latch means 360 latches the monitoring signal XMIT transitioning from "L" to "H".

Referring back to FIG. 1, the continuous information storage unit 400 may be implemented as a SAR (Successive Approximate Register) that generates the next data based on previously stored data. Preferably, the clock signal group ( In response to the reset clock signal RCLK of GCLK, the level adjustment data DLCN and the capacitance setting data DCST are generated. In this case, the level adjustment data DLCN corresponds to the capacitance setting data DCST for shifting the logic state of the monitoring signal XMIT in one direction (from "L" to "H" in this embodiment). . In the present embodiment, the level adjustment data DLN corresponds to the capacitance setting data DCST that transitions the logic state of the monitoring signal XMIT.

FIG. 4 is a timing diagram for explaining an example of the level adjustment monitoring operation in the bandgap reference voltage generation circuit of FIG. 1 and shows a case of a normal process. Referring to Figure 4, the operation of the reference voltage generating circuit of the present invention will be described.

First, in the first unit monitoring period P-UM <1>, the first setting bit data DCST <1> is “H”, and the second setting bit data DCST <2> is also “H”. to be. In the second unit monitoring period P-UM <2>, the first setting bit data DCST <1> is “L” and the second setting bit data DCST <2> is “H”. to be.

Further, in the third unit monitoring period P-UM <3>, the first setting bit data DCST <1> is “H” and the second setting bit data DCST <2> is “L”. "to be. In the fourth unit monitoring period P-UM <4>, the first setting bit data DCST <1> is “L”, and the second setting bit data DCST <2> is also “L”. to be.

In addition, in each unit monitoring period (P-UM <1> to P-UM <4>), the voltage level of the charging signal XCP increases in response to the generation of the charging clock signal CCLK. In response to the generation of the reset clock signal RCLK, the voltage level of the charging signal XCP is reset.

At this time, when looking at the voltage level of the charge signal (XCP), in the first and second unit monitoring period (P-UM <1> and P-UM <2>), it does not reach the set level voltage (VSL). In this case, the monitoring signal XMIT keeps the "L" state.

On the other hand, in the third unit monitoring period P-UM <3>, the voltage level of the charging signal XCP rises above the set level voltage VSL. In this case, the monitoring signal XMIT is shifted from "L" to "H" and latched.

Accordingly, the first control bit data DLCN <1> and the second control bit data DLCN <2> included in the level control data DLN are determined as “H” and “L”, respectively.

On the other hand, the logic state of the first control bit data (DLCN <1>) and the second control bit data (DLCN <2>) may be determined differently from the example of Figure 4 according to the process conditions.

FIG. 5 is a timing diagram illustrating another example of the level adjustment monitoring operation in the bandgap reference voltage generation circuit of FIG. 1, and illustrates a case of a reduction process.

In the present specification, the “shrinkage process” refers to a process of reducing the area forming the first to third capacitors 315a to 315c. In the reduction process, the capacitances of the first to third capacitors 315a to 315c, that is, the capacitance of the capacitor group GCP, are reduced. In this case, in the second unit monitoring period P-UM <2>, the voltage level of the charging signal XCP rises above the set level voltage VSL.

Therefore, in the reduction process of FIG. 5, the first control bit data DLCN <1> and the second control bit data DLCN <2> are determined as “L” and “H”, respectively.

FIG. 6 is a timing diagram illustrating another example of the level adjustment monitoring operation in the bandgap reference voltage generation circuit of FIG. 1, and illustrates an extension process.

In the present specification, an 'expansion step' means a process of expanding an area forming the first to third capacitors 315a to 315c. In the dean process, the capacitance of the first to third capacitors 315a to 315c, that is, the capacitance of the capacitor group GCP, is increased. In this case, in the third unit monitoring period P-UM <3>, the set level voltage VSL does not reach. In the fourth unit monitoring period P-UM <4>, the voltage level of the charging signal XCP rises above the set level voltage VSL. Therefore, in the expansion process of FIG. 6, the first control bit data DLCN <1> and the second control bit data DLCN <2> are determined as “L” and “L”, respectively.

In the bandgap reference voltage generation circuit of the present invention, the logic states of the first control bit data DLCN <1> and the second control bit data DLCN <2> are as shown in FIGS. 4 to 6. Likewise, it is determined by reflecting changes in process conditions.

In addition, the band gap reference voltage generator 100 may include the first control bit data DLCN <1> and the second control bit data DLCN <2> in which a logic state is determined in response to a change in process conditions. Is provided.

That is, according to the bandgap reference voltage generator of the present invention in which the resistance value Rv of the variable resistor 160 of the bandgap reference voltage generator 100 is controlled by the level control data DLCN, a more stable level is achieved. A bandgap reference voltage of VBGR is provided.

In the bandgap reference voltage generation circuit of the present invention as described above, the bandgap reference voltage VBGR whose voltage level is controlled according to the level adjustment data is generated. The data value of the level adjustment data is determined by reflecting the process conditions.

Therefore, according to the bandgap reference voltage generating circuit of the present invention, the bandgap reference voltage VBGR is provided which is stable to the change of the process conditions.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (6)

In the bandgap reference voltage generation circuit, A bandgap voltage generator for generating a bandgap reference voltage, wherein the level of the bandgap reference voltage is adjusted by level control data; A clock generator generating a clock signal group having a predetermined clock period; In each of the plurality of unit monitoring intervals, the level adjustment monitoring according to the capacitance of the capacitor group controlled by the capacitance setting data is performed, and generates a monitoring signal indicating the result of the level adjustment monitoring, the timing of each unit monitoring interval A width monitoring unit corresponding to a clock period of the clock signal group; And A continuous data storage unit generating the level adjustment data and the capacitance setting data in response to the clock signal group, wherein the capacitance setting data is generated for each unit monitoring period, and the data sequentially controls the capacitance of the capacitor group. The continuous information storage having a value, wherein the level adjustment data includes the continuous information storage having a data value corresponding to the capacitance setting data at which one-way transition of a logic state of the monitoring signal is generated; Gap reference voltage generator circuit. The method of claim 1, wherein the charge monitoring unit A charging level generating means for generating a charging signal, the capacitor group being charged in response to a charging clock signal included in the clock signal group, and responding to a reset clock signal included in the clock signal group; The charge level generating means, the charge signal being increased in accordance with the charging of the capacitor group and the voltage level being reset in response to the discharge of the capacitor group; And Comparative latch means for generating the monitoring signal by comparing the level of the charging signal at the time of charging the capacitor group with a predetermined set level voltage, comprising the comparison latch means for latching a one-way transition state of the monitoring signal. Bandgap reference voltage generation circuit, characterized in that. The method of claim 2, wherein the filling level generating means A charging node providing the charging signal; A predetermined current receiving node; A current supply unit supplying a current to the current receiving node in response to the charging clock signal; An inverting and amplifying unit driving the charging node by inverting and amplifying a signal of the current receiving node with respect to a predetermined bias voltage; And And a capacitor group formed between the charging node and the current receiving node and electrically connecting the charging node and the current receiving node in response to the reset clock signal. The method of claim 3, wherein the capacitor group A first capacitor formed between the charging node and the current receiving node; A second capacitor formed between the charging node and the current receiving node in parallel with the first capacitor and coupling the charging node and the current receiving node in response to first setting bit data included in the capacitance setting data; Capacitors; And And a reset switch electrically connecting the charging node and the current receiving node in response to the reset clock signal. The method of claim 4, wherein the capacitor group The charging node and the current receiving node are formed in parallel with the first capacitor and the second capacitor, and the charging node and the current receiving node are connected in response to the second setting bit data included in the capacitance setting data. And a third capacitor coupled to the bandgap reference voltage generation circuit. The method of claim 1, wherein the band gap voltage generator An output node for generating the bandgap reference voltage; A first spare node; A second spare node; An output comparator that receives a signal of the first spare node at a negative input terminal and receives a signal of the second spare node at a positive input terminal, wherein the voltage level of the negative input terminal is compared with the voltage level of the positive input terminal. The output comparator to drive the output node; A first resistor formed between the output node and the first spare node; A second resistor formed between the output node and the second spare node; A first diode having one end connected to a ground voltage; A variable resistor formed between the first spare node and the other end of the first diode, wherein the variable resistor adjusts a resistance value according to the level control data; And And a second diode formed between the ground voltage and the second spare node.

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