KR20090010272A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20090010272A
KR20090010272A KR1020070073230A KR20070073230A KR20090010272A KR 20090010272 A KR20090010272 A KR 20090010272A KR 1020070073230 A KR1020070073230 A KR 1020070073230A KR 20070073230 A KR20070073230 A KR 20070073230A KR 20090010272 A KR20090010272 A KR 20090010272A
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KR
South Korea
Prior art keywords
pad
film
fuse
forming
semiconductor device
Prior art date
Application number
KR1020070073230A
Other languages
Korean (ko)
Inventor
이민영
Original Assignee
주식회사 하이닉스반도체
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070073230A priority Critical patent/KR20090010272A/en
Publication of KR20090010272A publication Critical patent/KR20090010272A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A method for fabricating semiconductor device is provided to prevent from pad being damaged in the repair / pad etch by forming a pad passivation on the pad. A fuse is formed at the upper part of the fuse regions of the semiconductor substrate in which the fuse regions and pad area are equipped. A first insulating layer(23) is formed in the front side including the fuse. A pad part in which pad and a pad passivation are laminated on is formed on the first insulating layer, and the second insulating layer(27) is formed in the front side including pad part. Forming a hard mask pattern(28) on the second insulating layer, forming the pad open part so that the pad passivation is exposed by the etching barrier wall, and performing a repair etch so that the fuse open part is formed are performed at same time.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can prevent the pad from being damaged during repair / pad etching.

In the manufacture of a semiconductor device, especially a memory device, if any one of a number of cells fails, the memory device does not function as a memory and thus is treated as a defective product. However, in spite of a defect occurring in only some cells in the memory, discarding the entire device as a defective product is an inefficient processing method in terms of yield.

Therefore, when a defect occurs in a semiconductor device, a fuse is used to repair the defective portion. The fuse is not formed by an additional process, but instead is formed by a bit line, a word line, or a plate line of a capacitor. It is formed using a conductive layer forming a (Plate line).

1 is a cross-sectional view illustrating a fuse region and a pad region of a semiconductor device according to the prior art, and FIG. 2 is an image illustrating pad discoloration and pad contamination generated in region “A” of FIG. 1.

1 and 2, a fuse 12 is formed on an upper portion of a fuse region of a semiconductor substrate 11 having a fuse region and a pad region. Subsequently, a first insulating film Intermetal Dielectric (IMD) 13 is formed on the entire surface including the fuse 12. Subsequently, the pad portion 16 on which the pad 14 and the conductive etch stop layer 15 are stacked is formed on the first insulating layer 13 of the pad region. In this case, the pad 14 is formed of a metal-based material such as aluminum film Al, and the conductive etch stop film 15 is formed of aluminum film Al or titanium nitride film TiN.

Subsequently, a second insulating layer 17 is formed on the entire surface including the pad part 16, and a repair etching and a pad etching are simultaneously performed to perform a pad opening part 18 and a fuse opening part ( 19). At this time, the repair etching and the pad etching are simultaneously performed as a target for maintaining the first insulating layer 13 on the fuse 12 in the fuse region at a predetermined thickness.

Here, in the prior art, a silicon oxide film (SiO 2 ) is used as the first insulating film 13 and the second insulating film 17, and a halogen-based gas such as CF 4 is used as an etching gas for etching the silicon oxide film during the repair / pad etching. or Cl 2 gas is used. At this time, the halogen-based gas and Al or Ti constituting the pad portion 16 react with each other to generate a pitting on the surface of the pad portion 16, as shown in FIG. It causes contamination, and there is a problem that the packaging (package) yield is lowered.

In addition, even after the surface of the pad 14 is exposed due to the step between the pad 14 and the fuse 12, the etching process is continued to form the fuse-opening part 18. In this case, the surface of the pad 14 is in a plasma state. There is a problem in that PID (Plasma Induced Damage) occurs. In the case of the triple layer of metal (TLM) structure that is introduced to reduce the chip area, the PID increases the repair etching time as the thickness of the insulating layer increases, thereby increasing the surface of the pad 14. There is a problem in that the exposure time to the plasma is further increased, thereby further damaging the surface of the pad 14 due to the PID.

The present invention has been proposed to solve the problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent a formula from occurring on the pad surface during repair / pad etching.

In addition, another object of the present invention is to provide a method of manufacturing a semiconductor device that can prevent the pad surface from being damaged by PID during repair / pad etching.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a fuse on an upper portion of a fuse region of a semiconductor substrate having a fuse region and a pad region; Forming a first insulating layer on a front surface of the fuse; Forming a pad part having a pad and a pad protection layer stacked on the first insulating layer in the pad area; Forming a second insulating film on the entire surface including the pad part; Forming a hard mask pattern on the second insulating layer and forming a pad opening to expose the surface of the pad protective layer using the hard mask pattern as an etch barrier; and forming the first insulating layer having a predetermined thickness on the fuse. And simultaneously performing repair etching to form the fuse-opening portion to remain. In this case, the pad protective layer is a group consisting of an oxide layer, a nitride layer, an oxynitride, a polysilicon layer, a carbon-containing layer such as an amorphous carbon layer (ACL) or a carbon rich polymer layer (Carbon Rich Polymer). It can be formed of any one selected from.

The repair etching and the pad etching may be performed by plasma etching using a halogen-based gas, and the halogen-based gas may include CF 4 or Cl 2 .

The pad may be formed of an aluminum layer (Al), and the pad part may further include a conductive etch stop layer between the pad and the pad protective layer. In this case, the conductive etch stop layer may be formed of an aluminum film (Al) or a titanium nitride film (TiN).

The present invention may further include forming a crack preventing film on both side walls of the pad opening part and the fuse opening part and the second insulating layer, wherein the crack preventing film may be formed of a polyimide film. have.

The present invention may further include exposing the pad surface by etching the pad protective layer using the crack prevention layer as an etch barrier.

According to the present invention, a pad protective film is formed on the pad, thereby protecting the pad surface from the halogen-based etching gas, thereby preventing the formation of a formula on the pad surface. In addition, by preventing the occurrence of the formula on the pad surface, it is possible to prevent the pad discoloration and pad contamination occurs, thereby improving the packaging yield.

In addition, the present invention by forming a pad protective film on the pad, there is an effect that can be prevented from being damaged on the surface of the pad by the plasma during repair / pad etching.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

As shown in FIG. 3A, a semiconductor substrate 21 having a region in which a fuse is to be formed (hereinafter referred to as a fuse region) and a region in which a pad is formed (hereinafter referred to as a pad region) is formed and a predetermined semiconductor structure is formed according to the semiconductor device. Prepare. In this case, the semiconductor structure may include an isolation layer, a transistor, a bit line, or a capacitor.

Next, a fuse 22 is formed over the fuse region of the semiconductor substrate 21. The fuse 22 may be formed by, for example, a patterning process after forming a conductive film for the upper electrode of the capacitor formed in the cell region to extend to the fuse region, and formed of a polysilicon film or a metal-based material. can do.

Next, a first insulating film 23 is formed on the entire surface of the semiconductor substrate 21 including the fuse 22. In this case, the first insulating layer may be formed of an oxide layer such as silicon oxide (SiO 2 ), boron phosphorus silicate glass (BPSG), phosphorus silicalicate glass (PSG), tetra-ethoxy ortho-silicate (TEOS), un-doped silicate glass (USG), or SOG. It may be formed of any one selected from the group consisting of (Spin On Glass), High Density Plasma Oxide (HDP) and SOD (Spin On Dielectric).

Next, the pad 24, the conductive etch stop layer 25, and the pad protective layer 26 are sequentially formed on the first insulating layer 23. In this case, the pad 24 may be formed of a metal-based material such as an aluminum film (Al), the conductive etch stop layer 25 may be formed of an aluminum film (Al) or titanium nitride film (TiN), the pad protective film (26) is any selected from the group consisting of an oxide film series, a nitride film series, an oxynitride, a carbon-containing film such as an amorphous carbon film (ACL) or a carbon rich polymer film and a polysilicon film. The material may be formed of one, and any material having an etching selectivity with the first insulating layer 23 may be used.

As shown in FIG. 3B, after the photoresist pattern is formed on the pad protection layer 26, the pad protection layer 26, the conductive etch stop layer 25, and the pad 24 are formed using the photoresist pattern as an etch barrier. Are sequentially etched to form a pad portion having a structure in which the pad 24A, the conductive etch stop film 25A, and the pad protective film 26A are stacked in the pad area.

Next, a second insulating film 27 is formed on the entire surface including the pad portion. In this case, the second insulating layer 27 may be formed of an oxide layer such as silicon oxide (SiO 2 ), boron phosphorus silicate glass (BPSG), phosphorus silicalicate glass (PSG), tetra-ethoxy ortho-silicate (TEOS), or un-doped silicate glass (USG). ), SOG (Spin On Glass), High Density Plasma (HDP) and SOD (Spin On Dielectric), and any one selected from the group consisting of, preferably repair / pad etching process easier In order to proceed, it is preferable to form the same material as the first insulating film (23).

Next, a hard mask pattern 28 having an opening corresponding to the pad portion and the fuse 22 is formed on the second insulating layer 27. In this case, the hard mask pattern 28 may be formed of any one selected from the group consisting of an oxide film series, a nitride film series, a nitride oxide film, a polysilicon film, and a carbon-containing film such as an amorphous carbon film or a carbon rich polymer film. 23) and any material having an etching selectivity with the second insulating film 27 can be used.

As illustrated in FIG. 3C, a pad etch forming the pad opening portion 29 to expose the surface of the pad protection layer 26A using the hard mask pattern 28 as an etch barrier and a predetermined thickness on the fuse 22. The repair etching for forming the fuse-opening part 30 is performed at the same time so that the insulating film 23 remains. In this case, the repair / pad etching is a target for maintaining the first insulating layer 23 on the fuse 22 in the fuse region at a predetermined thickness, for example, a halogen-based gas such as CF 4. or It can be carried out by a plasma etching method using Cl 2 gas.

Here, the pad 24A and the conductive etch stop layer are formed due to the pad protection layer 26A formed on the uppermost layer of the pad portion during the repair / pad etching process as a target for maintaining the first insulating layer on the fuse in the fuse region. 25A) is protected from halogen-based etching gas and plasma.

As shown in FIG. 3D, a crack prevention layer 31 is formed on both side walls of the fuse open unit 30 and the pad open unit 29 and the second insulating layer 27. At this time, the crack prevention layer 31 is to prevent cracks from occurring at both edges of the fuse-opening part 30 due to stress generated in a subsequent packaging process, and is made of polyimide. Can be formed.

Next, the surface of the conductive etch stop layer 25A is exposed by etching the pad protection layer 26A in the pad region using the crack prevention layer 31 as an etch barrier. In this case, the conductive etch stop layer 25A serves to prevent the pad 24A from being etched when the pad protective layer 26A is etched.

Through the above-described process, the fuse 22 and the pad 24A of the semiconductor device may be formed without damaging the pad 24A.

As described above, according to the present invention, by forming a pad protective film on the pad, it is possible to prevent the halogen-based gas and the pad from reacting with each other to generate a formula on the pad surface. In addition, by preventing the formation of the formula on the pad surface, it is possible to prevent the pad discoloration and pad contamination occurs, thereby improving the packaging yield.

In addition, by forming a pad protection layer on the pad, it is possible to prevent the pad surface from being exposed to the plasma during the repair etching for forming the fuse open portion, thereby preventing the pad surface from being damaged by the plasma. have. In particular, as the TLM structure introduced to reduce the chip area, the thickness of the insulating layer is increased to prevent the pad surface from being damaged by the pad protection layer formed on the pad even if the repair etching time is increased compared to the DLM structure. .

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1 is a cross-sectional view illustrating a fuse region and a pad region of a semiconductor device according to the related art.

FIG. 2 is an image showing pad discoloration and pad contamination in region “A” of FIG. 1. FIG.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

21 semiconductor substrate 22 fuse

23: first insulating film 24: pad

25: conductive etch stop film 26: pad protective film

27: second insulating film 28: hard mask pattern

29: pad opening portion 30: fuse opening portion

31: crack prevention film

Claims (14)

Forming a fuse on the fuse area of the semiconductor substrate including the fuse area and the pad area; Forming a first insulating layer on a front surface of the fuse; Forming a pad part having a pad and a pad protection layer stacked on the first insulating layer in the pad area; Forming a second insulating film on the entire surface including the pad part; Forming a hard mask pattern on the second insulating layer; And A pad etch forming a pad opening portion to expose the surface of the pad protective layer using the hard mask pattern as an etch barrier and a repair etching process for forming a fuse opening portion to leave the first insulating layer having a predetermined thickness on the fuse may be performed. step Method of manufacturing a semiconductor device comprising a. The method of claim 1, The pad protective film is a semiconductor device manufacturing method of any one selected from the group consisting of oxide film series, nitride film series, oxynitride (oxynitride), carbon containing film, polysilicon film. The method of claim 2, The carbon-containing film is a method of manufacturing a semiconductor device including an amorphous carbon film (Amorphous Carbon Layer, ACL) or a carbon rich polymer film (Carbon Rich Polymer). The method of claim 1, The repair etching and the pad etching are performed using a halogen-based gas. The method of claim 4, wherein The halogen-based gas manufacturing method of a semiconductor device comprising CF 4 or Cl 2 . The method of claim 1, The repair and pad etching is a plasma etching method of manufacturing a semiconductor device. The method of claim 1, The pad is a semiconductor device manufacturing method of forming an aluminum film (Al). The method of claim 1, The pad part further comprises a conductive etch stop layer between the pad and the pad protective layer. The method of claim 8, The conductive etch stop film is formed of an aluminum film (Al) or titanium nitride film (TiN) of the semiconductor device manufacturing method. The method of claim 1, And forming a crack prevention film on both sidewalls of the pad opening portion and the fuse opening portion and the second insulating layer. The method of claim 10, The crack preventing film is a semiconductor device manufacturing method of forming a polyimide (Polyimide). The method of claim 10, And etching the pad protective layer using the crack prevention layer as an etch barrier to expose a pad surface. The method of claim 1, And the first insulating film and the second insulating film are formed of an oxide film. The method of claim 13, The oxide film is silicon oxide (SiO 2 ), BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), TEOS (Tetra Ethyle Ortho Silicate), USG (Un-doped Silicate Glass), SOG (Spin On Glass), high density A method of manufacturing a semiconductor device, which is formed by any one selected from the group consisting of high density plasma (HDP) and spin on dielectric (SOD).
KR1020070073230A 2007-07-23 2007-07-23 Method for fabricating semiconductor device KR20090010272A (en)

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KR1020070073230A KR20090010272A (en) 2007-07-23 2007-07-23 Method for fabricating semiconductor device

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