KR20090007119A - Method of operating a non-volatile memory device - Google Patents

Abstract

An operation method of nonvolatile memory device is provided to rapidly stabilize data recorded in a memory cell by inducing a boosting voltage to a channel of the memory cell. Data is recorded by supplying a program voltage to a memory cell selected among a plurality of memory cells(S110). The recorded data is stabilized(S120). Injection quantity of electron is determined by measuring a current flowed in the memory cell. Data recording quantity is verified according to the decision result. The stabilized data is verified(S130). A program completion is determined(S140). A program voltage is increased in case a program is not completed(S150). A total process is repeated by using an increased program voltage.

Description

Method of operating a non-volatile memory device

The present invention relates to a semiconductor device, and more particularly to a method of operating a nonvolatile memory device.

Nonvolatile memory devices, such as EEPROM or flash memory, can retain data even when the power is turned off, and can further program the data. Such a nonvolatile memory device may be used in a semiconductor product such as a storage medium of a mobile device or a portable memory stick.

1 is a graph illustrating a distribution of threshold voltages during a program operation of a nonvolatile memory device.

Referring to FIG. 1, it can be seen that after writing data, it takes a considerable time until the threshold voltage V _th becomes constant. After recording the data, the threshold voltage V _th decreases significantly and gradually becomes saturated. It can be seen that when about 40 microseconds have passed, the threshold voltage V _th is about 0.1 V lower than when saturated, and at about 500 V, about 0.01 V lower than when saturated. Accordingly, the threshold voltage V _th may vary depending on the time from the data to the data verification.

In an ISPP (incremental step pulse program) program, such a distribution of threshold voltages V _th may reduce the reliability of data verification, and may misread a program completion. As a result, program reliability can be greatly reduced.

Therefore, in order to improve the operational reliability of the nonvolatile memory device, it is necessary to reduce the distribution of the threshold voltage after data writing. In particular, for fast operation of the nonvolatile memory device, it is necessary to quickly saturate the threshold voltage after the write operation.

Accordingly, an object of the present invention is to provide a method of operating a nonvolatile memory device having high operating speed and high reliability of program operation.

A method of operating a nonvolatile memory device of one embodiment of the present invention for achieving the above technical problem is provided. The nonvolatile memory device includes a plurality of memory cells disposed in a NAND structure between a common source line and a plurality of bit lines on a semiconductor substrate. Data is written to a selected memory cell among the plurality of memory cells. A boosting voltage is induced to a channel of the selected memory cell through a channel of one or more memory cells adjacent to the selected memory cell among the plurality of memory cells to stabilize the written data. Then, the data is verified.

According to an example of a method of operating the nonvolatile memory device, inducing the boosting voltage may include applying a pass voltage to one or more word lines coupled to the one or more memory cells connected adjacent to the selected memory cell. And the boosting voltage may be capacitively derived from the pass voltage.

According to another example of a method of operating the nonvolatile memory device, inducing the boosting voltage may include applying a first voltage to the plurality of bit lines, selecting the selected memory cell and the plurality of memory cells from among the plurality of memory cells. The memory cells disposed between the bit lines may be turned on.

According to another example of a method of operating the nonvolatile memory device, inducing the boosting voltage may include applying a second voltage to the common source line, and selecting the selected memory cell and the common source from among the plurality of memory cells. Memory cells disposed between the lines may be turned on.

There is provided a method of operating a nonvolatile memory device according to another aspect of the present invention for achieving the above technical problem. Data is written to a selected memory cell among the plurality of memory cells. In the state where the selected memory cell is turned off, a boosting voltage is induced to a channel of the selected memory cell from the plurality of bit lines or the common source line to stabilize the written data. Then, the data is verified.

According to another aspect of the present invention, there is provided a method of operating a nonvolatile memory device. Data is written to a selected memory cell among the plurality of memory cells. The selected memory is selected from one or more memory cells connected to the selected memory cell among the plurality of memory cells without using the plurality of bit lines and the common source line while the selected memory cell is turned off. The boosted voltage is capacitively induced in the channel of the cell to stabilize the recorded data. Then, the data is verified.

According to the method of operating a nonvolatile memory device according to the present invention, data written in a memory cell can be stabilized quickly by inducing a boosting voltage to a channel of the memory cell. Therefore, since the threshold voltage of the memory cell is constantly saturated, the verification reliability of the data can be increased. Thus, the reliability of the data program for the memory cell can be increased.

In addition, according to the operating method of the nonvolatile memory device according to the present invention, the boosting voltage can be induced quickly within several to several hundred microseconds. Therefore, the method of operating the nonvolatile memory device according to the present invention may be suitable for the operation of the nonvolatile memory device requiring high speed operation.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. In the drawings, the components may be exaggerated in size for convenience of description.

In embodiments of the present invention, the nonvolatile memory device may include a device capable of writing data using charge storage, such as EEPROM or a flash memory device. In embodiments of the present invention, the nonvolatile memory device may have a stacked structure with a charge storage layer interposed between the semiconductor substrate and the control gate electrode, where the charge storage layer may be used as a floating gate or charge trap layer. have.

In embodiments of the present invention, the operating conditions of the nonvolatile memory device are presented by way of example. In addition, applying 0V under operating conditions of the nonvolatile memory device may be understood as the same meaning as grounding.

2 is a flowchart illustrating a method of operating a nonvolatile memory device according to an embodiment of the present invention. 3 is a graph illustrating a change in voltage over time in a method of operating a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, data may be written by applying a program voltage to a selected memory cell among a plurality of memory cells (S110). For example, such data writing may be performed by applying a program voltage V _pgm to a control gate electrode for a time from t1 to t2 as shown in FIG. 3. Accordingly, electrons can be injected into the charge storage layer from the semiconductor substrate by using Fouler-Nordheim (FN) tunneling.

Then, the recorded data can be stabilized (S120). For example, as illustrated in FIG. 3, a boosting voltage V _channel may be applied to a channel of a selected memory cell for a time t3 to t4 (where t3 ≧ t2). Accordingly, the threshold voltage of the memory cell selected by the boosting voltage V _channel may be rapidly saturated. That is, since the boosting voltage V _channel has the opposite polarity to the data write condition, the change induced in the memory cell selected by the write operation can be quickly removed.

For example, the boosting voltage V _channel may contribute to quickly eliminating dipole moments in the tunneling or blocking insulating layer between the control gate electrode and the semiconductor substrate. In addition, the boosting voltage V _channel may be stabilized by rapidly redistributing the charge injected into the charge storage layer. Accordingly, the threshold voltage of the selected memory cell may be saturated quickly.

Subsequently, the stabilized data may be verified (S130). For example, as illustrated in FIG. 3, a verify voltage V _verify may be applied to a control gate electrode of a selected memory cell for a time t5 to t6 (but t5 ≧ t4). Accordingly, by measuring the current flowing through the selected memory cell, the degree of injection of electrons can be determined to verify the degree of data writing. Since the threshold voltage is constantly saturated in the above-described stabilization step (S120), verification reliability of data may be increased. Therefore, the reliability of the data program operation can be increased.

Then, it may be determined whether the program is completed (S140). Whether the program is completed can be known from the result of the above-described data verification step S130. Subsequently, when the program is completed, the program operation may be terminated.

 If the program is not completed, it is possible to increase the program voltage (S150). Subsequently, the above-described steps S110 to S140 may be repeated. As such, the method of proceeding the program while increasing the program voltage may be referred to as an incremental step pulse program (ISPP) method.

Hereinafter, the above-described operating method will be described in more detail with reference to a nonvolatile memory device having a NAND structure.

4 is a circuit diagram illustrating a data writing step in a method of operating a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 4, NAND memory cells MC may be connected between the bit lines BL0, BL1, and BL2 and the common source line CSL. The word lines WL00, WL01, WL02, WL03, WL04, and WL05 may be arranged in a row and may be connected to the control gate electrodes of the memory cells MC so as to be coupled to the memory cells MC. The number of memory cells MC, the number of bit lines BLO, BL1, BL2 and the number of word lines WL00, WL01, WL02, WL03, WL04, WL05 may be appropriately selected, and according to the present invention. Do not limit the range.

The string select transistors T _SS may be connected between the bit lines BL0, BL1, BL2 and one end of the memory cells MC, for example, between the bit lines BL0, BL1, BL2, and the word line WL05. have. The string select lines SSL may be arranged in rows and may be coupled to the string select transistors T _SS . The ground select transistors T _GS may be connected between the common source line CSL and the other end of the memory cells MC, for example, between the common source line CSL and the word line WL00. The ground select lines GSL may be arranged in a row and may be coupled to the ground select transistors T _GS .

In order to write data in the selected memory cell MC1 indicated by a dotted line, 0 V may be applied to the selected bit line BL1, and an operating voltage Vcc may be applied to the unselected bit lines BL0 and BL2. . An operating voltage Vcc may be applied to the string select line SSL to turn on the string select transistor T _SS . 0V may be applied to the ground select line GSL and the common source line CSL. The program voltage V _pgm may be applied to the selected word line WL02, and a pass voltage V _pass may be applied to the remaining word lines WL0, WL1, WL03, WL04, and WL05.

Accordingly, the program voltage V _pgm is induced between the channel and the control gate electrode of the selected memory cell MC1, and tunneling of charge from the channel to the charge storage layer may occur. Therefore, data can be written in the selected memory cell MC1. The pass voltage V _pass may be selected so that tunneling from the channel to the charge storage layer does not occur while turning on the memory cells MC. Therefore, the pass voltage V _pass may be smaller than the program voltage V _pgm . The program voltage V _pgm and the pass voltage V _pass may be appropriately selected according to the memory cells MC.

Meanwhile, the boosting voltage may be induced by the operating voltage Vcc in the channel of the memory cells MC connected to the unselected bit lines BL0 and BL2. Therefore, the program of the memory cells MC coupled to the selected word line WL02 may be prevented.

 The above-described data recording step is presented as an example, and may be variously modified according to methods known to those skilled in the art.

5 is a circuit diagram illustrating a data stabilization step in a method of operating a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 5, 0 V is applied to the string select line SSL to turn off the string select transistor T _SS , and a ground select line GSL is turned off to turn off the ground select transistor T _GS . You can apply 0V to. Accordingly, the memory cells MC may be floated on the bit lines BL0, BL1, BL2, and the common source line CSL.

0V may be applied to the selected word line WL02 to turn off the selected memory cell MC1. A pass voltage V _pass may be applied to two pairs of word lines WL00, WL01, WL03, and WL04 adjacent to and selected from the selected word line WL02. Accordingly, the voltage of the channel of the memory cells MC capacitively coupled with the _pass voltage V _pass is increased, and the boosting voltage is applied to the channel of the selected memory cell MC1 disposed between the memory cells MC. Can be induced. As described above with reference to FIG. 2, the boosting voltage saturates the threshold voltage of the selected memory cell MC1 to stabilize the data quickly.

6 is a perspective view by simulation of a data stabilization step of a nonvolatile memory device according to an embodiment of the present invention. FIG. 7 is a graph illustrating channel voltages depending on channel positions of the nonvolatile memory device of FIG. 6.

Referring to FIG. 6, 0 V is applied to the string select line SSL and the ground select line GSL. 0 V was applied to the selected word line WL2 and 8 V was applied to the unselected word lines WL0, WL1, WL3, and WL4 as pass voltages. The semiconductor substrate on which memory cells are formed is grounded (V _sub = 0V).

Referring to FIG. 7, it can be seen that a voltage of about 3.5 V is capacitively induced in a channel of memory cells coupled to unselected word lines WL0, WL1, WL3, and WL4. In addition, it can be seen that a boosting voltage in a range of about 1.8 to about 2.2 V is induced in a channel of the memory cell coupled to the selected word line WL2. Such induction of boosting voltage may be referred to as local self boosting (LSB).

Since the induction of the boosting voltage occurs between the channels, the boosting voltage may occur in a much faster time than when the boosting voltage is supplied through the semiconductor substrate. For example, the boosting voltage can be induced quickly within a few to several hundred microseconds. Thus, the induction of such boosting voltage may be suitable for the operation of nonvolatile memory devices that require high speed operation.

8 to 13 are circuit diagrams showing modified examples of a data stabilization step of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 8, a pass voltage V _pass may be applied to only a pair of word lines WL01 and WL03 disposed on both sides immediately adjacent to the selected word line WL02. Accordingly, the voltage of the channel of the memory cells MC capacitively coupled with the _pass voltage V _pass is increased, and the boosting voltage is applied to the channel of the selected memory cell MC1 disposed between the memory cells MC. Can be induced.

The pass voltage V _pass may be further applied to other word lines WL00, WL04, and WL05, including the pair of word lines WL01 and WL03. For example, the pass voltage V _pass may be provided to at least one pair adjacent to both sides of the selected word line WL02 among the unselected word lines WL00, WL01, WL03, WL04, and WL05.

Referring to FIG. 9, an operating voltage Vcc (also referred to as a second voltage) may be applied to the common source line CSL. An operating voltage Vcc is applied to the ground select line GSL to apply a 0 V to the string select line SSL to turn off the string select transistor T _SS , and to turn on the ground select transistor T _GS . Can be applied. Accordingly, the operating voltage Vcc may be transferred to the memory cells MC through the ground select transistor T _GS .

0V may be applied to the selected word line WL02 to turn off the selected memory cell MC1. The pass voltage V _pass may be applied to the unselected word lines WL00, WL01, WL03, WL04, and WL05. Accordingly, the voltage of the channel of the memory cells MC coupled to the word lines WL00 and WL01 may increase momentarily, boosting the channel of the selected memory cell MC1 adjacent to the memory cells MC. Voltage can be induced. As described above with reference to FIG. 2, the boosting voltage saturates the threshold voltage of the selected memory cell MC1 to stabilize the data quickly.

In this embodiment, the boosting voltage can be distinguished from the local self boosting of FIG. 5 in that it is derived from the operating voltage Vcc applied to the common source line CSL. Meanwhile, in another modified example of this embodiment, the pass voltage V _pass may not be applied to the word lines WL03, WL04, and WL05 on the selected word line WL02. This is because the boosting voltage is not provided from the bit lines BL0, BL1, and BL2.

Referring to FIG. 10, an operating voltage Vcc (which may be referred to as a first voltage) may be applied to the bit lines BL0, BL1, and BL2. An operating voltage Vcc is applied to the string select line SSL to turn on the string select transistor T _SS , and 0 V is applied to the ground select line GSL to turn off the ground select transistor T _GS . Can be applied. Accordingly, the operating voltage Vcc may be transferred to the memory cells MC through the string select transistor T _SS .

0V may be applied to the selected word line WL02 to turn off the selected memory cell MC1. The pass voltage V _pass may be applied to the unselected word lines WL00, WL01, WL03, WL04, and WL05. Accordingly, the voltage of the channel of the memory cells MC coupled to the word lines WL03, WL04, and WL05 may increase momentarily, and the channel of the selected memory cell MC1 adjacent to the memory cells MC may increase. The boosting voltage can be induced. As described above with reference to FIG. 2, the boosting voltage saturates the threshold voltage of the selected memory cell MC1 to stabilize the data quickly.

This embodiment can be distinguished from the embodiment of FIG. 9 in that the boosting voltage is derived from the operating voltage Vcc applied to the bit lines BL0, BL1, BL2. In another modified example of this embodiment, the pass voltage V _pass may not be applied to the word lines WL00 and WL01 under the selected word line WL02. This is because the boosting voltage is not provided from the common source line CSL.

Referring to FIG. 11, the first voltage V _bl may be applied to the bit lines BL0, BL1, and BL2. The third voltage V _ssl is applied to the string select line SSL to turn on the string select transistor T _SS , and the ground select line GSL is turned off to turn off the ground select transistor T _GS . You can apply 0V to. The third voltage V _ssl may be greater than or equal to the first voltage V _bl . Accordingly, the first voltage V _bl may be transferred to the memory cells MC through the string select transistor T _SS .

0V may be applied to the selected word line WL02 to turn off the selected memory cell MC1. A pass voltage V _pass may be applied to unselected word lines WL03, WL04, and WL05 between the string select line SSL and the selected word line WL02. 0V may be applied to the other unselected word lines WL00 and WL01 below the selected word line WL02. Accordingly, the voltage of the channel of the memory cells MC coupled to the word lines WL03, WL04, and WL05 may increase, and boost the channel of the selected memory cell MC1 adjacent to the memory cells MC. Voltage can be induced. As described above with reference to FIG. 2, the boosting voltage saturates the threshold voltage of the selected memory cell MC1 to stabilize the data quickly.

This embodiment is similar to the embodiment of FIG. 9 in that the boosting voltage is derived from the bit lines BL0, BL1, BL2. However, this embodiment may be different from the embodiment of FIG. 9 in that the first voltage V _bl and the third voltage V _ssl may be different.

Referring to FIG. 12, a second voltage V _csl may be applied to the common source line CSL. Applying OV to the string select line SSL to turn off the string select transistor T _SS and a fourth voltage V to the ground select line GSL to turn on the ground select transistor T _GS . _gsl ) can be applied. The fourth voltage V _gsl may be greater than or equal to the second voltage V _csl . Accordingly, the second voltage V _csl may be transferred to the memory cells MC through the ground select transistor T _GS .

0V may be applied to the selected word line WL02 to turn off the selected memory cell MC1. A pass voltage V _pass may be applied to the unselected word lines WL00 and WL01 between the ground select line GSL and the selected word line WL02. 0V may be applied to the other unselected word lines WL03, WL04, and WL05 on the selected word line WL02. Accordingly, the voltage of the channel of the memory cells MC coupled to the word lines WL00 and WL01 may increase, and the boosting voltage may be increased in the channel of the selected memory cell MC1 adjacent to the memory cells MC. This can be induced. As described above with reference to FIG. 2, the boosting voltage saturates the threshold voltage of the selected memory cell MC1 to stabilize the data quickly.

This embodiment is similar to the embodiment of FIG. 10 in that the boosting voltage is derived from the common source line CSL. However, this embodiment may be different from the embodiment of FIG. 10 in that the second voltage V _csl and the fourth voltage V _gsl may be different.

Referring to FIG. 13, the first voltage V _bl may be applied to the bit lines BL0, BL1, and BL2, and the second voltage V _csl may be applied to the common source line CSL. The third voltage V _ssl is applied to the string select line SSL to turn on the string select transistor T _SS , and the ground select line GSL is turned on to turn on the ground select transistor T _GS . The fourth voltage V _gsl may be applied to the fourth voltage V _gsl . Accordingly, the first voltage V _bl is transferred to the memory cells MC through the string select transistor T _SS , and the second voltage V _csl is transferred to the memory cells MC through the ground select transistor T _GS . Can be delivered.

0V may be applied to the selected word line WL02 to turn off the selected memory cell MC1. The pass voltage V _pass may be applied to the unselected word lines WL00, WL01, WL03, WL04, and WL05. Accordingly, the voltage of the channel of the memory cells MC coupled to the word lines WL00, WL01, WL03, WL04, and WL05 may increase, and the selected memory cell MC1 adjacent to the memory cells MC may increase. A boosting voltage can be induced in the channel of. As described above with reference to FIG. 2, the boosting voltage saturates the threshold voltage of the selected memory cell MC1 to stabilize the data quickly.

14 is a circuit diagram illustrating a modified example of the nonvolatile memory device of FIGS. 4 to 13.

Referring to FIG. 14, the first dummy line DL1 is interposed between the ground select line GSL and the word line WL00, and the second dummy line DL2 is the string select line SSL and the word line WL05. May be intervened). The first and second dummy lines DL1 and DL2 may be coupled to the dummy transistors T _D. The dummy transistors T _D may have the same or similar structure as the memory cells MC, but may not be used for data writing.

For example, the dummy transistors T _D may be used when data stabilization is performed by selecting memory cells MC at edges coupled with the word lines WL00 and WL03. By providing a _pass voltage V _pass to the first and / or second dummy lines DL1 and DL2, a boosting voltage may be effectively provided to the memory cells MC at the edge. The operation of the nonvolatile memory device of FIG. 12 may refer to the operations of the nonvolatile memory device of FIGS. 5 to 13.

The foregoing description of specific embodiments of the invention has been presented for purposes of illustration and description. The present invention is not limited to the above embodiments, and it is apparent that many modifications and changes can be made in the technical spirit of the present invention by those having ordinary skill in the art in combination. .

1 is a graph showing a distribution of threshold voltages in a program operation of a nonvolatile memory device;

2 is a flowchart illustrating a method of operating a nonvolatile memory device according to an embodiment of the present invention;

3 is a graph showing a change in voltage over time in a method of operating a nonvolatile memory device according to an embodiment of the present invention;

4 is a circuit diagram showing a data writing step in a method of operating a nonvolatile memory device according to an embodiment of the present invention;

5 is a circuit diagram illustrating a data stabilization step in a method of operating a nonvolatile memory device according to an embodiment of the present invention;

6 is a perspective view by simulation of a data stabilization step of a nonvolatile memory device according to an embodiment of the present invention;

FIG. 7 is a graph showing channel voltages depending on channel positions of the nonvolatile memory device of FIG. 6; FIG.

8 to 13 are circuit diagrams showing modified examples of a data stabilization step of a nonvolatile memory device according to an embodiment of the present invention; And

14 is a circuit diagram illustrating a modified example of the nonvolatile memory device of FIGS. 4, 5, and 8 through 13.

Claims (25)

A method of operating a nonvolatile memory device including a plurality of memory cells disposed in a NAND structure between a common source line and a plurality of bit lines on a semiconductor substrate, Writing data to a selected memory cell among the plurality of memory cells; Stabilizing the written data by inducing a boosting voltage to a channel of the selected memory cell through a channel of one or more memory cells adjacent to the selected memory cell among the plurality of memory cells; And And verifying the data. The method of claim 1, wherein the stabilizing of the written data rapidly redistributes the charge injected into the charge storage layer of the selected memory cell. The method of claim 1, wherein in the stabilizing of the written data, the selected memory cell is turned off. The method of claim 3, wherein turning off the selected memory cell is performed by applying 0 V to a word line coupled to the selected memory cell. The method of claim 1, wherein the stabilizing of the written data is performed within several to several hundred microseconds. The method of claim 1, wherein in the stabilizing of the written data, the semiconductor substrate is grounded. The method of claim 1, wherein inducing the boosting voltage comprises applying a pass voltage to one or more word lines coupled to the one or more memory cells coupled adjacent to the selected memory cell, wherein the boosting voltage is applied to the boosting voltage. A method of operating a nonvolatile memory device, characterized in that it is capacitively derived from a pass voltage. 8. The memory device of claim 7, wherein the one or more memory cells comprise one or more pairs of memory cells coupled to both sides of the selected memory cell, wherein the one or more word lines are one or more pairs of word lines coupled to the one or more pairs of memory cells. Method of operating a nonvolatile memory device comprising a. 8. The method of claim 7, wherein the deriving of the boosting voltage comprises: a string select transistor connected between the plurality of bit lines and one end of the plurality of memory cells, and between the common source line and the other end of the plurality of memory cells. Turning off the ground select transistor coupled to the method of operating a non-volatile memory device. 10. The method of claim 9, wherein turning off the string select transistor and ground select transistor comprises applying 0V to a string select line coupled to the string select transistor and a ground select line coupled to the ground select transistor. A method of operating a nonvolatile memory device characterized by the above-mentioned. The method of claim 1, wherein the deriving of the boosting voltage comprises: applying a first voltage to the plurality of bit lines, and between the selected memory cell and the plurality of bit lines among the plurality of memory cells. A method of operating a nonvolatile memory device comprising turning on memory cells. 12. The method of claim 11, wherein turning on the memory cells applies a pass voltage to word lines coupled to the memory cells. 12. The operation of claim 11, further comprising turning on a string select transistor between each of the plurality of bit lines and one end of the plurality of memory cells in inducing the boosting voltage. Way. The operation of claim 13, wherein turning on the string select transistor applies a voltage greater than or equal to the first voltage to a string select line coupled to the string select transistor. Way. The method of claim 1, wherein the deriving of the boosting voltage comprises applying a second voltage to the common source line and turning on the selected memory cell among the plurality of memory cells and the memory cells disposed between the common source line. -On the method of operating a non-volatile memory device, characterized in that. 16. The method of claim 15, wherein turning on the memory cells applies a pass voltage to word lines coupled to the memory cells. 16. The method of claim 15, further comprising turning on a ground select transistor between the common source line and the other end of the plurality of memory cells in inducing the boosting voltage. 18. The operation of claim 17, wherein turning on the ground select transistor applies a voltage greater than or equal to the second voltage to a ground select line coupled to the ground select transistor. Way. The method of claim 1, wherein the deriving of the boosting voltage comprises: applying a first voltage to the plurality of bit lines, applying a second voltage to the common source line, and selecting the selected memory cell from among the plurality of memory cells. A method of operating a nonvolatile memory device, characterized in that to turn on the remaining memory cells except the cell. 20. The method of claim 19, wherein inducing the boosting voltage further turns on a string select transistor between the plurality of bit lines and one end of the plurality of memory cells, and further comprises turning on the common source line and the plurality of memories. And further turning on a ground select transistor between the other ends of the cells. 21. The operation of claim 20, wherein turning on the string select transistor applies a voltage greater than or equal to the first voltage to a string select line coupled to the string select transistor. Way. 21. The operation of claim 20, wherein turning on the ground select transistor applies a voltage greater than or equal to the second voltage to a ground select line coupled to the ground select transistor. Way. The memory device of claim 1, wherein the nonvolatile memory device further comprises a dummy select transistor connected between the common source line and the plurality of memory cells or between the plurality of bit lines and the plurality of memory cells. And turning on the dummy transistor in the data stabilization step. A nonvolatile memory device including a plurality of memory cells arranged in a NAND structure between a common source line and a plurality of bit lines on a semiconductor substrate. Writing data to a selected memory cell among the plurality of memory cells; Stabilizing the written data by inducing a boosting voltage to a channel of the selected memory cell from the plurality of bit lines or the common source line while the selected memory cell is turned off; And And verifying the data. A nonvolatile memory device including a plurality of memory cells arranged in a NAND structure between a common source line and a plurality of bit lines on a semiconductor substrate. Writing data to a selected memory cell among the plurality of memory cells; The selected memory is selected from one or more memory cells connected to the selected memory cell among the plurality of memory cells without using the plurality of bit lines and the common source line while the selected memory cell is turned off. Stabilizing the recorded data by capacitively inducing a boosting voltage in a channel of a cell; And And verifying the data.

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