KR20090005591A - Liquid crystal dispaly and driving method thereof - Google Patents

Abstract

A liquid crystal display driving method thereof are provided to prevent open of output terminal by discharging input electric charges increasing a gate voltage of a transistor of an output buffer part. A node controller(110) controls a charging/discharging of a first node(n1) and a second node(n2), and includes a first to a third transistors(T1-T3) controlling the charging/discharging the first node and a fourth to a sixth transistors(T4-T6) controlling the charging/discharging the second node. An output buffer part(120) outputs a common low voltage(VCOML) or a common high voltage(VCOMH) according to the first node and the second node, and includes a seventh transistor(T7), an eighth transistor(T8), a first capacitor(C1), and a second capacitor(C2). A refresh part(130) prevents increase of a gate voltage of the output buffer part, and includes a ninth transistor(T9), a tenth transistor(T10), a plurality of eleventh transistors(T11), a plurality of twelfth transistors(T12), a third capacitor(C3), and a fourth capacitor(C4).

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPALY AND DRIVING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a driving method thereof, and more particularly, to a liquid crystal display and a driving method thereof capable of preventing an increase in the gate voltage of the output buffer unit.

A liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in an active matrix form, and a driving circuit for driving the liquid crystal display panel.

The driving circuit includes a gate driving circuit for driving the gate line of the liquid crystal panel, a data driving circuit for driving the data line of the liquid crystal panel, and a common electrode driving circuit for driving the common electrode of the liquid crystal cell.

As shown in FIG. 1, the common electrode driving circuit includes a node control unit including a plurality of PMOS transistors to control charge and discharge states of the first and second nodes n1 and n2 and a voltage on the first node n1. The first PMOS transistor T1 is switched and the second PMOS transistor T2 is switched according to the voltage on the second node n2.

Here, the plurality of PMOS transistors constituting the node control unit and the first and second PMOS transistors T1 and T2 have large leakage currents, and when the channel is exposed to light, when the threshold voltage shifts in the positive direction along with the increase in the photocurrent. The leakage current is increased by the plurality of transistors forming the node controller. In addition, the leakage current causes the voltages of the first and second nodes n1 and n2 to fluctuate, that is, rise, thereby turning off the first and second PMOS transistors T1 and T2 that must selectively maintain the turn-on state. There is a problem that the output stage is open.

Accordingly, an object of the present invention is to provide a liquid crystal display and a driving method thereof capable of preventing the gate voltage of the output buffer unit from increasing.

In order to achieve the above technical problem, a liquid crystal display device according to the present invention includes a liquid crystal display panel having a liquid crystal cell; And a common driving circuit for supplying a common voltage to the liquid crystal cell, wherein the common driving circuit is configured to selectively supply a common high voltage and a common low voltage to the liquid crystal cell in response to voltages of first and second nodes. An output buffer section comprising a transistor; A node controller for controlling voltages of the first and second nodes; And refreshing the gate terminal voltages of the plurality of transistors of the output buffer unit periodically to prevent the gate terminal voltage from rising.

The node controller includes first and second transistors connected in series between the first node and a gate low voltage; A third transistor connected between the first node and a gate high voltage and controlled by the voltage of the second node; Fourth and fifth transistors connected in series between the second node and the gate low voltage; And a sixth transistor connected between the second node and the gate high voltage and controlled by the voltage of the first node.

A seventh transistor connected between the common line and the common low voltage and controlled by a voltage of the first node; An eighth transistor connected between the common line and the common high voltage and controlled by the voltage of the second node; A first capacitor connected between the eighth transistor and the common line; And a second capacitor connected between the seventh transistor and the common line.

The refresh unit includes ninth and tenth transistors cross-coupled between the gate low voltage and the third and fourth nodes; A third capacitor connected between the third node and a first clock signal; A fourth capacitor connected between the fourth node and a second clock signal; A plurality of eleventh transistors diode-connected between the first node and a third node; And a plurality of twelfth transistors diode-connected between the second node and the fourth node.

The refresh unit prevents the gate terminal voltage of the seventh transistor from rising through the tenth and eleventh transistors and prevents the gate terminal voltage of the eighth transistor from rising through the ninth and twelfth transistors. It is characterized by.

In order to achieve the above technical problem, a liquid crystal display panel having a liquid crystal cell; A driving method of a liquid crystal display according to the present invention comprising a common driving circuit for supplying a common voltage to the liquid crystal cell, the method comprising: controlling voltages of first and second nodes; Selectively supplying a common high voltage and a common low voltage to the liquid crystal cell through transistors of an output buffer unit in response to voltages of the first and second nodes; And periodically refreshing gate terminal voltages of the plurality of transistors of the output buffer unit in the refresh unit to prevent the gate terminal voltage from increasing.

The liquid crystal display and the driving method thereof according to the present invention discharge the input charges for raising the gate voltage of the transistor of the output buffer section through the refresh section. Therefore, the gate voltage of the transistor of the output buffer unit is prevented from rising, thereby preventing the output buffer unit from turning off and the output terminal being opened.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 2 to 6.

2 is a circuit diagram illustrating a common driving circuit of a display device according to the present invention.

The common driving circuit shown in FIG. 2 includes a node controller 110 that controls charging and discharging of the first and second nodes n1 and n2, and a common high according to the states of the first and second nodes n1 and n2. The output buffer unit 120 outputs the voltage VCOMH or the common low voltage VCOML, and the refresh unit 130 prevents the gate voltage of the output buffer unit 120 from rising.

The node controller 120 may include first to third transistors T1 to T3 for controlling charge and discharge of the first node n1, and fourth to sixth transistors for controlling charge and discharge of the second node n2. T4 to T6).

The first transistor T1 supplies the gate low voltage VGL to the second transistor T2 in response to the first clock signal CLK. For this purpose, the gate terminal of the first transistor T1 is connected to the first clock signal CLK, the source terminal is connected to the gate low voltage VGL, and the drain terminal is connected to the source terminal of the second transistor T2.

The second transistor T2 supplies the gate low voltage VGL supplied through the first transistor T1 to the first node n1 in response to the voltage supplied to the gate line GL. For this purpose, the gate terminal of the second transistor T2 is connected to the gate line GL, the source terminal is connected to the drain terminal of the first transistor T1, and the drain terminal is connected to the first node n1.

The third transistor T3 supplies the gate high voltage VGH to the first node n1 in response to the voltage of the second node n2. For this purpose, the gate terminal of the third transistor T3 is connected to the second node n2, the source terminal is connected to the gate high voltage VGH, and the drain terminal is connected to the first node n1.

The fourth transistor T4 supplies the gate low voltage VGL to the fifth transistor T5 in response to the second clock signal CLKB. For this purpose, the gate terminal of the fourth transistor T4 is connected to the second clock signal CLKB, the source terminal is connected to the gate low voltage VGL, and the drain terminal is connected to the source terminal of the fifth transistor T5.

The fifth transistor T5 supplies the gate low voltage VGL supplied through the fourth transistor T4 to the second node n2 in response to the voltage supplied to the gate line GL. For this purpose, the gate terminal of the fifth transistor T5 is connected to the gate line, the source terminal is connected to the drain terminal of the fourth transistor T4, and the drain terminal is connected to the second node n2.

The sixth transistor T16 supplies the gate high voltage VGH to the second node n2 in response to the voltage of the first node n1. For this purpose, the gate terminal of the sixth transistor T16 is connected to the first node n1, the source terminal is connected to the gate high voltage VGH, and the drain terminal is connected to the second node n2.

The output buffer unit 120 is connected to a voltage of the seventh transistor T7 and the second node n2 that supplies the common low voltage VCOML to the common line CL in response to the voltage of the first node n1. In response, the eighth transistor T8 that supplies the common high voltage VCOMH to the common line CL, and is connected between the gate terminal of the eighth transistor T8 and the common line CL, and is connected to the eighth transistor T8. Is connected between the first capacitor C1 and the gate terminal of the seventh transistor T7 and the common line CL to facilitate the bootstrapping operation of the seventh transistor T7. It includes a second capacitor (C2).

The gate terminal of the seventh transistor T7 is connected to the first node n1, the source terminal is connected to the common low voltage VCOML, and the drain terminal is connected to the common line CL. The gate terminal of the eighth transistor T8 is connected to the second node n2, the source terminal is connected to the common high voltage VCOMH, and the drain terminal is connected to the common line CL.

The refresh unit 130 lowers the gate terminal voltage by the increase of the gate terminal voltage of the seventh transistor T7 connected to the first node n1, and the gate of the eighth transistor T8 connected to the second node n2. The gate terminal voltage is lowered by the increase of the terminal voltage. To this end, the refresh unit 130 includes a plurality of diode-connected diodes connected between the ninth and tenth transistors T9 and T10 that are cross-coupled, and the first node n1 and the third node n3. The eleventh transistor T11, the plurality of twelfth transistors T12 diode-connected between the second node n2 and the fourth node n4, the third node n3, and the first clock signal CLK. And a third capacitor C3 formed therebetween, and a fourth capacitor C4 formed between the fourth node n4 and the second clock signal CLKB.

The ninth transistor T9 supplies the gate low voltage VGL to the fourth node n4 in response to the voltage of the third node n3. For this purpose, the gate terminal of the ninth transistor T9 is connected to the third node n3, the source terminal is connected to the gate low voltage VGL, and the drain terminal is connected to the fourth node n4.

The tenth transistor T10 supplies the gate low voltage VGL to the third node n3 in response to the voltage of the fourth node n4. For this purpose, the gate terminal of the tenth transistor T10 is connected to the fourth node n4, the source terminal is connected to the gate low voltage VGL, and the drain terminal is connected to the third node n3.

The eleventh transistor T11 is formed in an inverted diode form so that electric charges supplied to the gate terminal of the seventh transistor T7 are supplied to the third node n3. The twelfth transistor T12 is formed in the form of an inverted diode such that electric charges supplied to the gate terminal of the eighth transistor T8 are supplied to the fourth node n4. The steady state voltages of the gate terminals of the seventh and eighth transistors T7 and T8 are determined according to the threshold voltage values and the number of the eleventh and twelfth transistors T11 and T12.

The third capacitor C3 is connected between the first clock signal CLK and the third node n3 to charge or discharge in response to the first clock signal CLK. The fourth capacitor C4 is connected between the second clock signal CLKB and the fourth node n4 to charge or discharge in response to the second clock signal CLKB. Accordingly, the third and fourth nodes n3 and n4 repeat the gate low voltage VGL, the difference voltage VGL-VCLK between the gate low voltage VGL, and the clock signal.

That is, the fourth capacitor C4 is charged in response to the second clock signal CLKB of the high logic and is discharged in response to the second clock signal CLKB of the low logic.

Meanwhile, the plurality of transistors T1 to T12 constituting the common driving circuit have been described as an example of being formed of a PMOS transistor as shown in FIG. 2, but may also be formed of an NMOS transistor as shown in FIG. 3.

An operation method of the common driving circuit will be described with reference to FIGS. 2 and 4.

When the gate low voltage VGL is supplied to the gate terminals of the second and fifth transistors T2 and T5 through the gate line GL during the first horizontal period H1 of the first frame F1, the second and The fifth transistors T2 and T5 are turned on. When the first clock signal CLK maintains a low logic state and the second clock signal CLKB maintains a high logic state during the first horizontal period H1, the fourth transistor T4 is turned off. The first transistor T1 is turned on. Here, the first and second clock signals CLK and CLKB are inverted in phase by one frame and have two horizontal periods. The first and second clock signals CLK and CLKB are in phased with each other.

Accordingly, the first node n1 is supplied with a difference voltage between the gate low voltage VGL and the threshold voltages Vth of the first and second transistors T1 and T2, that is, VGL + | 2Vth | The sixth transistor T6 is turned on in response to VGL + 2Vth | supplied to the first node n1. Accordingly, the second node n2 is supplied with a difference voltage between the gate high voltage VGH and the threshold voltage Vth of the sixth transistor T6, that is, VGH- | Vth |. In response to VGH- | Vth | supplied to the second node n2, the third transistor T3 and the eighth transistor T8 are turned off and respond to VGL + │2Vth | charged in the first node n1. As a result, the seventh transistor T7 is turned on so that the common low voltage VCOML is supplied to the common line CL.

Subsequently, when the gate high voltage VGH is supplied to the second and fifth transistors T2 and T5 through the gate line GL during the second horizontal period H2, the second and fifth transistors T2 and T5. ) Is turned off so that the first node n1 is in a floating state, and the seventh transistor T7 is turned on. In this case, as the common low voltage VCOML is supplied to the seventh transistor T7, the floating first node n1 may have an internal capacitor Cgd formed between the gate terminal and the drain terminal of the seventh transistor T7. Bootstrapped by the influence of the second capacitor (C2). As a result, the voltage of the first node n1 further increases, so that the seventh transistor T7 is reliably turned on so that the common low voltage VCOML is rapidly supplied to the common line CL. The first to sixth and eighth transistors T1 to T6 and T8 maintain the same state as the first horizontal period H1. In particular, since the sixth transistor T6 is turned on until the voltage of the first node n1 becomes equal to or greater than VGH-Vthp, which is the turn-off voltage of the seventh transistor T7, the eighth transistor T8 is Keep off.

At this time, the charges supplied to the seventh transistor T7 through the third transistor T3, which must maintain the turn-off state, are discharged through the refresh unit 130.

In detail, the ninth transistor T9 is turned on in response to the first clock signal CLK of the low logic, and the tenth transistor T10 is turned off by the second clock signal CLKB of the high logic. Therefore, charges supplied to the gate terminal of the seventh transistor T7 through the third transistor T3 are charged to the third capacitor C3 through the plurality of eleventh transistors T11. Then, during the third horizontal period H3, the ninth transistor T9 is turned off by the high logic first clock signal CLK1 and the tenth transistor (by the low logic second clock signal CLKB). T10) is turned on. Therefore, the voltages charged in the third capacitor C3 through the turned-on tenth transistor T10 are discharged to the gate low voltage VGL to prevent the gate voltage of the seventh transistor T7 from rising. In this case, the gate voltage of the seventh transistor T8 should be a voltage at which the charge charged through the third transistor T3 and the charge discharged through the refresh unit 130 match.

When the gate low voltage VGL is supplied to the gate terminals of the second and fifth transistors T2 and T5 through the gate line GL during the first horizontal period H1 of the second frame F2, the second and The fifth transistors T2 and T5 are turned on. When the first clock signal CLK maintains a high logic state and the second clock signal CLKB maintains a low logic state during the first horizontal period H1, the fourth transistor T4 is turned on. The first transistor T1 is turned off. Accordingly, the second node n2 is supplied with a difference voltage between the gate low voltage VGL and the threshold voltages Vth of the fourth and fifth transistors T4 and T5, that is, VGL + | 2Vth | The third transistor T3 is turned on in response to VGL + | 2Vth | supplied to the second node n2. Accordingly, the first node n1 has a difference voltage between the gate high voltage VGH supplied through the third transistor T3 and the threshold voltage Vth of the third transistor T3, that is, VGH- | Vth | Supplied. The sixth transistor T6 and the seventh transistor T7 are turned off in response to VGH-│Vth│ supplied to the first node n1, and respond to VGL + │2Vth│ charged in the second node n2. The eighth transistor T8 is turned on to supply the common high voltage VCOMH to the common line CL.

Subsequently, when the gate high voltage VGH is supplied to the second and fifth transistors T2 and T5 through the gate line GL during the second horizontal period H2, the second and fifth transistors T2 and T5. ) Is turned off, so that the second node n2 is in a floating state, and the eighth transistor T8 is turned on. In this case, as the common high voltage VCOMH is supplied to the eighth transistor T8, the floating second node n2 may have an internal capacitor Cgd formed between the gate terminal and the drain terminal of the eighth transistor T8. Bootstraped under the influence of the first capacitor C1. As a result, the voltage of the second node n2 further increases to ensure that the eighth transistor T8 is turned on reliably so that the common high voltage VCOMH is quickly supplied to the common line CL. The first to seventh transistors T1 to T7 maintain the same state as the first horizontal period H1. In particular, since the third transistor T3 remains turned on until the voltage of the second node n2 becomes equal to or greater than VGH-Vthp, which is the turn-off voltage of the eighth transistor T8, the seventh transistor T7 is turned on. Keep off.

At this time, the charges supplied to the eighth transistor T8 through the sixth transistor T6, which should maintain the turn-off state, are discharged through the refresh unit 130.

In detail, the tenth transistor T10 is turned on by the first clock signal CLK of the high logic, and the ninth transistor T9 is turned off by the second clock signal CLK of the low logic. Accordingly, charges supplied to the gate terminal of the eighth transistor T8 through the sixth transistor T6 are charged to the fourth capacitor C4 through the plurality of twelfth transistors T12. Then, the tenth transistor T10 is turned off by the first clock signal CLK of low logic during the third horizontal period H3, and the ninth transistor (by the second clock signal CLKB of high logic). T9) is turned on. Therefore, the voltages charged in the fourth capacitor C4 through the turned-on ninth transistor T9 are discharged to the gate low voltage VGL to prevent the gate voltage of the eighth transistor T8 from rising. In this case, the gate voltage of the eighth transistor T8 should be a voltage at which the charge charged through the sixth transistor T6 matches the charge discharged through the refresh unit 130.

FIG. 5A is a diagram illustrating voltage-current characteristics of transistors included in the output buffer unit according to the related art and the present invention, and FIG. 5B is a diagram illustrating the change of the gate terminal voltage of each transistor included in the conventional output buffer unit, and FIG. 5C. Is a view showing a voltage change of a gate terminal of each transistor included in an output buffer unit according to the present invention.

As shown in FIG. 5A, the transistors having threshold voltages of -2.6V and -5V, respectively, of the output buffer part according to the related art and the present invention increase the current when the gate-source terminal voltage is 0V. Accordingly, as illustrated in FIG. 5B, the gate terminal voltage of the conventional output buffer unit including the transistors having the threshold voltages of -2.6 V and -5 V, respectively, is constant over time, but the conventional gate electrode having the threshold voltage of -0.27 V The gate terminal voltage of the output buffer part continues to increase as time passes, which causes the transistor to be turned on to be turned off. On the other hand, as shown in Fig. 5c, the gate terminal voltage of the output buffer unit according to the present invention, which is composed of transistors having threshold voltages of -0.27V, -2.6V, and -5, respectively, is constant over time, thereby turning on or turning off. Keep it for as long as you want. That is, the gate terminal voltage of the output buffer part according to the present invention, which is composed of transistors having threshold voltages of -0.27V, -2.6V, and -5, respectively, is caused by charges supplied through the third and sixth transistors T3 and T6. After the increase is reduced by the refresh unit 130 it is repeated.

FIG. 6 is a block diagram illustrating a liquid crystal display device having a common driving circuit shown in FIG. 2.

The liquid crystal display shown in FIG. 6 includes a liquid crystal panel 146 for displaying an image, a gate driving circuit 144 for driving a gate line GL of the liquid crystal panel 146, and data of the liquid crystal panel 146. The data driving circuit 142 driving the line DL and the common driving circuit 140 driving the common line CL of the liquid crystal panel 146 are provided.

The liquid crystal panel 146 includes gate lines GL, data lines DL intersecting the gate lines GL while insulated from the gate lines GL, and intersections of the gate lines GL and the data lines DL. The thin film transistor TFT formed in each region to be formed, the liquid crystal cell Clc connected to the thin film transistor TFT, and the storage capacitor Cst connected in parallel with the liquid crystal cell Clc are formed.

The thin film transistor TFT of the liquid crystal panel 146 is turned on by the gate high voltage from the gate line GL so that the data signal of the data line DL is supplied to the liquid crystal cell Clc so that the liquid crystal cell Clc is turned on. The voltage equal to the difference between the common voltage Vcom and the data signal is applied, and is turned off by the gate low voltage to maintain the voltage applied to the liquid crystal cell Clc. The liquid crystal cell Clc drives the liquid crystal according to the applied voltage to adjust the light transmittance so that the liquid crystal panel 146 displays an image.

The gate driving circuit 144 sequentially supplies the gate high voltage to the gate line GL in response to a control signal from a timing controller (not shown), and supplies the gate low voltage in other periods.

The data driving circuit 142 converts the digital data signal into an analog voltage using the control signal and the gamma voltage from the timing controller, and supplies the changed analog voltage to the data line DL.

The common driving circuit 140 supplies a common voltage Vcom to the liquid crystal cell Clc and the storage capacitor Cst in response to a control signal from the timing controller. In this case, the common voltage supplied to the liquid crystal cell Clc and the common voltage of the storage capacitor Cst may be the same or different. When the two voltages are different from each other, a common driving circuit generating a common voltage Vcom supplied to the liquid crystal cell Clc and a space supplied to the storage capacitor Cst.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a diagram illustrating a common driving circuit of a conventional liquid crystal display.

2 is a circuit diagram illustrating a common driving circuit of the liquid crystal display according to the present invention.

3 is a circuit diagram illustrating another embodiment of a common driving circuit of a liquid crystal display according to the present invention.

4 is a diagram illustrating a driving waveform diagram of the common driving circuit illustrated in FIG. 2.

FIG. 5A is a diagram illustrating voltage-current characteristics of a P-type transistor included in an output buffer unit according to the prior art and the present invention, and FIG. 5C is a view illustrating a change in gate terminal voltage of each transistor included in an output buffer unit according to the present invention.

FIG. 6 is a block diagram illustrating a liquid crystal display device having a common driving circuit shown in FIG. 2.

<Description of Symbols for Main Parts of Drawings>

110: node controller 120: output buffer unit

130: refresh unit 140: common drive circuit

142: data driving circuit 144: gate driving circuit

146 liquid crystal panel

Claims (6)

A liquid crystal display panel having a liquid crystal cell; A common driving circuit for supplying a common voltage to the liquid crystal cell, The common driving circuit An output buffer unit comprising a plurality of transistors to selectively supply a common high voltage and a common low voltage to the liquid crystal cell in response to voltages of first and second nodes; A node controller for controlling voltages of the first and second nodes; And a refresh unit for periodically refreshing gate terminal voltages of the plurality of transistors of the output buffer unit to prevent the gate terminal voltage from rising. The method of claim 1, The node control unit First and second transistors connected in series between the first node and a gate low voltage; A third transistor connected between the first node and a gate high voltage and controlled by the voltage of the second node; Fourth and fifth transistors connected in series between the second node and the gate low voltage; And a sixth transistor connected between the second node and the gate high voltage and controlled by the voltage of the first node. The method of claim 2, The output buffer unit A seventh transistor connected between the common line and the common low voltage and controlled by the voltage of the first node; An eighth transistor connected between the common line and the common high voltage and controlled by the voltage of the second node; A first capacitor connected between the eighth transistor and the common line; And a second capacitor connected between the seventh transistor and the common line. The method of claim 3, wherein The refresh unit Ninth and tenth transistors cross-coupled between the gate low voltage and the third and fourth nodes; A third capacitor connected between the third node and a first clock signal; A fourth capacitor connected between the fourth node and a second clock signal; A plurality of eleventh transistors diode-connected between the first node and a third node; And a plurality of twelfth transistors diode-connected between the second node and the fourth node. The method of claim 4, wherein The refresh unit prevents the gate terminal voltage of the seventh transistor from rising through the tenth and eleventh transistors and prevents the gate terminal voltage of the eighth transistor from rising through the ninth and twelfth transistors. A liquid crystal display device, characterized in that. A liquid crystal display panel having a liquid crystal cell; In the driving method of the liquid crystal display device provided with the common drive circuit which supplies a common voltage to the said liquid crystal cell, Controlling the voltages of the first and second nodes; Selectively supplying a common high voltage and a common low voltage to the liquid crystal cell through transistors of an output buffer unit in response to voltages of the first and second nodes; And periodically refreshing gate terminal voltages of the plurality of transistors of the output buffer unit in the refresh unit to prevent the gate terminal voltage from rising.

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