KR20080111745A - Method for booting of multi-processor using multi-port memory, multi-port memory and muliti-processor system having multi-port memory - Google Patents

Abstract

A method for booting a multi-processor by using a multi-port memory, the multi-port memory and a multi-processor system having the multi-port memory are provided to improve the booting speed and miniaturize a processor device. A method for booting a multi-processor comprises at least one or more processors. The method comprises the following steps of: copying data stored in the first processor exclusive memory area of a multi-port memory to the second processor exclusive memory area(309); and booting the second processor based on the data copied to the second processor exclusive memory area(315).

Description

Method for booting of multi-processor using multi-port memory, multi-port memory and muliti-processor system having multi-port Memory}

1 is a block diagram showing the configuration of a conventional multiprocessor system.

2 is a flowchart illustrating a booting process of a conventional multiprocessor system.

3 is a block diagram illustrating a configuration of a multiprocessor system using a multi-port memory according to an embodiment of the present invention.

4 is a flowchart illustrating a booting process of a multiprocessor using a multi-port memory according to an embodiment of the present invention.

FIG. 5 is a flowchart illustrating an operation of the boot controller illustrated in FIG. 3.

6 is a block diagram illustrating a configuration of a multiprocessor system using a multiport memory according to another exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110, 510: first processor 130, 520: second processor

135: boot control unit 200, 600: multi-port memory

210, 610: first dedicated memory area

230, 620: second dedicated memory area

250 and 650: shared memory area 259 and 659: semaphore control unit

525: second boot control unit 530: third processor

535: third boot control unit 540: fourth processor

545: fourth boot control unit 630: third dedicated memory area 640: fourth dedicated memory area

The present invention relates to a multiprocessor system having a multi-port memory, and more particularly, to a multi-processor booting method, a multi-port memory and a multi-port memory using a multi-port memory that can reduce the boot time of the processor It's about the system.

Recently, portable terminals such as mobile communication terminals and PDAs (Personal Digital Assistants) include various additional applications such as image and video recording, video calling, mobile Internet, and multimedia data playback in addition to wireless communication functions such as voice calls. To include one or more processors.

That is, recent portable terminals include a baseband processor for performing the original functions of the mobile communication and an application processor for performing various additional applications.

Here, the baseband processor may be a processor of the ARM family (eg, ARM7 or ARM9), and the application processor may use various processors (eg, multimedia processors) according to the manufacturer.

When the portable terminal includes a baseband processor and an application processor as described above, the baseband processor plays a role of a master, and the application processor plays a role of a slave.

That is, when the portable terminal is initialized, first, the baseband processor serving as the master is booted, and then the application processor is booted by controlling the application processor serving as a slave through the host processor interface (HPI).

1 is a block diagram illustrating a configuration of a conventional multiprocessor system, in which a first processor 10 and a second processor 30 are independently connected to a first main memory 13 and a second memory 33, respectively. Indicates.

Referring to FIG. 1, a conventional multiprocessor system includes a first processor 10 and a second processor 30, and the first processor 10 and the second processor 30 each include a first buffer 11. And a second buffer 31. Here, the first buffer 11 and the second buffer 31 may be a cache memory, and have a predetermined size (for example, 128 bytes or 256 bytes).

The first processor 10 is connected to the first main memory 13 through a first external bus interface (EBI) 12, and the second processor 30 is connected to the second external bus interface 32. It is connected to the second main memory 33 through. Here, the first external bus interface 12 and the second external bus interface 32 may each be a synchronous dynamic random access memory (SDRAM) external bus interface.

The first main memory 13 includes a first memory interface 14, and the second main memory 33 includes a second memory interface 34. The first memory interface 14 and the second memory interface 34 may each be SDRAM memory interfaces.

The first memory interface 14 receives an address, a control signal, a clock, and data from the first processor 10 through the first external bus interface 12, and reads, writes, and refreshes the data. Data input and output are performed according to the operation timing. The first memory interface 14 includes a command decoder, a row decoder, a column decoder, an input / output buffer, and the like.

The second memory interface 34 receives an address, a control signal, a clock, and data from the second processor 30 through the second external bus interface 32, and stores the memory according to an operation timing such as reading, writing, and refreshing. I / O of area and data is performed. The second memory interface 34 includes a command decoder, a row decoder, a column decoder, an input / output buffer, and the like.

In addition, the first processor 10 and the second processor 30 exchange control signals, commands, data to be processed, and the like through the host processor interface (HPI) 20. For example, the second processor 30 may receive data necessary for booting through the host processor interface 20.

2 is a flowchart illustrating a booting process of a conventional multiprocessor system, and illustrates a case in which the first processor 10 performs a master role and the second processor 30 performs a slave role.

Referring to FIGS. 1 and 2, a booting process of a conventional multiprocessor system is described. First, when a multiprocessor system is initialized, the first processor 10 performs a booting procedure and initializes an operating system according to an initialization program. Transfer from volatile memory to first main memory 13 (step 51).

Thereafter, the first processor 10 initializes the second processor 30 by providing a power control signal and a reset signal to the second processor 30 through the host processor interface 20 (step 52). That is, the first processor 10 provides the power control signal to the second processor 30 through the host processor interface 20 so that the second processor 30 is in an on state from the off state and provides a reset signal. By doing so, the second processor 30 is reset.

Next, the first processor 10 copies a portion of data (ie, an operating system) stored in the first main memory 13 to the first buffer 11 through the first external bus interface 12 (step 53). ). In addition, the first processor 10 may provide data stored in the first buffer 11 to the second buffer 31 of the second processor 30 through the host processor interface 20. Data is copied to the second buffer 31 (step 54).

Thereafter, the data copied to the second buffer 31 is stored in the second main memory 33 by the second processor 30 (step 55), and the second processor 30 stores the first main memory 13. It is determined whether all of the data in the second main memory 33 has been copied (step 56), and if it is determined that the copying is not completed, the process returns to step 53 where the data of the first main memory 13 is stored in the second main memory ( Copy to 33).

If it is determined that all data of the first main memory 13 has been copied to the second main memory 33, the second processor 30 performs a booting procedure based on the data stored in the second main memory 33. Perform (step 57). That is, the second processor 30 reads and decodes the instructions and / or data stored in the second main memory 33 to perform a decoded instruction to perform a booting procedure. (Step 58).

As shown in FIG. 2, in the conventional multiprocessor system, the first processor 10 serving as a master controls the second processor 30 serving as a slave through the host processor interface 20, and the first processor 10 performs the first processing. The booting procedure may be performed by providing data stored in the first main memory 13 of the processor 10 to the second main memory 33 of the second processor 30 through the host processor interface 20 to boot the slave processor. It is complicated and has a disadvantage in that an initial waiting time until a user input can be executed after power is applied to the system due to a long boot time is long.

In addition, in FIG. 2, the multiprocessor system including only the first processor 10 performing the master role and the second processor 30 performing the slave role has been described as an example. However, a processor performing the slave role may be further added. In this case, the overall boot time of a multiprocessor system will be longer.

In addition, since the data required for booting is transmitted between the first processor 10 and the second processor 30 through a separate host processor interface 20, the number of pins due to the host processor interface 20 increases. As a result, the size of the package increases, manufacturing costs increase, power consumption increases, and there is a limitation in miniaturization and slimming of a device (for example, a mobile communication terminal) on which the processor package is mounted.

Accordingly, a first object of the present invention is to provide a booting method of a multiprocessor using a multi-port memory which can improve booting speed and can reduce the size of a processor device.

In addition, a second object of the present invention is to provide a multi-port memory used by a multiprocessor to improve the boot speed and to reduce the size of the processor device.

It is also a third object of the present invention to provide a multiprocessor system having a multi-port memory capable of improving the boot speed and miniaturizing the size of the processor device.

According to an aspect of the present invention, there is provided a booting method of a multiprocessor using a multi-port memory, the method comprising: storing data stored in a first processor dedicated memory area of the multi-port memory; Copying to a second processor dedicated memory region, and booting the second processor based on data copied to the second processor dedicated memory region. Copying data stored in the first processor dedicated memory area of the multi-port memory to the second processor dedicated memory area of the multi-port memory may include copying data stored in the first processor dedicated memory area of the multi-port memory to a shared memory area. Copying the data copied to the shared memory area to a second processor dedicated memory area of the multi-port memory. Copying data stored in a first processor dedicated memory area of the multi-port memory to a shared memory area may include: booting the first processor based on an initialization program; and when the first processor finishes booting, The method may include copying data stored in a first processor dedicated memory area to the shared memory area. Copying the data copied to the shared memory area to a second processor dedicated memory area of the multi-port memory may include resetting the second processor based on a reset control signal provided from the first processor. have. Copying the data copied to the shared memory area to the second processor dedicated memory area of the multi-port memory may include acquiring an access right to the shared memory area, and in the shared memory area, the second processor dedicated memory. The method may include copying data to an area and releasing access to the shared memory area when copying of the data is completed. Copying data from the shared memory area to the second processor dedicated memory area may include branching a start address to an address at which an instruction to be executed first is stored. The data may include instructions to copy data copied to the shared memory area to a second processor dedicated memory area of the multi-port memory.

The multi-port memory according to an aspect of the present invention for achieving the second object of the present invention is a dedicated memory area of the first processor, the first dedicated memory in which booting data is stored after the first processor has completed booting. An area and a memory area shared by the first processor and the second processor, the shared memory area to which the boot data is copied by the first processor, and a dedicated memory area of the second processor, stored in the shared memory area. And a second dedicated memory area to which boot data is copied. The multi-port memory may include a semaphore control unit to guarantee access rights of the first processor and the second processor to the predetermined shared memory area.

According to an aspect of the present invention, there is provided a multiprocessor system including: a first processor configured to copy data stored in a first dedicated memory area to a predetermined shared memory area after booting is completed; A second processor and the first dedicated memory area, the second dedicated memory area and the second processor performing a booting procedure based on the copied boot data after copying the data from the predetermined shared memory area to a second dedicated memory area; It includes a multi-port memory having at least one shared memory area. The second processor may be reset based on a reset control signal provided from the first processor after power is applied. The second processor may include a boot control unit releasing an access right to the shared memory area when copying of the data for obtaining the access right to the predetermined shared memory area is completed after the reset is performed. The boot controller may branch the start address to the address where the first command to be executed is stored. The data may include a command to copy data copied to the predetermined shared memory area to the second dedicated memory area. The multi-port memory may guarantee exclusive access rights of the first processor and the second processor to the predetermined shared memory area.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. In the following description of the present invention, the same reference numerals are used for the same elements in the drawings and redundant descriptions of the same elements will be omitted.

3 is a block diagram illustrating a configuration of a multiprocessor system using a multi-port memory according to an embodiment of the present invention. 3 illustrates an example of a multiprocessor system consisting of dual port memory with two processors and two ports. Hereinafter, the multi-port memory is a concept including a dual port memory.

Referring to FIG. 3, a multiprocessor system according to an exemplary embodiment of the present invention generally includes a first processor 110, a second processor 130, and a multi-port memory 200.

The multi-port memory 200 may be composed of a first memory interface 211, a second memory interface 231, and a memory cell array. The memory cell array may be divided into a first dedicated memory area 210, a second dedicated memory area 230, and a shared memory area 250, and the shared memory area 250 may include first to fourth shared memory areas ( 251 to 257). Here, the memory cell array of the multi-port memory 200 may be composed of DRAM cells.

In addition, the multi-port memory 200 may allow the first processor 110 or the second processor 130 to acquire exclusive access rights to the first to fourth shared memory areas 251 to 257. And a semaphore control unit 259 for ensuring synchronization between the second processors 130.

The first dedicated memory area 210 is a memory area used exclusively by the first processor 110, and the second dedicated memory area 230 is a memory area used exclusively by the second processor 130. In addition, the shared memory area 250 is a memory area that the first processor 110 and the second processor 130 can use in common. The first processor 110 and the second processor 130 are the semaphore control unit 259. After obtaining the exclusive right for the predetermined shared memory area 250 using the data input and output data.

The first processor 110 and the second processor 130 may access the multi-port memory 200 and the data through the first external bus interface (EBI) 111 and the second external bus interface 131, respectively. Perform I / O.

The first external bus interface 111 and the second external bus interface 131 serve as a kind of memory controller, and an external bus interface of a synchronous DRAM (SDRAM) or a pseudo SRAM (PSRAM) may be used. In the following embodiment of the present invention, it is assumed that the first external bus interface 111 and the second external bus interface 131 are SDRAM external bus interfaces.

The first processor 110 provides an address, a plurality of control signals, and a clock to the multi-port memory 200 through the first port 212 of the multi-port memory 200, and the multi-port memory 200 includes a first port. Input and output of data with the first processor 110 is performed through the port 212 and the first external bus interface 111.

The second processor 130 provides an address, a plurality of control signals, and a clock to the multi-port memory 200 through the second port 232 of the multi-port memory 200, and the multi-port memory 200 includes a second port. Input and output data to and from the second processor 130 through the port 232 and the second external bus interface 131.

Here, the first processor 110 may be, for example, an ARM-based baseband processor mounted on a portable terminal to process a mobile communication function, and the second processor 130 may be a multimedia processor to process additional applications. Can be.

The first memory interface 211 may be configured as an SDRAM memory interface. The first memory interface 211 receives an address, a control signal, a clock, and data from the first processor 110 through the first port 212, and assigns an address to a row address and a column address. After decoding, the decoded address is output to the memory cell array, and data is read from the memory cell array or written to the memory cell array in accordance with an operation timing such as reading, writing, and refreshing the memory cell array.

To this end, the first memory interface 211 may include a command decoder (not shown), a row decoder (not shown), a column decoder (not shown), and input / output used in a general SDRAM interface. And a buffer (not shown).

The second memory interface 231 may be configured as an SDRAM memory interface. The second memory interface 231 receives an address, a control signal, a clock, and data from the second processor 130 through the second port 232, and sets the addresses as row addresses and columns. After decoding to an address, the decoded address is output to the memory cell array, and data is read from or written to the memory cell array in accordance with an operation timing such as reading, writing, and refreshing the memory cell array.

To this end, the second memory interface 231 may include a command decoder (not shown), a row decoder (not shown), a column decoder (not shown), an input / output buffer (not shown) used in a general SDRAM interface, and the like.

In the multiprocessor system illustrated in FIG. 3, the first processor 110 plays a role of a master processor, and the second processor 130 plays a role of a slave processor initialized by the first processor 110. The second processor 130 includes a boot control unit 135 for controlling booting after initialization.

When the multiprocessor system is initialized, the first processor 110 completes booting and transfers data (eg, an operating system) stored in the first dedicated memory area 210 to predetermined shared memory areas 251 to 257 (eg, For example, after copying to the first shared memory area 251, the second processor 130 is initialized by providing a power control signal and a reset signal to the second processor 130.

When the second processor 130 is reset, the boot controller 135 provides the semaphore controller 259 with a lock control signal lock_con to acquire exclusive access right to a predetermined shared memory area, and then the predetermined shared memory. Data stored in the areas 251 to 257 (eg, the first shared memory area 251) is copied to the second dedicated memory.

In addition, the boot controller 135 may store a preset address in which a command to be first performed in the second dedicated memory or the predetermined shared memory areas 251 to 257 (for example, the first shared memory area 251) is stored. If it is not the starting address, branch the starting address (eg program counter) to the address where the first instruction to be executed is stored.

Here, the first command to be executed may be, for example, a command to copy data stored in the first shared memory area 251 to the second dedicated memory area 230. That is, the second processor 130 executes the instruction after branching to the address where the first instruction to be executed by the boot controller 135 is stored, and then stores the data stored in the first shared memory region 251 in the second dedicated memory. Copy to area 230.

The boot controller 135 may be implemented in hardware logic and connected to the semaphore controller 259 through a physical signal transmission line 137.

4 is a flowchart illustrating a booting process of a multiprocessor using a multi-port memory according to an embodiment of the present invention, wherein the first processor 110 and the second processor 130 have two ports. A booting process using the shared memory area 250 of FIG.

Referring to FIGS. 3 and 4, when the multiprocessor system is initialized, the first processor 110 performs a booting procedure according to an initialization program and sets the operating system in the nonvolatile memory to the first dedicated memory area 210. (Step 301).

Here, the initialization program may be an initial program or a bootstrap loader that should be executed first when the device is powered on, and the bootstrap program is a predetermined device equipped with a multiprocessor system. It may be stored in a nonvolatile memory (for example, a flash memory or an EEPROM (Electrically Erasable and Programmable Read Only Memory)) provided in the portable terminal.

Thereafter, the first processor 110 copies the data stored in the first dedicated memory area 210 to the first shared memory area 251 (step 303). Here, the data may include an operating system. In addition to the operating system, the data may include various application programs executed in the second processor 130.

For example, the data may include a hardware device driver, an operating system kernel, a file system, a digital multimedia broadcasting (DMB) related file, a conditional access system (CAS), and a digital right (DRM). Management), an audio codec, a multimedia engine, and the like, and the files may be compiled binary files.

When all data stored in the first dedicated memory area 210 is copied to the first shared memory area 251, the first processor 110 supplies a power and reset control signal (power / reset) to the second processor 130. Transmit to initialize the second processor 130 (step 305). Here, the first processor 110 and the second processor 130 may transmit power and reset control signals (power / reset) through separate signal transmission lines 120 (eg, 1 bit).

When the second processor 130 is initialized, the boot controller 135 provides the semaphore controller 259 with a lock control signal lock_con to obtain exclusive access right to the predetermined shared memory area 250 (step 307). . The predetermined shared memory area 250 may be any one of the first to fourth shared memory areas 251 to 257. Hereinafter, in an embodiment of the present invention, it is assumed that the predetermined shared memory areas 251 to 257 are the first shared memory areas 251 for convenience of description.

After obtaining the exclusive access right to the first shared memory area 251, the boot controller 135 copies the data stored in the first shared memory area 251 to the second dedicated memory area 230 (step 309). ). Here, the boot controller 135 stores the first instruction to be executed when the first stored instruction in the second dedicated memory region 230 or the first shared memory region 251 is not a preset start address. You can branch start addresses to addresses.

The boot controller 135 determines whether the copy of the data is completed (step 311), and if it is determined that the copy is not completed, returns to step 309 to continue copying, and if it is determined that the copy is completed, the first share The access right of the memory area 251 is unlocked (step 313).

Thereafter, the second processor 130 performs a boot based on the data stored in the second dedicated memory area 230 (step 315), and waits for a command waiting state when the booting is completed (step 317).

3 and 4, in the booting method of a multiprocessor using the multi-port memory 200 according to an embodiment of the present invention, a slave processor (that is, a second processor) using the multi-port memory 200 is used. 130)) allows for faster booting time and eliminates the need for a separate host processor interface for transmitting data, addresses, control signals, etc. required for booting.

FIG. 5 is a flowchart illustrating an operation of the boot controller 135 illustrated in FIG. 3, and illustrates the processing of steps 307 and 309 illustrated in FIG. 4 in detail.

Referring to FIG. 5, first, the boot controller 135 determines whether power is applied (step 401), and if it is determined that power is applied, determines whether the second processor 130 is reset (step 403).

If it is determined in step 403 that the second processor 130 is reset, the boot control unit 135 transmits a lock control signal lock_con to the semaphore control unit 259, thereby exclusive access to the first shared memory area 251. Is obtained (step 405).

Thereafter, the boot controller 135 determines whether a command exists at the start address of the second dedicated memory area 230 (step 407), and determines that the command does not exist at the start address of the second dedicated memory area 230. , Branch the starting address to the address at which the instruction exists. Here, the start address refers to an address of a memory which first reads an instruction after the second processor 130 is initialized, and the address where the instruction exists is the most of the data copied to the first shared memory area 251. It can be the address of the location where the first command to be executed is stored.

Thereafter, the boot controller 135 reads and executes the command from the branched start address (step 411). The read command may be a command for copying data stored in the first shared memory area 251 to the second dedicated memory area 230.

6 is a block diagram illustrating a configuration of a multiprocessor system using a multiport memory according to another exemplary embodiment of the present invention. 6 illustrates an example of a multiprocessor system consisting of a multi-port memory with four processors and four ports.

Referring to FIG. 6, a multiprocessor system according to another exemplary embodiment of the present invention may include a first processor 510, a second processor 520, a third processor 530, a fourth processor 540, and a multi-port memory. And 600.

The multi-port memory 600 may include a first memory interface 611, a second memory interface 621, a third memory interface 631, a fourth memory interface 641, and a memory cell array. The memory cell array may be divided into a first dedicated memory area 610, a second dedicated memory area 620, a third dedicated memory area 630, a fourth dedicated memory area 640, and a shared memory area 650. The shared memory area 650 may be divided into first to fourth shared memory areas 651 to 657.

 In addition, the multi-port memory 600 allows the first to fourth processors 510 to 540 to acquire exclusive access rights to the first to fourth shared memory areas 651 to 657. And a semaphore control unit 659 to ensure synchronization between the 510 and 540.

The first dedicated memory area 610 is a memory area exclusively used by the first processor 510, and the second dedicated memory area 620 is a memory area exclusively used by the second processor 520. In addition, the third dedicated memory area 630 is a memory area dedicated to the third processor 530, and the fourth dedicated memory area 640 is a memory area dedicated to the fourth processor 540.

The shared memory area 650 is a memory area that can be commonly used by the first to fourth processors 510 to 540. The first to fourth processors 510 to 540 may be predetermined using the semaphore control unit 659. Data may be input and output after obtaining exclusive rights for the shared memory regions 651 to 657 of FIG.

The first to fourth processors 510 to 540 respectively input and output data to and from the multi-port memory 600 through the first to fourth external bus interfaces 511 to 541.

The first processor 510 provides an address, a plurality of control signals, and a clock to the multi-port memory 600 through the first port 612 of the multi-port memory 600, and the multi-port memory 600 includes the first port 612. Input and output data to and from the first processor 510 through the port 612 and the first external bus interface 511.

The second processor 520 provides an address, a plurality of control signals, and a clock to the multi-port memory 600 through the second port 622 of the multi-port memory 600, and the multi-port memory 600 includes a second Input and output data to and from the second processor 520 through the port 612 and the second external bus interface 521.

The third processor 530 provides an address, a plurality of control signals, and a clock to the multi-port memory 600 through the third port 632 of the multi-port memory 600, and the multi-port memory 600 is a third port. Input and output of data is performed with the third processor 530 through the port 632 and the third external bus interface 531.

The fourth processor 540 provides an address, a plurality of control signals, and a clock to the multi-port memory 600 through the fourth port 541 of the multi-port memory 600, and the multi-port memory 600 is a fourth port. Input / output of data with the fourth processor 540 is performed through the port 642 and the fourth external bus interface 541.

In the multiprocessor system illustrated in FIG. 6, the first processor 510 serves as a master processor, and the second processor 520, the third processor 530, and the fourth processor 540 may be the first processor 510. It acts as a slave processor initialized by. The second processor 520, the third processor 530, and the fourth processor 540 are initialized after the second boot control unit 525, the third boot control unit 535, and the fourth boot control unit to control booting, respectively. 545.

When the multiprocessor system is initialized, the first processor 510 completes booting and stores data (eg, an operating system) stored in the first dedicated memory area 610 in a predetermined shared memory area (eg, the first). After copying to the shared memory area 651, the second processor 520 is initialized by providing a power control signal and a reset signal (power / reset) to the second processor 520. Hereinafter, it is assumed that the predetermined shared memory area is the first shared memory area 651.

When the second processor 520 is reset, the second boot controller 525 provides the semaphore controller 659 with the lock control signal lock_con1 to acquire exclusive access to the first shared memory area 651. Data stored in the first shared memory area 651 is copied to the second dedicated memory area 620.

In addition, the second boot controller 525 may be first executed when the address in which the first instruction to be executed in the second dedicated memory region 620 or the first shared memory region 651 is stored is not a preset start address. Causes the start address (e.g. program counter) to branch to the address where the instruction is stored.

When copying of the data of the first shared memory area 651 is completed, the second boot controller 525 unlocks the access right of the first shared memory area 651 and performs a booting procedure.

The third processor 530 is initialized by a power control signal and a reset signal (power / reset) provided from the first processor 510. When the first shared memory area 651 is unlocked, the third boot control unit 535 provides the semaphore control unit 659 with the lock control signal lock_con2 to provide the first shared memory area 651 with the first shared memory area 651. After obtaining the exclusive access right, the data stored in the first shared memory area 651 is copied to the third dedicated memory area 630.

In addition, the third boot controller 535 may perform the first operation when the address in which the first instruction to be executed in the third dedicated memory region 630 or the first shared memory region 651 is stored is not a preset start address. Causes the start address to branch to the address where the instruction is stored.

Subsequently, when copying of the data of the first shared memory area 651 is completed, the third boot controller 535 releases the access right of the first shared memory area 651 and performs a booting procedure.

The fourth processor 540 is initialized by a power control signal and a reset signal (power / reset) provided from the first processor 510. When the first shared memory area 651 is unlocked, the fourth boot control unit 545 provides the semaphore control unit 659 with a lock control signal lock_con3 to provide the first shared memory area 651 with the first shared memory area 651. After obtaining the exclusive access right, the data stored in the first shared memory area 651 is copied to the fourth dedicated memory area 640.

In addition, the fourth boot controller 545 may perform the first operation when the address in which the first instruction to be executed in the third dedicated memory region 640 or the first shared memory region 651 is stored is not a preset start address. Causes the start address to branch to the address where the instruction is stored.

Subsequently, when copying of the data of the first shared memory area 651 is completed, the fourth boot control unit 545 releases an access right of the first shared memory area 651 and performs a booting procedure.

In FIG. 6, the second to fourth processors 540 are sequentially initialized by the first processor 510, and the data stored in the first shared memory area 651 is sequentially owned through the semaphore control unit 659. As an example of copying to a memory area, in another embodiment of the present invention, after the first processor 510 is booted, the second to fourth processors 540 are simultaneously initialized by the first processor 510. Afterwards, the semaphore control unit 659 may be configured to copy sequentially to its own dedicated memory area.

3 and 6 illustrate that the shared memory regions 250 and 650 include four shared memory regions, but in another embodiment of the present invention, the shared memory includes: Of course, the regions 250 and 650 may be divided into four regions.

According to a multiprocessor booting method using a multi-port memory, a multi-processor system having a multi-port memory and a multi-port memory, when a first processor serving as a master finishes booting, its own dedicated memory area (that is, the first dedicated memory). Data stored in the memory area) to a predetermined shared area. Thereafter, the first processor initializes a second processor serving as a slave, and the initialized second processor acquires exclusive access right to the predetermined shared device, and then owns data stored in the predetermined shared memory area. After copying to the dedicated memory area (ie, the second dedicated memory area), the booting process is performed.

Therefore, booting speed can be improved by performing booting using the multi-port memory, and a plurality of physical transmission lines for data transmission between a processor serving as a master and a processor serving as a slave are not required. The pins can be removed, which reduces the area of the processor chip.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (15)

In the method of booting a multiprocessor having at least one processor, Copying data stored in a first processor dedicated memory area of the multi-port memory to a second processor dedicated memory area of the multi-port memory; Booting the second processor based on the data copied to the second processor dedicated memory area. The method of claim 1, wherein copying data stored in a first processor dedicated memory area of the multi-port memory to a second processor dedicated memory area of the multi-port memory includes: Copying data stored in the first processor dedicated memory area of the multi-port memory to the shared memory area; And And copying the data copied to the shared memory area to a second processor dedicated memory area of the multi-port memory. The method of claim 2, wherein copying data stored in a first processor dedicated memory area of the multi-port memory to a shared memory area comprises: The first processor performing booting based on an initialization program; And Copying data stored in the first processor dedicated memory area to the shared memory area when the first processor finishes booting. The method of claim 2, wherein copying data copied to the shared memory area to a second processor dedicated memory area of the multi-port memory includes: And resetting the second processor based on a reset control signal provided from the first processor. The method of claim 2, wherein copying data copied to the shared memory area to a second processor dedicated memory area of the multi-port memory includes: Obtaining access rights to the shared memory area; Copying data from the shared memory area to the second processor dedicated memory area; And Releasing access to the shared memory area when copying of the data is completed. The method of claim 5, wherein copying data from the shared memory area to the second processor dedicated memory area includes: A method of booting a multiprocessor using multi-port memory, comprising: branching a start address to a stored address at which an instruction to be executed first is stored. The method of claim 1, wherein the data, And copying the data copied to the shared memory area to a second processor dedicated memory area of the multi-port memory. A multiprocessor system comprising at least one processor, A first processor for copying data stored in the first dedicated memory area to a predetermined shared memory area after booting ends; A second processor which copies the data from the predetermined shared memory area to a second dedicated memory area and performs a booting procedure based on the copied boot data; And And a multi-port memory having said first dedicated memory area, said second dedicated memory area, and at least one shared memory area. The method of claim 8, wherein the second processor And reset based on a reset control signal provided from the first processor after power is applied. The method of claim 8, wherein the second processor And a boot control unit releasing the access right to the shared memory area when copying of the data for obtaining the access right to the predetermined shared memory area is completed after the reset is performed. The system of claim 10, wherein the boot control unit A multiprocessor system, characterized by branching the starting address to the address at which the instruction to be executed first is stored. The method of claim 8, wherein the data is And copying data copied to the predetermined shared memory area to the second dedicated memory area. The method of claim 8, wherein the multi-port memory is And a semaphore control unit to guarantee access rights of the first processor and the second processor to the predetermined shared memory area. In the multi-port memory for performing input and output of data with the first processor and the second processor, A dedicated memory area of a first processor, comprising: a first dedicated memory area in which boot data is stored after booting of the first processor is completed; A memory area shared by the first processor and the second processor, the shared memory area to which the boot data is copied by the first processor; And And a second dedicated memory area to which boot data stored in the shared memory area is copied, as a dedicated memory area of the second processor. 15. The system of claim 14, wherein said multi-port memory is And a semaphore control unit to guarantee access rights of the first processor and the second processor to the predetermined shared memory area.

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