KR20080109302A - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device is provided to improve the transmittance by driving a liquid crystal of a piled area where common electrode and a drain electrode are intersected. A gate electrode(42a) of a TFT is connected to a gate line(42). A first conductive pattern includes a common line(46) separating from the gate line. A gate insulating layer(43) covers the first conductive pattern. A data line(44) is intersecting with the gate line and defines the pixel region. A source electrode(44a) of TFT is connected to the data line. A drain electrode(44b) of the TFT is formed according to the connected lines in the pixel region. A common electrode(52) is overlapped among the drain electrode in the other one side. A third conductive pattern is formed on the protective film.

Description

Liquid Crystal Display Device

1 is a view showing an example of a conventional liquid crystal display device.

FIG. 2 is a cross-sectional view illustrating an arrangement structure of a common line, a common electrode, and a pixel electrode for improving transmittance and aperture ratio of the liquid crystal display shown in FIG. 1.

3 is a photograph showing transmission characteristics in region C shown in FIG. 2.

4 is a plan view illustrating a thin film transistor array of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along the lines " I-I '", " II-II' ", " III-III '"

FIG. 6 is a photograph showing transmission characteristics in region C shown in FIG. 5. FIG.

7A and 7B are plan and cross-sectional views illustrating a first mask process of a thin film transistor array according to an exemplary embodiment of the present invention.

8A and 8B are plan and cross-sectional views illustrating a second mask process of a thin film transistor array according to an exemplary embodiment of the present invention.

9A and 9B are plan and cross-sectional views illustrating a third mask process of a thin film transistor array according to an exemplary embodiment of the present invention.

10A and 10B are plan and cross-sectional views illustrating a fourth mask process of a thin film transistor array according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

TFT: thin film transistor 42: gate line

42a: gate electrode 46: common line

46a: common line horizontal portion 46b, 46c: common line vertical portion

43: gate insulating film 44: data line

44a: source electrode 44b: drain electrode

55 semiconductor pattern 53 active layer

54: ohmic contact layer 45: protective film

40: first contact hole 50: second contact hole

48 pixel electrode 48a pixel electrode finger portion

48b: pixel electrode connection portion 52: common electrode

52a: common electrode finger portion 52b: common electrode connection portion

The present invention relates to a liquid crystal display device. In particular, the present invention relates to a liquid crystal display device having improved transmittance.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal displays are roughly classified into a vertical electric field application type and a horizontal electric field application type according to the direction of the electric field for driving the liquid crystal.

In the vertical field application type liquid crystal display, the liquid crystal is driven by a vertical electric field formed between the pixel electrode and the common electrode disposed to face the upper and lower substrates. Such a vertical field application type liquid crystal display device has a large aperture ratio, but has a narrow viewing angle of about 90 degrees.

The horizontal field application type liquid crystal display drives a liquid crystal by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. The horizontal field application liquid crystal display device has an advantage that a viewing angle is wide as about 160 degrees.

Referring to FIG. 1, a horizontal field application type liquid crystal display includes a thin film transistor array 10 and a color filter array 20 facing each other with a liquid crystal 9 interposed therebetween.

The color filter array 20 includes a black matrix 3, a color filter 5, and an overcoat layer 7 sequentially formed on the upper substrate 1. The black matrix 3 serves to prevent light leakage and to prevent light interference between neighboring color filters. The color filter 5 makes it possible to display colors by including patterns of red (R), green (G), and blue (B). The overcoat layer 7 serves to planarize the upper substrate 1 on which the black matrix 3 and the color filter 5 are formed.

The thin film transistor array 10 includes a gate line 12 and a data line 14 crossing each other to define a pixel region, and a thin film transistor TFT connected to the gate line 12 and the data line 14, respectively. And a pixel electrode 18 connected to the thin film transistor TFT, a common electrode 22 parallel to the pixel electrode 18, and a common line 16 connected to the common electrode 22. The common electrode 22 and the pixel electrode 18 include portions formed in the form of slits, and the slits are formed to be parallel to each other. The thin film transistor array 10 is formed on the lower substrate 11.

The thin film transistor TFT supplies the data signal from the data line 14 to the pixel electrode 18 in response to the gate signal from the gate line 12. A horizontal electric field is formed between the pixel electrode 18 supplied with the data signal through the thin film transistor TFT and the common electrode 22 supplied with the reference voltage through the common line 16. The liquid crystal 9 rotates by this horizontal electric field. The degree of rotation of the liquid crystal 9 is adjusted in accordance with the data signal.

A first polarizing plate 33 and a second polarizing plate 31 for transmitting light vibrating in a specific direction are attached to each of an outer surface of the lower substrate 11 and an outer surface of the upper substrate 1. In general, the transmission axis x of the first polarizing plate 33 and the transmission axis y of the second polarizing plate 31 are disposed to be perpendicular to each other.

As described above, the horizontal field application type liquid crystal display realizes an image by controlling the degree of rotation of the liquid crystal 9 by the horizontal electric field so that the light transmittance through the pixel region is changed. In this case, the long axis of the liquid crystal 9 driven by the horizontal electric field may be obliquely arranged on the transmission axes x and y of the first and second polarizing plates 33 and 31 to contribute to the transmittance of the liquid crystal display. . That is, the light transmitted through the liquid crystal 9 having the long axis parallel to or perpendicular to the transmission axes y of the first and second polarizing plates 33 and 31 does not transmit the second polarizing plate 33, and thus, Can not contribute.

Such a horizontal field application liquid crystal display device has been developed in a direction to improve the aperture ratio and transmittance by designing the arrangement structure of the common electrode 22 and the pixel electrode 18 in various ways. As shown in FIG. 2, the common electrode 22 and the pixel electrode 18 are formed side by side on the insulating layers 23 and 25, and the common line 16 for applying a signal to the common electrode 22. Has been proposed to overlap the common electrode 22 and the pixel electrode 18 with the insulating layers 23 and 25 interposed therebetween. In the structure, the common electrode 22 is connected to the common line 16 through a contact hole (not shown) passing through the insulating layers 25 and 23 to receive a reference voltage. When the data signal is supplied to the pixel electrode 18 formed in this structure and the reference voltage is supplied to the common electrode 22 through the common line 16, the liquid crystal disposed in the pixel region is driven to transmit light. At this time, the liquid crystal disposed in the region B between the pixel electrode 18 and the common electrode 22 is driven by a horizontal electric field formed between the pixel electrode 18 and the common electrode 22 to contribute to the transmittance. In addition, the liquid crystal disposed in the region A adjacent to the portion where the common line 16 and the pixel electrode 18 overlap each other is formed by a fringe field formed in a parabolic shape on the common line 16 and the pixel electrode 18. Driven to contribute to transmittance. On the other hand, the liquid crystal disposed in the C region adjacent to the portion where the common line 16 and the common electrode 22 overlap with each other maintains the initial arrangement state because the same voltage is applied to the common line 16 and the common electrode 22. Accordingly, even though the data signal is supplied to the pixel electrode 18 and the reference voltage is supplied to the common electrode 22 through the common line 16, the long axis of the liquid crystal is first and second in the C region as shown in FIG. 3. It is arranged side by side or perpendicular to the transmission axis of the polarizing plate does not transmit light and cannot contribute to the transmittance.

An object of the present invention is to provide a liquid crystal display device having improved transmittance.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention includes a first conductive pattern including a gate line, a gate electrode of a TFT connected to the gate line, and a common line separated from the gate line; A gate insulating layer covering the first conductive pattern; A data line crossing the gate line to define a pixel area, a source electrode of the TFT connected to the data line, and a drain electrode of the TFT formed along two sides connected to each other in the pixel area; 2 conductive patterns; A passivation layer covering the second conductive pattern; And a third electrode pattern connected to one side of the drain electrode and a common electrode connected to the common line and overlapping the other side of the drain electrode, and formed on the passivation layer.

The pixel electrode may include a plurality of pixel electrode finger parts formed parallel to each other; And a pixel electrode connection part connecting the pixel electrode finger parts at one side of the pixel area.

The common electrode may include a plurality of common electrode finger parts parallel to the pixel electrode finger parts; And a common electrode connecting part connecting the common electrode finger parts to the other side of the pixel area.

The common line may include a horizontal portion parallel to the gate line; A first vertical part connected to the horizontal part and overlapping with the pixel electrode connection part; And a second vertical part connected to the horizontal part and overlapping with the common electrode connection part.

The common electrode overlapping the drain electrode is the common electrode connection part.

The common electrode finger portion and the pixel electrode finger portion are alternated in the data line direction, and the common electrode connection portion and the pixel electrode connection portion are parallel to the data line.

A semiconductor pattern including an active layer and an ohmic contact layer overlaps under the second conductive pattern.

The pixel electrode is connected to the drain electrode through a first contact hole through the passivation layer to expose the drain electrode.

The common electrode is connected to the common line through a second contact hole through the passivation layer and the gate insulating layer to expose the common line.

Other objects and advantages of the present invention other than the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 10B.

4 is a plan view illustrating a thin film transistor array of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is a line "I-I '", "II-II'", or "III-III 'shown in FIG. Is a cross-sectional view taken along the line.

The liquid crystal display according to the exemplary embodiment of the present invention includes a thin film transistor array and a color filter array facing each other with a liquid crystal interposed therebetween. The liquid crystal is rotated according to the voltage applied to the pixel electrode 48 included in the thin film transistor array to display an image by adjusting the light transmittance.

In order to drive the liquid crystal, a thin film transistor array according to an exemplary embodiment of the present invention may include a gate line 42 and a data line 44, a gate line 42, and data intersecting with each other, as illustrated in FIGS. 4 and 5. The thin film transistor TFT connected to the line 44, the pixel electrode 48 connected to the thin film transistor TFT, the common electrode 52 parallel to the pixel electrode 48, and the common electrode 52 are connected. Common line 46. This thin film transistor array is formed on the lower substrate 41.

The gate line 42 supplies a gate signal to the thin film transistor TFT, and the data line 44 supplies a data signal to the thin film transistor TFT. The gate line 42 and the data line 44 cross each other to define a pixel area.

The thin film transistor TFT keeps the data signal of the data line 44 charged and maintained in the pixel electrode 48 in response to the gate signal of the gate line 42. To this end, the thin film transistor TFT includes a gate electrode 42a connected to the gate line 42, a source electrode 44a connected to the data line 44, a drain electrode 44b connected to the pixel electrode 48, and a gate. A semiconductor pattern 55 overlapping with the electrode 42a and the gate insulating film 43 is provided.

The semiconductor pattern 55 includes an ohmic contact layer 54 and an active layer 53 superimposed on the ohmic contact layer 54. The active layer 53 is exposed between the source electrode 44a and the drain electrode 44b to form a channel. The ohmic contact layer 54 is formed between the source electrode 44a and the active layer 53 and between the drain electrode 44b and the active layer 53 to ohmic the source and drain electrodes 44a and 44b and the active layer 53. Contact. The semiconductor pattern 55 may overlap the lower portion of the data line 44 due to the manufacturing process.

The pixel electrode 48 is connected to the drain electrode 44b of the thin film transistor TFT through the first contact hole 40 penetrating the passivation layer 45. In this case, the pixel electrode 48 is divided into a plurality of pixel electrode finger parts 48a formed parallel to each other, and a pixel electrode connection part 48b connecting the pixel electrode finger parts 48a.

The common electrode 52 is formed in parallel with the pixel electrode 48. The common electrode 52 is connected to the common line 56 through the second contact hole 50 passing through the passivation layer 45 and the gate insulating layer 43. The common electrode 52 is divided into a plurality of common electrode finger portions 52a formed in parallel with each other, and a common electrode connection portion 52b connecting the common electrode finger portions 52a.

The common electrode finger portion 52a described above is formed in parallel with the pixel electrode finger portion 48a. Accordingly, when a data signal is supplied to the pixel electrode finger portion 48a and a common voltage is supplied to the common electrode finger portion 52a, an electric field is applied to the region B between the pixel electrode finger portion 48a and the common electrode finger portion 52a. Is formed to drive the liquid crystal. The pixel electrode finger portion 48a and the common electrode finger portion 52a are alternately formed in the direction of the data line 44 so that a region where an electric field is formed is formed wider. As a result, the pixel electrode finger portion 48a and the common electrode finger portion 52a are formed to protrude in the horizontal direction. Accordingly, the pixel electrode connector 48b is formed in parallel with the data line 44 to connect the pixel electrode finger portions 48a formed to protrude in the horizontal direction. In addition, the common electrode fingers 52b are formed in parallel with the data line 44 to connect the common electrode fingers 52a formed to protrude in the horizontal direction. The pixel electrode connector 48b and the common electrode connector 52b face each other with the pixel electrode and the common electrode finger portions 48a and 52a interposed therebetween.

The common line 46 is connected to the common electrode 52 to supply a common voltage for driving the liquid crystal to the common electrode 52. The common line 46 is connected to the horizontal portion 46a parallel to the gate line 42, the first vertical portion 46b connected to the horizontal portion 46a and overlapping the pixel electrode connection portion 48b, and the horizontal portion 46a. And a second vertical portion 46c connected to the common electrode connecting portion 52b.

The horizontal part 46a is connected to a pad part (not shown) connected to the driving circuit outside the pixel area to receive a common voltage from the pad part.

The pixel electrode connection portion 48b and the first vertical portion 46b overlap each other with the gate insulating layer 43 and the passivation layer 45 therebetween to form a parabolic fringe field in an area A adjacent to the pixel electrode connection portion 48b. do. The liquid crystals disposed in the area A are driven by a fringe field formed by the data voltage applied to the pixel electrode 48 and the common voltage applied to the common line 46, thereby contributing to the transmittance of the liquid crystal display.

The common electrode connecting portion 52b and the second vertical portion 46c overlap each other with the gate insulating layer 43, the drain electrode 44b, and the passivation layer 45 interposed therebetween and form a parabolic shape in a region C adjacent to the common electrode connecting portion 52b. A fringe field of is formed. The liquid crystals disposed in the region C are driven by a fringe field formed by the data voltage applied to the drain electrode 44b and the common voltage applied to the common electrode 52, thereby contributing to the transmittance of the liquid crystal display.

As described above, the drain electrode 44b according to the exemplary embodiment of the present invention must be connected to the pixel electrode 48 and overlap the common electrode connector 52b. To this end, the drain electrode 44b is formed along two sides connected in the pixel region so that one side of the drain electrode 44b is connected to the pixel electrode 48 and the other side of the drain electrode 44b is the common electrode connection portion 52b. ) And overlap.

As described above, in the liquid crystal display according to the exemplary embodiment, the drain electrode 44b is overlapped between the common line 46 and the common electrode 52 so that the common electrode 52 and the drain electrode 44b overlap each other. The fringe field is formed in the C region. Accordingly, as shown in FIG. 6, the liquid crystal of the C region may be driven by the fringe field, thereby contributing to the transmittance.

The liquid crystal display implements an image by adjusting the light transmittance of the liquid crystal. In the image realization, in order to reduce the phase delay difference of the light passing through the liquid crystal molecules according to the viewing angle direction, the common electrode finger portion 52a and the pixel electrode finger portion 48a refer to the axis along the gate line 42 direction at the center of the pixel region. Finger portions in the first direction and symmetrical directions may be provided. Here, the finger part in the first direction and the finger part in the second direction are connected to each other. As such, when the finger parts 52a and 48a of each electrode are symmetrically formed about the reference axis, the liquid crystal molecules are driven symmetrically about the reference axis. Since the phase delay values of the light transmitted through the symmetrically driven liquid crystal molecules cancel each other, the phase delay difference along the viewing angle direction is reduced, thereby improving the image quality of the liquid crystal display device.

The thin film transistor substrate of the liquid crystal display according to the exemplary embodiment of the present invention having such a configuration is formed by a four mask process as follows.

7A and 7B, a first conductive pattern including a gate line 42, a gate electrode 42a, and a common line 46 is formed on the substrate 41 by a first mask process.

When the first mask process is described in detail, the first conductive layer is deposited on the substrate 41 by a deposition method such as sputtering. Here, as the first conductive layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, or the like is laminated and used in one or more layers. Subsequently, a photoresist pattern is formed by a photolithography process and an etching process using the first mask. When the first conductive layer is etched using the photoresist pattern as a mask, a first conductive pattern including the gate line 42, the gate electrode 42a, and the common line 46 is formed.

Subsequently, as shown in FIGS. 8A and 8B, the gate insulating layer 43 is formed on the substrate 41 to cover the first conductive pattern, and the active layer 53 and the ohmic contact layer 54 are formed by the second mask process. The second conductive pattern including the semiconductor pattern 55 including the data line, the data line 44, the source electrode 44a, and the drain electrode 44b is formed. The semiconductor pattern 55 and the second conductive pattern are formed by one mask process using a diffraction exposure mask or a transflective mask.

Referring to the second mask process in detail, the gate insulating layer 43, the amorphous silicon layer, the amorphous silicon layer doped with the impurity (n + or p +), and the second conductive layer are sequentially formed on the substrate 41. For example, the gate insulating layer 43, the amorphous silicon layer, and the amorphous silicon layer doped with impurities are formed by PECVD, and the source / drain metal layer is formed by sputtering. As the gate insulating layer 43, an inorganic insulating material such as SiOx, SiNx, or the like, and as the second conductive layer, a single layer of metal material such as Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, etc. Or it is laminated | stacked and used more than a bilayer. Then, a photoresist is applied on the second conductive layer, and then the photoresist is exposed and developed by a photolithography process using a diffraction exposure mask. After development, a photoresist pattern relatively thinner than the photoresist pattern of other portions is formed in the channel portion.

Subsequently, an etching process using a photoresist pattern is patterned from the second conductive layer to the amorphous silicon layer. In this process, the source electrode 44a and the drain electrode 44b are patterned to be connected to the data line 44.

Then, the photoresist pattern of the channel portion is removed by ashing the photoresist pattern by an ashing process using an oxygen (O ₂ ) plasma. In addition, the first conductive layer exposed by the etching process using the ashed photoresist pattern and the ohmic contact layer 54 thereunder are removed to separate the source electrode 44a and the drain electrode 44b and the active layer 53. ) Is exposed.

The photoresist pattern remaining on the second conductive pattern is removed by a stripping process.

Thereafter, as shown in FIGS. 9A and 9B, the passivation layer 45 including the first and second contact holes 40 and 50 in a third mask process on the gate insulating layer 43 on which the second conductive pattern is formed. Is formed.

When the third mask process is described in detail, the passivation layer 45 is formed on the gate insulating layer 43 on which the second conductive pattern is formed by a method such as PECVD, spin coating, or spinless coating. As the protective film 45, an inorganic insulating material such as the gate insulating film 43, or an organic insulating material is used. Next, the first contact hole 40 and the common line 46 exposing the drain electrode 44b by patterning the passivation layer 45 and the gate insulating layer 43 by a photolithography process and an etching process using a third mask. The second contact hole 50 is formed to expose the.

Thereafter, as shown in FIGS. 10A and 10B, a third conductive pattern including the pixel electrode 48 and the common electrode 52 is formed on the passivation layer 45 by a fourth mask process. The third conductive pattern is formed by forming a third conductive layer on the passivation layer 45 and then patterning the same by a photolithography process and an etching process using a fourth mask. Here, the third conductive layer may include indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). ) And the like are used.

As described above, in the liquid crystal display according to the exemplary embodiment, the fringe field is formed in the region where the drain electrode and the common electrode overlap by forming the drain electrode so as to be connected to the pixel electrode and overlapping the common electrode. Accordingly, in the liquid crystal display according to the exemplary embodiment of the present invention, since the liquid crystal of the region where the common electrode and the drain electrode overlap is driven by the fringe field, the transmittance may be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A first conductive pattern including a gate line, a gate electrode of a TFT connected to the gate line, and a common line separated from the gate line; A gate insulating layer covering the first conductive pattern; A data line crossing the gate line to define a pixel area, a source electrode of the TFT connected to the data line, and a drain electrode of the TFT formed along two sides connected to each other in the pixel area; 2 conductive patterns; A passivation layer covering the second conductive pattern; And And a third conductive pattern formed on the passivation layer, the pixel electrode connected to one side of the drain electrode and the common electrode connected to the common line and overlapping the other side of the drain electrode. Device. The method of claim 1, The pixel electrode A plurality of pixel electrode finger parts formed parallel to each other; And And a pixel electrode connection part connecting the pixel electrode finger parts to one side of the pixel area. The method of claim 2, The common electrode A plurality of common electrode finger portions parallel to the pixel electrode finger portions; And And a common electrode connecting part connecting the common electrode finger parts to the other side of the pixel area. The method of claim 3, wherein The common line A horizontal portion parallel to the gate line; A first vertical part connected to the horizontal part and overlapping with the pixel electrode connection part; And And a second vertical part connected to the horizontal part and overlapping the common electrode connection part. The method of claim 3, wherein The common electrode overlapping the drain electrode And a common electrode connection part. The method of claim 3, wherein The common electrode finger portion and the pixel electrode finger portion are alternated in the data line direction, And the common electrode connector and the pixel electrode connector are parallel to the data line. The method of claim 1, Under the second conductive pattern And a semiconductor pattern including an active layer and an ohmic contact layer. The method of claim 1, The pixel electrode And a drain electrode connected to the drain electrode through a first contact hole through the passivation layer to expose the drain electrode. The method of claim 1, The common electrode And a second contact hole through the passivation layer and the gate insulating layer to expose the common line.

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