KR20080109233A - Memory device having reduced area - Google Patents

Abstract

A memory device is provided to decrease the height of the memory device and reduce layout by including one precharge block in each MUX block. In a compiled memory device including a plurality of MUX blocks, each MUX block(131, 132) is a precharge block(301, 302) precharging a signal transmitted through a bit line, and a local precharge driver(311), provided in one or two MUX blocks, supplies a control signal to the precharge block. A MUX block include a sense amp and a local sense driver, the local sense driver is shared by the MUX and neighboring one.

Description

Memory device having reduced area

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a view showing an arrangement of a memory device to which the present invention is applied.

FIG. 2 is a view showing a mux partial arrangement of the related art of FIG. 1. FIG.

Figure 3a is a view showing a mux partial arrangement according to an embodiment of the present invention.

3B is a view showing a mux partial arrangement according to another embodiment of the present invention.

4A is a view showing a mux partial arrangement according to another embodiment of the present invention.

4B is a diagram illustrating a local sense driver portion of FIG. 4A.

5 is a view showing a mux block power gating switch unit according to the present invention.

** Description of the symbols for the main parts of the drawings **

101, 102, 103, 104: MUX unit

121, 123: cell array

131, 132, 133: MUX block

141, 142, 143: power gating switch block

301 and 302: precharge circuit

311: local precharge driver

320: local sense driver

331 and 332: sense amplifiers

The present invention relates to a compiled memory device, and more particularly to a compiled memory device having a reduced area.

1 is a view showing an arrangement of a memory device to which the present invention is applied.

Referring to FIG. 1, a general compiled memory device includes a plurality of MUX units 101, 102, 103, and 104, controllers 111 and 112, a driver 125, and a cell array. (Cell array) 121, 123, and a power gating switch unit (151, 153).

The cell array 123 includes a plurality of cells for data storage, and the mux unit 104 selects the plurality of mux blocks 131, 132, and 133 according to the number of cells provided in the cell array 123. Equipped. The power gating switch units 151, 152, 153, 155, and 157 include a plurality of switch blocks 141, 142, and 143 according to the number of the plurality of mux blocks.

Here, the bit cell array 123 is a part for storing data and has a fixed size according to the capacity of the memory device. That is, in a memory device having a predetermined capacity, the cell array 123 having a predetermined size or more should be provided. As the storage capacity of the memory field increases, the size of the cell array portion generally expands left and right. The MUX unit (typically 104) serves to output data stored in one selected cell in the cell array 123. Therefore, when the width of the cell array 123 increases due to an increase in the storage capacity of the memory device, the width of the mux unit 104 also increases.

In the compiled register file memory, a structure that is extended in the horizontal direction as the memory capacity increases is called a fat type. In addition, in such a fat type structure, it is more important to reduce the height rather than the width in order to reduce the overall area.

As described above, in the memory device 100, the portion of the cell array 123 has a fixed size, and thus, the portion 'a', portion 'd', <1>, <2>, and <3 are shown. By reducing the length of the portion, the size of the memory device 100 may be reduced. That is, by reducing the height of the 'a' portion, the 'd' portion, the <1>, and the <2> portion, the total area can be reduced.

In accordance with the trend of miniaturization and low power consumption of semiconductor devices, it will be very important to reduce the height of the above-mentioned parts.

FIG. 2 is a diagram illustrating a conventional mux portion arrangement of FIG. 1. FIG.

Referring to FIG. 2, the mux unit 104 of FIG. 1 includes a plurality of mux blocks 131_0, 132_0, 133_0, and 134_0.

Each mux block (typically, 131_0) includes a precharge circuit 201, a mux 212, a sense amplifier 231, a data latch 214, and an output buffer ( 216.

Roles and operations of the precharge circuit, the mux, the sense amplifier, the data latch, and the output buffer are obvious to those skilled in the art, and thus detailed descriptions thereof will be omitted.

In a conventional semiconductor device, four mux blocks 131_0, 132_0, 133_0, and 134_0 share one local precharge driver 210 and one local sense driver 220. It was. Here, the local precharge driver 210 transmits the first control signal CNTL1 applied from the controller 112 to the respective precharge circuits 201, 202, 203, and 204. The local sense driver 220 transmits the second control signal CNTL2 applied from the controller 112 to the respective sense amplifiers 231, 232, 233, and 234.

Here, the size of the driver 210 or 220 varies depending on the driving current amount. The larger the maximum drive current required, the larger the size of the driver.

In the conventional structure, the local precharge driver 210 has a size of 2.48um / 1.24um, and the local sense driver 220 has a size of 1.62um / 0.68um. In addition, the height of the mux portion 104 as a whole had a size of 20.80um.

The pre-autonomous circuit is activated or deactivated in response to the first control signal CNTL1, and the sense amplifier is activated or deactivated in response to the second control signal CNTL2.

Since the conventional local precharge driver 210 has to transmit the first control signal CNTL1 to four mux blocks, the driving capability has to be large. In addition, since the conventional local sense driver 220 has to transmit the second control signal CNTL2 to four mux blocks, the driving capability has to be large. Increasing the driving capability leads to an increase in the area of the transistor. The buffer (or inverter) used as a driver is composed of a P-type MOS transistor and an N-type MOS transistor. That is, to increase the driving capability, the transistors must be increased in size, which leads to an increase in driver size.

If the driving capability of the driver is not secured above a certain value, distortion of the transmitted signal occurs, and signal transmission cannot be performed properly. In addition, in order to increase the driver driving ability, it is necessary to increase the size of the driver, which leads to an increase in the size of the semiconductor device.

An object of the present invention is to provide a memory device capable of reducing the size of a semiconductor device while maintaining the driving capability of a local driver.

A memory device according to an embodiment of the present invention for achieving the above technical problem is provided with a plurality of mux block.

Each mux block includes a precharge block and a local precharge block.

The precharge block precharges the signal transmitted through the bit line.

The local precharge driver applies a control signal to the precharge block.

The local precharge driver is characterized in that one is provided per one mux block.

Preferably, the mux block further includes a sense amplifier for sensing a data signal output from the precharge block, and a local sense driver for applying a control signal to the sense amplifier.

Preferably, the memory device further includes a power gating switch block connected to the mux block in a one-to-one manner.

The power gating switch block has one first switch connecting the peripheral circuit supply voltage and the peripheral circuit. Another power gating switch block adjacent to the power gating switch block includes a first switch for connecting the peripheral circuit supply voltage and the peripheral circuit and a second switch for connecting the cell array supply voltage and the cell array block. Here, the peripheral circuit is a portion of the memory device except for the cell array block.

The local sense driver is connected one-to-one with the sense amplifier.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

Figure 3a is a view showing a mux partial arrangement according to an embodiment of the present invention.

Referring to FIG. 3A, a mux part according to an embodiment of the present invention includes one local precharge driver 311 for each mux block 131_1. The two mux blocks 131_1 and 132_1 share and use one local sense driver 320. In this case, an inverter, a NAND gate, or the like may be used for the local precharge driver 311 and the local sense driver 320. In the drawing, the inverter 310 is illustrated as a local precharge driver 311 and a buffer is illustrated as a local sense driver 320.

The signal lines 341 and 343 represent bit line pairs (bit lines and complementary bit lines), and data is transmitted to the cell array 123 through the signal lines 341 and 343.

The data latch 335 latches a signal (a signal precharged in the precharge circuit 301 and amplified through the sense amplifier 331) transmitted through the signal lines 341 and 343, and then output buffer 337. ) The output buffer 337 outputs the input signal to an external signal line.

In indicating the size of a semiconductor device, a transistor or a parent transistor (MOSFET) indicates its size in width / length (W / L). In the case of a buffer or inverter device, the size is indicated by the width of the P-type MOS transistor / the width of the N-type MOS transistor (P type MOSFET / N type MOSFET: PW / NW).

Referring to FIGS. 2 and 3A, when one mux block 131_1 includes one local precharge driver 311, the size of a driver to be provided may be reduced in half. Also, the four mux blocks in FIG. 2 share one local sense driver 220, whereas the two mux blocks 131_1 and 132_1 share one local sense driver 320. Therefore, the size of the local precharge driver 210 in FIG. 2 is 2.48um / 1.24um, whereas in FIG. 3A, it is 0.64um / 0.34um. In addition, while the local sense driver 220 of FIG. 2 has a size of 1.62um / 0.68um, it is 0.81um / 0.34um in FIG. 3A. Here, the exact size of the drivers 210 and 220 may vary according to driving current values (driving current values required in the corresponding memory device) and the design rule of the semiconductor device.

Due to the size reduction of the drivers 310 and 320 described above, the height of the entire mux part 104 may be reduced by about 3.01 um compared to the conventional case (20.80 um) to have a height of 17.79 um. That is, the height of the mux portion can be reduced by about 15% as compared with the conventional, thereby resulting in a unique effect of reducing the overall size of the semiconductor device.

3B is a view showing a mux partial arrangement according to another embodiment of the present invention.

In the memory device according to another exemplary embodiment of the present invention, two mux blocks 131_1 and 132_1 share one local precharge driver 360 as compared to FIG. 3A. That is, one local precharge driver 360 is provided per two mux blocks.

All other configurations are the same as in FIG. 3A.

4A is a view showing a mux partial arrangement according to another embodiment of the present invention.

Referring to FIG. 4A, a mux block 131_2 according to another embodiment of the present invention includes two precharge circuits 401 and 403 and two muxes 405 and 407. The local precharge driver 420, the sense amplifier 425, the local sense driver 430, one data latch 441, and one output buffer 443 are provided.

Here, the local pre-autonomous driver 420 and the local sense driver 430 have sizes of 1.24 um / 0.62 um and 0.81 um / 0.34 um, respectively, to reduce the size of the local pre-driver 420 and the local sense driver 430.

4B is a diagram illustrating a local sense driver portion of FIG. 4A.

Referring to FIG. 4B, the local sense driver portion 432 of FIG. 4A may be configured using an inverter. That is, one local sense driver 430 is composed of two inverters 435 and 436.

5 is a view showing a power gating switch unit disposed on a side of a mux block according to the present invention.

1 and 5, the memory device 100 is supplied with power necessary for the operation of the memory device 100 through the power gating switching units a and d parts 151, 153, 155, and 157. The power gating switching unit 153 includes a plurality of power gating switching blocks 141, 142, and 143.

The power supplied to the core including the bit cell array 123 is referred to as VDC, and is supplied to the peripheral circuits of the memory device (the mux part, the control circuit, etc., indicating the rest of the circuit except the core). The power supply is called VDP. One power gating switching block 141 is provided per one mux block 131.

In the memory device, the amount of power supplied to the peripheral circuit is required more than the amount of power supplied to the core. Therefore, in the present invention, one mux block 141 includes only the VDP power supply switch, and the neighbor mux block 142 includes both the VDP power supply switch and the VDC power supply switch. That is, the even block includes both the VDC and the VDP power supply switches, and the odd block includes only the VDP power supply switches.

In FIG. 5, a MOS transistor is used as a switch. The control signal for switching is applied through the gate of the MOS transistor, and the control signal for switching is generated in a controller (not shown) provided inside or outside. In order to supply power to the peripheral circuit, a logic high level control signal is applied to the gates of the 511, 515, and 517 MOS transistors so that the VDP power is supplied.

In this way, the VDP power supply switch is provided only in odd blocks (or even blocks), thereby increasing the area utilization efficiency. In addition, the odd blocks (or even blocks) may include only one VDP power supply switch, thereby reducing the height of the memory device 100.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although certain terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the memory device according to the present invention has one precharge block per mux block, thereby reducing the height and reducing the area of the memory device.

Claims (8)

In a compiled memory device having a number of mux blocks, Each mux block A precharge block for precharging a signal transmitted through the bit line; A local precharge driver for applying a control signal to the precharge block; The local precharge driver is provided with one for each one mux block or two mux blocks. The method of claim 1, wherein the mux block A sense amplifier configured to sense a data signal output from the precharge block; And Further comprising a local sense driver for applying a control signal to the sense amplifier, Wherein the local sense driver is shared by the mux block and a mux block adjacent to the mux block. The method of claim 2, wherein the mux block A latch for latching the sensed data signal; And And an output buffer for outputting the latched signal. The method of claim 1, The local precharge driver is provided one per one mux block, The precharge block has two precharge circuits, And the local precharge driver is connected in common with the two precharge circuits. The method of claim 1, The local precharge driver is provided one per two mux blocks, The precharge block has one precharge circuit, And the local precharge driver is connected in common to two precharge circuits respectively provided in the mux block and the mux block adjacent to the mux block. The method of claim 1, The local precharge driver is provided one per one mux block, The precharge block has one precharge circuit, In each mux block, And the local precharge driver is connected one-to-one with the local precharge driver. The method of claim 1, wherein the size of the local precharge driver is The memory device may vary depending on a current value required by the precharge block. The memory device of claim 1, wherein the memory device Further provided with a plurality of power gating switch blocks are provided in one-to-one connection with the mux block, The power gating switch block A first switch connecting the peripheral circuit supply voltage and the peripheral circuit, The other power gating switch block adjacent to the power gating switch block A first switch for connecting the peripheral circuit supply voltage and the peripheral circuit; And A second switch for connecting the cell array supply voltage and the cell array block, The peripheral circuit is a memory device, characterized in that the remaining portion of the memory device except the cell array block.

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